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[X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in memory expressions like [EAX+ESP]. 

By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register.

There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently.

llvm-svn: 335394
This commit is contained in:
Craig Topper 2018-06-22 21:57:24 +00:00
parent ec7d7f312e
commit 1d707539e4
2 changed files with 12 additions and 0 deletions
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4
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -1858,6 +1858,10 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
unsigned IndexReg = SM.getIndexReg(); unsigned IndexReg = SM.getIndexReg();
unsigned Scale = SM.getScale(); unsigned Scale = SM.getScale();
if (Scale == 1 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
(IndexReg == X86::ESP || IndexReg == X86::RSP))
std::swap(BaseReg, IndexReg);
// If this is a 16-bit addressing mode with the base and index in the wrong // If this is a 16-bit addressing mode with the base and index in the wrong
// order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is // order, swap them so CheckBaseRegAndIndexRegAndScale doesn't fail. It is
// shared with att syntax where order matters. // shared with att syntax where order matters.

8
llvm/test/MC/X86/intel-syntax.s
View File

@ -889,3 +889,11 @@ sysret
// CHECK: sysretq // CHECK: sysretq
sysretq sysretq
// CHECK: leaq (%rsp,%rax), %rax
lea rax, [rax+rsp]
// CHECK: leaq (%rsp,%rax), %rax
lea rax, [rsp+rax]
// CHECK: leal (%esp,%eax), %eax
lea eax, [eax+esp]
// CHECK: leal (%esp,%eax), %eax
lea eax, [esp+eax]