forked from OSchip/llvm-project
[RISCV] Update isLegalAddressingMode for RVV.
RVV instructions only support base register addressing. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D124820
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@ -1014,6 +1014,10 @@ bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
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if (AM.BaseGV)
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return false;
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// RVV instructions only support register addressing.
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if (Subtarget.hasVInstructions() && isa<VectorType>(Ty))
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return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs;
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// Require a 12-bit signed offset.
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if (!isInt<12>(AM.BaseOffs))
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return false;
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@ -596,7 +596,6 @@ define void @struct_gather(i32* noalias nocapture %A, %struct.foo* noalias nocap
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;
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; CHECK-ASM-LABEL: struct_gather:
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; CHECK-ASM: # %bb.0: # %entry
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; CHECK-ASM-NEXT: addi a0, a0, 32
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; CHECK-ASM-NEXT: addi a1, a1, 132
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; CHECK-ASM-NEXT: li a2, 1024
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; CHECK-ASM-NEXT: li a3, 16
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@ -606,13 +605,13 @@ define void @struct_gather(i32* noalias nocapture %A, %struct.foo* noalias nocap
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; CHECK-ASM-NEXT: vsetivli zero, 8, e32, m1, ta, mu
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; CHECK-ASM-NEXT: vlse32.v v8, (a4), a3
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; CHECK-ASM-NEXT: vlse32.v v9, (a1), a3
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; CHECK-ASM-NEXT: addi a4, a0, -32
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; CHECK-ASM-NEXT: vle32.v v10, (a4)
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; CHECK-ASM-NEXT: vle32.v v11, (a0)
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; CHECK-ASM-NEXT: vle32.v v10, (a0)
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; CHECK-ASM-NEXT: addi a4, a0, 32
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; CHECK-ASM-NEXT: vle32.v v11, (a4)
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; CHECK-ASM-NEXT: vadd.vv v8, v10, v8
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; CHECK-ASM-NEXT: vadd.vv v9, v11, v9
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; CHECK-ASM-NEXT: vse32.v v8, (a4)
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; CHECK-ASM-NEXT: vse32.v v9, (a0)
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; CHECK-ASM-NEXT: vse32.v v8, (a0)
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; CHECK-ASM-NEXT: vse32.v v9, (a4)
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; CHECK-ASM-NEXT: addi a2, a2, -16
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; CHECK-ASM-NEXT: addi a0, a0, 64
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; CHECK-ASM-NEXT: addi a1, a1, 256
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@ -838,17 +837,16 @@ define void @gather_of_pointers(i32** noalias nocapture %0, i32** noalias nocapt
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;
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; CHECK-ASM-LABEL: gather_of_pointers:
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; CHECK-ASM: # %bb.0:
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; CHECK-ASM-NEXT: addi a0, a0, 16
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; CHECK-ASM-NEXT: li a2, 1024
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; CHECK-ASM-NEXT: li a3, 40
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; CHECK-ASM-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
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; CHECK-ASM-NEXT: addi a4, a1, 80
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; CHECK-ASM-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-ASM-NEXT: vlse64.v v8, (a1), a3
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; CHECK-ASM-NEXT: addi a4, a1, 80
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; CHECK-ASM-NEXT: vlse64.v v9, (a4), a3
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; CHECK-ASM-NEXT: addi a4, a0, -16
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; CHECK-ASM-NEXT: vse64.v v8, (a4)
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; CHECK-ASM-NEXT: vse64.v v9, (a0)
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; CHECK-ASM-NEXT: vse64.v v8, (a0)
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; CHECK-ASM-NEXT: addi a4, a0, 16
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; CHECK-ASM-NEXT: vse64.v v9, (a4)
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; CHECK-ASM-NEXT: addi a2, a2, -4
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; CHECK-ASM-NEXT: addi a0, a0, 32
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; CHECK-ASM-NEXT: addi a1, a1, 160
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@ -912,14 +910,13 @@ define void @scatter_of_pointers(i32** noalias nocapture %0, i32** noalias nocap
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;
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; CHECK-ASM-LABEL: scatter_of_pointers:
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; CHECK-ASM: # %bb.0:
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; CHECK-ASM-NEXT: addi a1, a1, 16
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; CHECK-ASM-NEXT: li a2, 1024
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; CHECK-ASM-NEXT: li a3, 40
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; CHECK-ASM-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
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; CHECK-ASM-NEXT: addi a4, a1, -16
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; CHECK-ASM-NEXT: vsetivli zero, 2, e64, m1, ta, mu
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; CHECK-ASM-NEXT: vle64.v v8, (a4)
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; CHECK-ASM-NEXT: vle64.v v9, (a1)
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; CHECK-ASM-NEXT: vle64.v v8, (a1)
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; CHECK-ASM-NEXT: addi a4, a1, 16
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; CHECK-ASM-NEXT: vle64.v v9, (a4)
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; CHECK-ASM-NEXT: addi a4, a0, 80
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; CHECK-ASM-NEXT: vsse64.v v8, (a0), a3
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; CHECK-ASM-NEXT: vsse64.v v9, (a4), a3
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