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AMDGPU: Fix emitting encoded calls 

This was failing on out of bounds access to the extra operands
on the s_swappc_b64 beyond those in the instruction definition.

This was working, but somehow regressed within the past few weeks,
although I don't see any obvious commit.

llvm-svn: 309782
This commit is contained in:
Matt Arsenault 2017-08-02 01:42:04 +00:00
parent 6ed7b9bfc0
commit 1d6317c3ad
3 changed files with 30 additions and 4 deletions
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13
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
View File

@ -129,6 +129,7 @@ bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
unsigned Opcode = MI->getOpcode();
const auto *TII = ST.getInstrInfo();
// FIXME: Should be able to handle this with emitPseudoExpansionLowering. We
// need to select it to the subtarget specific version, and there's no way to
@ -137,11 +138,17 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
Opcode = AMDGPU::S_SETPC_B64;
else if (Opcode == AMDGPU::SI_CALL) {
// SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
// called function.
Opcode = AMDGPU::S_SWAPPC_B64;
// called function (which we need to remove here).
OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
MCOperand Dest, Src;
lowerOperand(MI->getOperand(0), Dest);
lowerOperand(MI->getOperand(1), Src);
OutMI.addOperand(Dest);
OutMI.addOperand(Src);
return;
}
int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(Opcode);
int MCOpcode = TII->pseudoToMCOpcode(Opcode);
if (MCOpcode == -1) {
LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "

2
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -278,7 +278,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
return;
// Check for additional literals in SRC0/1/2 (Op 1/2/3)
for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
// Check if this operand should be encoded as [SV]Src
if (!AMDGPU::isSISrcOperand(Desc, i))

19
llvm/test/CodeGen/AMDGPU/call-encoding.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -amdgpu-function-calls -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=fiji -d - | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-function-calls -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=gfx900 -d - | FileCheck -check-prefixes=GCN,GFX9 %s
; XUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -amdgpu-function-calls -filetype=obj -verify-machineinstrs < %s | llvm-objdump -triple amdgcn--amdhsa -mcpu=hawaii -d - | FileCheck -check-prefixes=GCN,CI %s
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64
define void @void_func_void() #1 {
ret void
}
; GCN: s_getpc_b64
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_void_func_void() {
call void @void_func_void()
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind noinline }