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Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 

Patch by James Molloy.

llvm-svn: 137647
This commit is contained in:
Owen Anderson 2011-08-15 20:51:32 +00:00
parent 990dd3d0fb
commit 1d5d2cac8c
2 changed files with 47 additions and 33 deletions
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15
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1094,6 +1094,21 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
unsigned P = fieldFromInstruction32(Insn, 24, 1);
bool writeback = (W == 1) | (P == 0);
// For {LD,ST}RD, Rt must be even, else undefined.
switch (Inst.getOpcode()) {
case ARM::STRD:
case ARM::STRD_PRE:
case ARM::STRD_POST:
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
if (Rt & 0x1) return false;
break;
default:
break;
}
if (writeback) { // Writeback
if (P)
U |= ARMII::IndexModePre << 9;

65
llvm/test/MC/Disassembler/ARM/memory-arm-instructions.txt
View File

@ -104,21 +104,21 @@
#------------------------------------------------------------------------------
# LDRD (immediate)
#------------------------------------------------------------------------------
# CHECK: ldrd r3, r4, [r5
# CHECK: ldrd r7, r8, [r2, #15
# CHECK: ldrd r1, r2, [r9, #32]!
# CHECK: ldrd r0, r1, [r5]
# CHECK: ldrd r8, r9, [r2, #15]
# CHECK: ldrd r2, r3, [r9, #32]!
# CHECK: ldrd r6, r7, [r1], #8
# CHECK: ldrd r1, r2, [r8], #0
# CHECK: ldrd r1, r2, [r8], #0
# CHECK: ldrd r1, r2, [r8], #-0
# CHECK: ldrd r2, r3, [r8], #0
# CHECK: ldrd r2, r3, [r8], #0
# CHECK: ldrd r2, r3, [r8], #-0
0xd0 0x30 0xc5 0xe1
0xdf 0x70 0xc2 0xe1
0xd0 0x12 0xe9 0xe1
0xd0 0x00 0xc5 0xe1
0xdf 0x80 0xc2 0xe1
0xd0 0x22 0xe9 0xe1
0xd8 0x60 0xc1 0xe0
0xd0 0x10 0xc8 0xe0
0xd0 0x10 0xc8 0xe0
0xd0 0x10 0x48 0xe0
0xd0 0x20 0xc8 0xe0
0xd0 0x20 0xc8 0xe0
0xd0 0x20 0x48 0xe0
#------------------------------------------------------------------------------
@ -128,15 +128,15 @@
#------------------------------------------------------------------------------
# LDRD (register)
#------------------------------------------------------------------------------
# CHECK: ldrd r3, r4, [r1, r3
# CHECK: ldrd r4, r5, [r1, r3]
# CHECK: ldrd r4, r5, [r7, r2]!
# CHECK: ldrd r1, r2, [r8], r12
# CHECK: ldrd r1, r2, [r8], -r12
# CHECK: ldrd r0, r1, [r8], r12
# CHECK: ldrd r0, r1, [r8], -r12
0xd3 0x30 0x81 0xe1
0xd3 0x40 0x81 0xe1
0xd2 0x40 0xa7 0xe1
0xdc 0x10 0x88 0xe0
0xdc 0x10 0x08 0xe0
0xdc 0x00 0x88 0xe0
0xdc 0x00 0x08 0xe0
#------------------------------------------------------------------------------
@ -388,21 +388,21 @@
#------------------------------------------------------------------------------
# STRD (immediate)
#------------------------------------------------------------------------------
# CHECK: strd r1, r2, [r4
# CHECK: strd r2, r3, [r6, #1
# CHECK: strd r3, r4, [r7, #22]!
# CHECK: strd r0, r1, [r4]
# CHECK: strd r2, r3, [r6, #1]
# CHECK: strd r2, r3, [r7, #22]!
# CHECK: strd r4, r5, [r8], #7
# CHECK: strd r5, r6, [sp], #0
# CHECK: strd r4, r5, [sp], #0
# CHECK: strd r6, r7, [lr], #0
# CHECK: strd r7, r8, [r9], #-0
# CHECK: strd r6, r7, [r9], #-0
0xf0 0x10 0xc4 0xe1
0xf0 0x00 0xc4 0xe1
0xf1 0x20 0xc6 0xe1
0xf6 0x31 0xe7 0xe1
0xf6 0x21 0xe7 0xe1
0xf7 0x40 0xc8 0xe0
0xf0 0x50 0xcd 0xe0
0xf0 0x40 0xcd 0xe0
0xf0 0x60 0xce 0xe0
0xf0 0x70 0x49 0xe0
0xf0 0x60 0x49 0xe0
#------------------------------------------------------------------------------
@ -412,16 +412,15 @@
#------------------------------------------------------------------------------
# STRD (register)
#------------------------------------------------------------------------------
# CHECK: strd r8, r9, [r4, r1
# CHECK: strd r7, r8, [r3, r9]!
# CHECK: strd r8, r9, [r4, r1]
# CHECK: strd r6, r7, [r3, r9]!
# CHECK: strd r6, r7, [r5], r8
# CHECK: strd r5, r6, [r12], -r10
# CHECK: strd r4, r5, [r12], -r10
0xf1 0x80 0x84 0xe1
0xf9 0x70 0xa3 0xe1
0xf9 0x60 0xa3 0xe1
0xf8 0x60 0x85 0xe0
0xfa 0x50 0x0c 0xe0
0xfa 0x40 0x0c 0xe0
#------------------------------------------------------------------------------
# STRH (immediate)