forked from OSchip/llvm-project
parent
e7174ffcd8
commit
1d56e888c9
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@ -446,14 +446,6 @@ template <typename InsnType>
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static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus
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DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
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@ -639,34 +631,6 @@ static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder) {
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InsnType Rt = fieldFromInstruction(insn, 16, 5);
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InsnType Imm = fieldFromInstruction(insn, 0, 16);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
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Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
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Rt)));
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder) {
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InsnType Rt = fieldFromInstruction(insn, 21, 5);
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InsnType Imm = fieldFromInstruction(insn, 0, 16);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
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Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
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Rt)));
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MI.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <typename InsnType>
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static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
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uint64_t Address,
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