forked from OSchip/llvm-project
[PowerPC] fix potential verification errors
This patch fixes trivial mishandling of 32-bit/64-bit instructions that may cause verification errors with -verify-machineinstrs. llvm-svn: 305984
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@ -521,7 +521,7 @@ void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
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const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
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bool HasBP = RegInfo->hasBasePointer(MF);
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unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
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unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
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unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FP8Reg;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI)
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@ -389,9 +389,14 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
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unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
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if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
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.addReg(PPC::R31)
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.addImm(FrameSize);
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if (LP64)
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
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.addReg(PPC::X31)
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.addImm(FrameSize);
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else
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BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
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.addReg(PPC::R31)
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.addImm(FrameSize);
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} else if (LP64) {
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BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
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.addImm(0)
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@ -478,8 +483,10 @@ void PPCRegisterInfo::lowerDynamicAreaOffset(
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
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bool is64Bit = TM.isPPC64();
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DebugLoc dl = MI.getDebugLoc();
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BuildMI(MBB, II, dl, TII.get(PPC::LI), MI.getOperand(0).getReg())
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BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
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MI.getOperand(0).getReg())
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.addImm(maxCallFrameSize);
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MBB.erase(II);
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}
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