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Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions. 

llvm-svn: 114766
This commit is contained in:
Evan Cheng 2010-09-24 22:03:46 +00:00
parent 264d65924b
commit 1d35ad62cc
5 changed files with 12 additions and 5 deletions
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6
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -2729,9 +2729,11 @@ def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
// Large immediate handling.
// Two piece so_imms.
// FIXME: Expand this in ARMExpandPseudoInsts.
// FIXME: Remove this when we can do generalized remat.
let isReMaterializable = 1 in
def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
Pseudo, IIC_iMOVi,
Pseudo, IIC_iMOVix2,
"mov", "\t$dst, $src",
[(set GPR:$dst, so_imm2part:$src)]>,
Requires<[IsARM, NoV6T2]>;
@ -2754,7 +2756,7 @@ def : ARMPat<(add GPR:$LHS, so_neg_imm2part:$RHS),
// as a single unit instead of having to handle reg inputs.
// FIXME: Remove this when we can do generalized remat.
let isReMaterializable = 1 in
def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVi,
def MOVi32imm : AI1x2<(outs GPR:$dst), (ins i32imm:$src), Pseudo, IIC_iMOVix2,
"movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
[(set GPR:$dst, (i32 imm:$src))]>,
Requires<[IsARM, HasV6T2]>;

6
llvm/lib/Target/ARM/ARMInstrThumb2.td
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@ -2689,10 +2689,10 @@ def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS),
(t2_so_neg_imm2part_2 imm:$RHS))>;
// 32-bit immediate using movw + movt.
// This is a single pseudo instruction to make it re-materializable. Remove
// when we can do generalized remat.
// This is a single pseudo instruction to make it re-materializable.
// FIXME: Remove this when we can do generalized remat.
let isReMaterializable = 1 in
def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
"movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}",
[(set rGPR:$dst, (i32 imm:$src))]>;

1
llvm/lib/Target/ARM/ARMSchedule.td
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@ -23,6 +23,7 @@ def IIC_iCMPr : InstrItinClass;
def IIC_iCMPsi : InstrItinClass;
def IIC_iCMPsr : InstrItinClass;
def IIC_iMOVi : InstrItinClass;
def IIC_iMOVix2 : InstrItinClass;
def IIC_iMOVr : InstrItinClass;
def IIC_iMOVsi : InstrItinClass;
def IIC_iMOVsr : InstrItinClass;

2
llvm/lib/Target/ARM/ARMScheduleA8.td
View File

@ -50,6 +50,8 @@ def CortexA8Itineraries : ProcessorItineraries<
//
// Move instructions, unconditional
InstrItinData<IIC_iMOVi , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVix2,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsi, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsr, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [1, 1, 1]>,

2
llvm/lib/Target/ARM/ARMScheduleA9.td
View File

@ -32,6 +32,8 @@ def CortexA9Itineraries : ProcessorItineraries<
//
// Move instructions, unconditional
InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>,
InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1]>,
InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Pipe0, A9_Pipe1]>], [1, 1]>,
InstrItinData<IIC_iMOVsr , [InstrStage<2, [A9_Pipe0, A9_Pipe1]>], [2, 2, 1]>,