forked from OSchip/llvm-project
PowerPC: Optimize SPE double parameter calling setup
Summary:
SPE passes doubles the same as soft-float, in register pairs as i32
types. This is all handled by the target-independent layer. However,
this is not optimal when splitting or reforming the doubles, as it
pushes to the stack and loads from, on either side.
For instance, to pass a double argument to a function, assuming the
double value is in r5, the sequence currently looks like this:
evstdd 5, X(1)
lwz 3, X(1)
lwz 4, X+4(1)
Likewise, to form a double into r5 from args in r3 and r4:
stw 3, X(1)
stw 4, X+4(1)
evldd 5, X(1)
This optimizes the fence to use SPE instructions. Now, to pass a double
to a function:
mr 4, 5
evmergehi 3, 5, 5
And to form a double into r5 from args in r3 and r4:
evmergelo 5, 3, 4
This is comparable to the way that gcc generates the double splits.
This also fixes a bug with expanding builtins to libcalls, where the
LowerCallTo() code path was generating intermediate illegal type nodes.
Reviewers: nemanjai, hfinkel, joerg
Subscribers: kbarton, jfb, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D54583
llvm-svn: 363526
This commit is contained in:
Justin Hibbits
parent
4f15732067
commit
1d1cf30b73
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@ -105,4 +105,58 @@ static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
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return false;
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}
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// Split F64 arguments into two 32-bit consecutive registers.
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static bool CC_PPC32_SPE_CustomSplitFP64(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 };
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static const MCPhysReg LoRegList[] = { PPC::R4, PPC::R6, PPC::R8, PPC::R10 };
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// Try to get the first register.
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unsigned Reg = State.AllocateReg(HiRegList);
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if (!Reg)
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return false;
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unsigned i;
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for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
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if (HiRegList[i] == Reg)
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break;
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unsigned T = State.AllocateReg(LoRegList[i]);
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(void)T;
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assert(T == LoRegList[i] && "Could not allocate register");
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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// Same as above, but for return values, so only allocate for R3 and R4
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static bool CC_PPC32_SPE_RetF64(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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static const MCPhysReg HiRegList[] = { PPC::R3 };
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static const MCPhysReg LoRegList[] = { PPC::R4 };
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// Try to get the first register.
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unsigned Reg = State.AllocateReg(HiRegList, LoRegList);
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if (!Reg)
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return false;
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unsigned i;
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for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i)
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if (HiRegList[i] == Reg)
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break;
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
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LocVT, LocInfo));
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return true;
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}
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#include "PPCGenCallingConv.inc"
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@ -91,7 +91,7 @@ def RetCC_PPC : CallingConv<[
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CCIfSubtarget<"hasSPE()",
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CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
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CCIfSubtarget<"hasSPE()",
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CCIfType<[f64], CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>,
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CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>,
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// For P9, f128 are passed in vector registers.
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CCIfType<[f128],
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@ -182,6 +182,9 @@ def CC_PPC32_SVR4_Common : CallingConv<[
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CCIfType<[i32],
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CCIfSplit<CCIfNotSubtarget<"useSoftFloat()",
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CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>>,
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CCIfType<[f64],
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CCIfSubtarget<"hasSPE()",
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CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
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CCIfSplit<CCIfSubtarget<"useSoftFloat()",
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CCIfOrigArgWasPPCF128<CCCustom<
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"CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128">>>>,
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@ -202,7 +205,7 @@ def CC_PPC32_SVR4_Common : CallingConv<[
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CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>>,
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CCIfType<[f64],
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CCIfSubtarget<"hasSPE()",
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CCAssignToReg<[S3, S4, S5, S6, S7, S8, S9, S10]>>>,
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CCCustom<"CC_PPC32_SPE_CustomSplitFP64">>>,
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CCIfType<[f32],
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CCIfSubtarget<"hasSPE()",
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CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>>,
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@ -1269,22 +1269,6 @@ unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
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return Align;
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}
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unsigned PPCTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv:: ID CC,
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EVT VT) const {
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if (Subtarget.hasSPE() && VT == MVT::f64)
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return 2;
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return PPCTargetLowering::getNumRegisters(Context, VT);
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}
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MVT PPCTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
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CallingConv:: ID CC,
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EVT VT) const {
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if (Subtarget.hasSPE() && VT == MVT::f64)
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return MVT::i32;
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return PPCTargetLowering::getRegisterType(Context, VT);
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}
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bool PPCTargetLowering::useSoftFloat() const {
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return Subtarget.useSoftFloat();
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}
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@ -1402,6 +1386,8 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::QBFLT: return "PPCISD::QBFLT";
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case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
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case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
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case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
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case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
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case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
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case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
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case PPCISD::FP_EXTEND_LH: return "PPCISD::FP_EXTEND_LH";
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@ -3427,7 +3413,7 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
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// Reserve space for the linkage area on the stack.
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unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
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CCInfo.AllocateStack(LinkageSize, PtrByteSize);
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if (useSoftFloat() || hasSPE())
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if (useSoftFloat())
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CCInfo.PreAnalyzeFormalArguments(Ins);
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CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
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@ -3460,7 +3446,8 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
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if (Subtarget.hasVSX())
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RC = &PPC::VSFRCRegClass;
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else if (Subtarget.hasSPE())
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RC = &PPC::SPERCRegClass;
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// SPE passes doubles in GPR pairs.
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RC = &PPC::GPRCRegClass;
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else
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RC = &PPC::F8RCRegClass;
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break;
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@ -3484,13 +3471,26 @@ SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
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break;
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}
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// Transform the arguments stored in physical registers into virtual ones.
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unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
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ValVT == MVT::i1 ? MVT::i32 : ValVT);
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if (ValVT == MVT::i1)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
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SDValue ArgValue;
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// Transform the arguments stored in physical registers into
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// virtual ones.
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if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
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assert(i + 1 < e && "No second half of double precision argument");
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unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
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unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
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SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
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SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
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if (!Subtarget.isLittleEndian())
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std::swap (ArgValueLo, ArgValueHi);
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ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
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ArgValueHi);
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} else {
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unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
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ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
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ValVT == MVT::i1 ? MVT::i32 : ValVT);
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if (ValVT == MVT::i1)
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ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
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}
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InVals.push_back(ArgValue);
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} else {
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@ -5135,10 +5135,27 @@ SDValue PPCTargetLowering::LowerCallResult(
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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SDValue Val = DAG.getCopyFromReg(Chain, dl,
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VA.getLocReg(), VA.getLocVT(), InFlag);
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Chain = Val.getValue(1);
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InFlag = Val.getValue(2);
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SDValue Val;
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if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
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SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
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InFlag);
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Chain = Lo.getValue(1);
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InFlag = Lo.getValue(2);
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VA = RVLocs[++i]; // skip ahead to next loc
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SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
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InFlag);
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Chain = Hi.getValue(1);
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InFlag = Hi.getValue(2);
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if (!Subtarget.isLittleEndian())
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std::swap (Lo, Hi);
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Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
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} else {
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Val = DAG.getCopyFromReg(Chain, dl,
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VA.getLocReg(), VA.getLocVT(), InFlag);
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Chain = Val.getValue(1);
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InFlag = Val.getValue(2);
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}
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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@ -5459,12 +5476,15 @@ SDValue PPCTargetLowering::LowerCall_32SVR4(
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bool seenFloatArg = false;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, j = 0, e = ArgLocs.size();
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// i - Tracks the index into the list of registers allocated for the call
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// RealArgIdx - Tracks the index into the list of actual function arguments
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// j - Tracks the index into the list of byval arguments
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for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size();
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i != e;
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++i) {
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++i, ++RealArgIdx) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = OutVals[i];
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ISD::ArgFlagsTy Flags = Outs[i].Flags;
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SDValue Arg = OutVals[RealArgIdx];
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ISD::ArgFlagsTy Flags = Outs[RealArgIdx].Flags;
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if (Flags.isByVal()) {
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// Argument is an aggregate which is passed by value, thus we need to
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@ -5513,7 +5533,17 @@ SDValue PPCTargetLowering::LowerCall_32SVR4(
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if (VA.isRegLoc()) {
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seenFloatArg |= VA.getLocVT().isFloatingPoint();
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// Put argument in a physical register.
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) {
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bool IsLE = Subtarget.isLittleEndian();
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SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
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DAG.getIntPtrConstant(IsLE ? 0 : 1, dl));
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0)));
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SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
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DAG.getIntPtrConstant(IsLE ? 1 : 0, dl));
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RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(),
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SVal.getValue(0)));
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} else
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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// Put argument in the parameter list area of the current stack frame.
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assert(VA.isMemLoc());
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@ -6781,11 +6811,11 @@ PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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SmallVector<SDValue, 4> RetOps(1, Chain);
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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for (unsigned i = 0, RealResIdx = 0; i != RVLocs.size(); ++i, ++RealResIdx) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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SDValue Arg = OutVals[i];
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SDValue Arg = OutVals[RealResIdx];
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switch (VA.getLocInfo()) {
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default: llvm_unreachable("Unknown loc info!");
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@ -6800,8 +6830,21 @@ PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
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break;
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}
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
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if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
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bool isLittleEndian = Subtarget.isLittleEndian();
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// Legalize ret f64 -> ret 2 x i32.
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SDValue SVal =
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DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
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DAG.getIntPtrConstant(isLittleEndian ? 0 : 1, dl));
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), SVal, Flag);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
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DAG.getIntPtrConstant(isLittleEndian ? 1 : 0, dl));
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Flag = Chain.getValue(1);
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VA = RVLocs[++i]; // skip ahead to next loc
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), SVal, Flag);
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} else
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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}
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@ -194,6 +194,15 @@ namespace llvm {
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/// Direct move of 2 consecutive GPR to a VSX register.
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BUILD_FP128,
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/// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and
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/// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is
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/// unsupported for this target.
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/// Merge 2 GPRs to a single SPE register.
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BUILD_SPE64,
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/// Extract SPE register component, second argument is high or low.
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EXTRACT_SPE,
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/// Extract a subvector from signed integer vector and convert to FP.
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/// It is primarily used to convert a (widened) illegal integer vector
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/// type to a legal floating point vector type.
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@ -908,14 +917,6 @@ namespace llvm {
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unsigned JTI,
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MCContext &Ctx) const override;
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unsigned getNumRegistersForCallingConv(LLVMContext &Context,
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CallingConv:: ID CC,
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EVT VT) const override;
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MVT getRegisterTypeForCallingConv(LLVMContext &Context,
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CallingConv:: ID CC,
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EVT VT) const override;
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private:
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struct ReuseLoadInfo {
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SDValue Ptr;
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@ -230,6 +230,18 @@ def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128",
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SDTCisSameAs<1,2>]>,
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[]>;
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def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64",
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SDTypeProfile<1, 2,
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[SDTCisVT<0, f64>, SDTCisVT<1,i32>,
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SDTCisVT<1,i32>]>,
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[]>;
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def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE",
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SDTypeProfile<1, 2,
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[SDTCisVT<0, i32>, SDTCisVT<1, f64>,
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SDTCisPtrTy<2>]>,
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[]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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@ -511,7 +511,7 @@ def EVLWWSPLATX : EVXForm_1<792, (outs sperc:$RT), (ins memrr:$src),
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def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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"evmergehi $RT, $RA, $RB", IIC_VecGeneral, []>;
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def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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def EVMERGELO : EVXForm_1<557, (outs sperc:$RT), (ins gprc:$RA, gprc:$RB),
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"evmergelo $RT, $RA, $RB", IIC_VecGeneral, []>;
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def EVMERGEHILO : EVXForm_1<558, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
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"evmergehilo $RT, $RA, $RB", IIC_VecGeneral, []>;
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@ -886,4 +886,14 @@ def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
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(SELECT_SPE (CRANDC $lhs, $rhs), $tval, $fval)>;
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def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)),
|
||||
(SELECT_SPE (CRXOR $lhs, $rhs), $tval, $fval)>;
|
||||
|
||||
|
||||
def : Pat<(f64 (PPCbuild_spe64 i32:$rB, i32:$rA)),
|
||||
(f64 (COPY_TO_REGCLASS (EVMERGELO $rA, $rB), SPERC))>;
|
||||
|
||||
def : Pat<(i32 (PPCextract_spe f64:$rA, 1)),
|
||||
(i32 (EXTRACT_SUBREG (EVMERGEHI $rA, $rA), sub_32))>;
|
||||
def : Pat<(i32 (PPCextract_spe f64:$rA, 0)),
|
||||
(i32 (EXTRACT_SUBREG $rA, sub_32))>;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -472,10 +472,8 @@ entry:
|
|||
; CHECK-LABEL: test_dselect
|
||||
; CHECK: andi.
|
||||
; CHECK: bc
|
||||
; CHECK: evldd
|
||||
; CHECK: b
|
||||
; CHECK: evldd
|
||||
; CHECK: evstdd
|
||||
; CHECK: evor
|
||||
; CHECK: evmergehi
|
||||
; CHECK: blr
|
||||
}
|
||||
|
||||
|
|
@ -519,7 +517,7 @@ entry:
|
|||
%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
|
||||
ret i32 %1
|
||||
; CHECK-LABEL: test_dasmconst
|
||||
; CHECK: evldd
|
||||
; CHECK: evmergelo
|
||||
; CHECK: #APP
|
||||
; CHECK: efdctsi
|
||||
; CHECK: #NO_APP
|
||||
|
|
|
|||
Loading…
Reference in New Issue