forked from OSchip/llvm-project
[InstCombine][X86][XOP] Combine XOP integer vector comparisons to native IR
We now have lowering support for XOP PCOM/PCOMU instructions. llvm-svn: 249977
This commit is contained in:
Simon Pilgrim
parent
52d47e5704
commit
1d1c56e2df
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@ -446,6 +446,43 @@ static Value *SimplifyX86vperm2(const IntrinsicInst &II,
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return nullptr;
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}
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/// Decode XOP integer vector comparison intrinsics.
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static Value *SimplifyX86vpcom(const IntrinsicInst &II,
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InstCombiner::BuilderTy &Builder, bool IsSigned) {
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if (auto *CInt = dyn_cast<ConstantInt>(II.getArgOperand(2))) {
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uint64_t Imm = CInt->getZExtValue() & 0x7;
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VectorType *VecTy = cast<VectorType>(II.getType());
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CmpInst::Predicate Pred = ICmpInst::BAD_ICMP_PREDICATE;
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switch (Imm) {
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case 0x0:
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Pred = IsSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT;
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break;
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case 0x1:
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Pred = IsSigned ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE;
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break;
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case 0x2:
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Pred = IsSigned ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT;
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break;
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case 0x3:
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Pred = IsSigned ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE;
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break;
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case 0x4:
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Pred = ICmpInst::ICMP_EQ; break;
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case 0x5:
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Pred = ICmpInst::ICMP_NE; break;
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case 0x6:
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return ConstantInt::getSigned(VecTy, 0); // FALSE
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case 0x7:
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return ConstantInt::getSigned(VecTy, -1); // TRUE
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}
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if (Value *Cmp = Builder.CreateICmp(Pred, II.getArgOperand(0), II.getArgOperand(1)))
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return Builder.CreateSExtOrTrunc(Cmp, VecTy);
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}
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return nullptr;
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}
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/// visitCallInst - CallInst simplification. This mostly only handles folding
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/// of intrinsic instructions. For normal calls, it allows visitCallSite to do
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/// the heavy lifting.
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@ -1252,6 +1289,22 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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return ReplaceInstUsesWith(*II, V);
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break;
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case Intrinsic::x86_xop_vpcomb:
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case Intrinsic::x86_xop_vpcomd:
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case Intrinsic::x86_xop_vpcomq:
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case Intrinsic::x86_xop_vpcomw:
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if (Value *V = SimplifyX86vpcom(*II, *Builder, true))
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return ReplaceInstUsesWith(*II, V);
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break;
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case Intrinsic::x86_xop_vpcomub:
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case Intrinsic::x86_xop_vpcomud:
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case Intrinsic::x86_xop_vpcomuq:
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case Intrinsic::x86_xop_vpcomuw:
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if (Value *V = SimplifyX86vpcom(*II, *Builder, false))
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return ReplaceInstUsesWith(*II, V);
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break;
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case Intrinsic::ppc_altivec_vperm:
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// Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant.
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// Note that ppc_altivec_vperm has a big-endian bias, so when creating
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@ -0,0 +1,209 @@
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define <2 x i64> @cmp_slt_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: @cmp_slt_v2i64
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; CHECK-NEXT: %1 = icmp slt <2 x i64> %a, %b
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; CHECK-NEXT: %2 = sext <2 x i1> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%1 = tail call <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define <2 x i64> @cmp_ult_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: @cmp_ult_v2i64
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; CHECK-NEXT: %1 = icmp ult <2 x i64> %a, %b
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; CHECK-NEXT: %2 = sext <2 x i1> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%1 = tail call <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define <2 x i64> @cmp_sle_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: @cmp_sle_v2i64
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; CHECK-NEXT: %1 = icmp sle <2 x i64> %a, %b
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; CHECK-NEXT: %2 = sext <2 x i1> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%1 = tail call <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define <2 x i64> @cmp_ule_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: @cmp_ule_v2i64
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; CHECK-NEXT: %1 = icmp ule <2 x i64> %a, %b
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; CHECK-NEXT: %2 = sext <2 x i1> %1 to <2 x i64>
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; CHECK-NEXT: ret <2 x i64> %2
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%1 = tail call <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %1
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}
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define <4 x i32> @cmp_sgt_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @cmp_sgt_v4i32
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; CHECK-NEXT: %1 = icmp sgt <4 x i32> %a, %b
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; CHECK-NEXT: %2 = sext <4 x i1> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%1 = tail call <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %1
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}
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define <4 x i32> @cmp_ugt_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @cmp_ugt_v4i32
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; CHECK-NEXT: %1 = icmp ugt <4 x i32> %a, %b
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; CHECK-NEXT: %2 = sext <4 x i1> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%1 = tail call <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %1
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}
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define <4 x i32> @cmp_sge_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @cmp_sge_v4i32
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; CHECK-NEXT: %1 = icmp sge <4 x i32> %a, %b
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; CHECK-NEXT: %2 = sext <4 x i1> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%1 = tail call <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %1
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}
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define <4 x i32> @cmp_uge_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @cmp_uge_v4i32
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; CHECK-NEXT: %1 = icmp uge <4 x i32> %a, %b
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; CHECK-NEXT: %2 = sext <4 x i1> %1 to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %2
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%1 = tail call <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %1
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}
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define <8 x i16> @cmp_seq_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: @cmp_seq_v8i16
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; CHECK-NEXT: %1 = icmp eq <8 x i16> %a, %b
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; CHECK-NEXT: %2 = sext <8 x i1> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%1 = tail call <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %1
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}
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define <8 x i16> @cmp_ueq_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: @cmp_ueq_v8i16
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; CHECK-NEXT: %1 = icmp eq <8 x i16> %a, %b
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; CHECK-NEXT: %2 = sext <8 x i1> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%1 = tail call <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %1
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}
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define <8 x i16> @cmp_sne_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: @cmp_sne_v8i16
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; CHECK-NEXT: %1 = icmp ne <8 x i16> %a, %b
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; CHECK-NEXT: %2 = sext <8 x i1> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%1 = tail call <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %1
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}
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define <8 x i16> @cmp_une_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: @cmp_une_v8i16
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; CHECK-NEXT: %1 = icmp ne <8 x i16> %a, %b
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; CHECK-NEXT: %2 = sext <8 x i1> %1 to <8 x i16>
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; CHECK-NEXT: ret <8 x i16> %2
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%1 = tail call <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %1
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}
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define <16 x i8> @cmp_strue_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: @cmp_strue_v16i8
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; CHECK-NEXT: ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%1 = tail call <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %1
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}
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define <16 x i8> @cmp_utrue_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: @cmp_utrue_v16i8
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; CHECK-NEXT: ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%1 = tail call <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %1
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}
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define <16 x i8> @cmp_sfalse_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: @cmp_sfalse_v16i8
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; CHECK-NEXT: ret <16 x i8> zeroinitializer
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%1 = tail call <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %1
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}
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define <16 x i8> @cmp_ufalse_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: @cmp_ufalse_v16i8
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; CHECK-NEXT: ret <16 x i8> zeroinitializer
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%1 = tail call <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %1
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}
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declare <16 x i8> @llvm.x86.xop.vpcomltb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomltw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomltd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomltub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomltuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomltud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomleb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomlew(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomled(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomleub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomleuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomleud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomgtb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomgtw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomgtq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomgtub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomgtuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomgtuq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomgeb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomgew(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomgeq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomgeub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomgeuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomgeuq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomeqd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomeqq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomequb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomequd(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomequq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomneb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomned(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomneq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomneub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomneud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomneuq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomfalsew(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomfalsed(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomfalseq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomfalseuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomfalseud(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomfalseuq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8>, <16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomtrued(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.x86.xop.vpcomtrueq(<2 x i64>, <2 x i64>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomtruew(<8 x i16>, <8 x i16>) nounwind readnone
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declare <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.x86.xop.vpcomtrueuw(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.x86.xop.vpcomtrueud(<4 x i32>, <4 x i32>) nounwind readnone
|
||||
declare <2 x i64> @llvm.x86.xop.vpcomtrueuq(<2 x i64>, <2 x i64>) nounwind readnone
|
||||
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Reference in New Issue