maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Disable the pattern isel 

llvm-svn: 15787
This commit is contained in:
Chris Lattner 2004-08-15 23:02:17 +00:00
parent 9f714c8d35
commit 1d088db15e
4 changed files with 13 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
llvm/lib/Target/X86/Makefile
View File

@ -15,8 +15,7 @@ TARGET = X86
# Make sure that tblgen is run, first thing.
$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
X86GenRegisterInfo.inc X86GenInstrNames.inc \
X86GenInstrInfo.inc X86GenAsmWriter.inc \
X86GenInstrSelector.inc
X86GenInstrInfo.inc X86GenAsmWriter.inc
TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \
$(SourceDir)/../Target.td
@ -45,9 +44,9 @@ $(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td assembly writer with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-asm-writer -o $@
$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction selector with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
#$(TARGET)GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
# @echo "Building $(TARGET).td instruction selector with tblgen"
# $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
clean::
$(VERB) rm -f *.inc

6
llvm/lib/Target/X86/X86.h
View File

@ -29,12 +29,6 @@ class IntrinsicLowering;
///
FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM);
/// createX86PatternInstructionSelector - This pass converts an LLVM function
/// into a machine code representation using pattern matching and a machine
/// description file.
///
FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM);
/// createX86SSAPeepholeOptimizerPass - Create a pass to perform SSA-based X86
/// specific peephole optimizations.
///

7
llvm/lib/Target/X86/X86ISelPattern.cpp
View File

@ -14,6 +14,11 @@
//
//===----------------------------------------------------------------------===//
/// NOTE: This whole selector is completely disabled. This is only retained
/// for historical interest and future work. It will probably change
/// substantially in the future.
#if 0
#include "X86.h"
#include "llvm/Pass.h"
#include "llvm/Function.h"
@ -122,3 +127,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
}
#endif

16
llvm/lib/Target/X86/X86TargetMachine.cpp
View File

@ -26,12 +26,6 @@
using namespace llvm;
namespace {
#if 0 // FIXME: This will be used in the future.
cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
cl::desc("Use the 'simple' X86 instruction selector"));
#else
static const bool NoPatternISel = true;
#endif
cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
cl::desc("Disable the ssa-based peephole optimizer "
"(defaults to disabled)"));
@ -87,10 +81,7 @@ bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
if (NoPatternISel)
PM.add(createX86SimpleInstructionSelector(*this));
else
PM.add(createX86PatternInstructionSelector(*this));
PM.add(createX86SimpleInstructionSelector(*this));
// Run optional SSA-based machine code optimizations next...
if (!NoSSAPeephole)
@ -145,10 +136,7 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
if (NoPatternISel)
PM.add(createX86SimpleInstructionSelector(TM));
else
PM.add(createX86PatternInstructionSelector(TM));
PM.add(createX86SimpleInstructionSelector(TM));
// Run optional SSA-based machine code optimizations next...
if (!NoSSAPeephole)