VirtRegMap: Add pass option to not clear virt regs

In a future change it will be possible to run register
allocation with a specific set of register classes,
so some of the remaining virtual registers will still
be meaningful.
This commit is contained in:
Matt Arsenault 2018-10-25 14:45:55 -07:00
parent e6701e575c
commit 1cf3d68f97
2 changed files with 21 additions and 7 deletions

View File

@ -150,6 +150,7 @@ namespace llvm {
/// VirtRegRewriter pass. Rewrite virtual registers to physical registers as /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
/// assigned in VirtRegMap. /// assigned in VirtRegMap.
extern char &VirtRegRewriterID; extern char &VirtRegRewriterID;
FunctionPass *createVirtRegRewriter(bool ClearVirtRegs = true);
/// UnreachableMachineBlockElimination - This pass removes unreachable /// UnreachableMachineBlockElimination - This pass removes unreachable
/// machine basic blocks. /// machine basic blocks.

View File

@ -181,6 +181,7 @@ class VirtRegRewriter : public MachineFunctionPass {
SlotIndexes *Indexes; SlotIndexes *Indexes;
LiveIntervals *LIS; LiveIntervals *LIS;
VirtRegMap *VRM; VirtRegMap *VRM;
bool ClearVirtRegs;
void rewrite(); void rewrite();
void addMBBLiveIns(); void addMBBLiveIns();
@ -192,17 +193,22 @@ class VirtRegRewriter : public MachineFunctionPass {
public: public:
static char ID; static char ID;
VirtRegRewriter(bool ClearVirtRegs_ = true) :
VirtRegRewriter() : MachineFunctionPass(ID) {} MachineFunctionPass(ID),
ClearVirtRegs(ClearVirtRegs_) {}
void getAnalysisUsage(AnalysisUsage &AU) const override; void getAnalysisUsage(AnalysisUsage &AU) const override;
bool runOnMachineFunction(MachineFunction&) override; bool runOnMachineFunction(MachineFunction&) override;
MachineFunctionProperties getSetProperties() const override { MachineFunctionProperties getSetProperties() const override {
if (ClearVirtRegs) {
return MachineFunctionProperties().set( return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs); MachineFunctionProperties::Property::NoVRegs);
} }
return MachineFunctionProperties();
}
}; };
} // end anonymous namespace } // end anonymous namespace
@ -257,10 +263,13 @@ bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
// Write out new DBG_VALUE instructions. // Write out new DBG_VALUE instructions.
getAnalysis<LiveDebugVariables>().emitDebugValues(VRM); getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
if (ClearVirtRegs) {
// All machine operands and other references to virtual registers have been // All machine operands and other references to virtual registers have been
// replaced. Remove the virtual registers and release all the transient data. // replaced. Remove the virtual registers and release all the transient data.
VRM->clearAllVirt(); VRM->clearAllVirt();
MRI->clearVirtRegs(); MRI->clearVirtRegs();
}
return true; return true;
} }
@ -591,3 +600,7 @@ void VirtRegRewriter::rewrite() {
} }
} }
} }
FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
return new VirtRegRewriter(ClearVirtRegs);
}