forked from OSchip/llvm-project
remove unnecessary forward declaration; NFC
llvm-svn: 243328
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aa99a2304d
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@ -67,10 +67,6 @@ static cl::opt<bool> ExperimentalVectorWideningLegalization(
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"rather than promotion."),
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cl::Hidden);
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// Forward declarations.
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static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
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SDValue V2);
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X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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const X86Subtarget &STI)
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: TargetLowering(TM), Subtarget(&STI) {
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@ -2867,6 +2863,18 @@ static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
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return Chain;
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}
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/// Returns a vector_shuffle mask for an movs{s|d}, movd
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/// operation of specified width.
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static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
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SDValue V2) {
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unsigned NumElems = VT.getVectorNumElements();
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SmallVector<int, 8> Mask;
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Mask.push_back(NumElems);
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for (unsigned i = 1; i != NumElems; ++i)
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Mask.push_back(i);
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return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
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}
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SDValue
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X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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@ -4399,18 +4407,6 @@ static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
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return DAG.getBitcast(VT, Vec);
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}
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/// Returns a vector_shuffle mask for an movs{s|d}, movd
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/// operation of specified width.
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static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
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SDValue V2) {
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unsigned NumElems = VT.getVectorNumElements();
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SmallVector<int, 8> Mask;
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Mask.push_back(NumElems);
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for (unsigned i = 1; i != NumElems; ++i)
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Mask.push_back(i);
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return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
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}
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/// Returns a vector_shuffle node for an unpackl operation.
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static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
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SDValue V2) {
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