forked from OSchip/llvm-project
Change the operand orders to t_addrmode_s* to make it easier to morph
instructions that use these address modes to instructions that use t_addrmode_sp. llvm-svn: 33651
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7fa6964dc2
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1cd3c0efb8
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@ -523,7 +523,8 @@ void
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ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
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unsigned Scale) {
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const MachineOperand &MO1 = MI->getOperand(Op);
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const MachineOperand &MO2 = MI->getOperand(Op+2);
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const MachineOperand &MO2 = MI->getOperand(Op+1);
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const MachineOperand &MO3 = MI->getOperand(Op+2);
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if (!MO1.isRegister()) { // FIXME: This is for CP entries, but isn't right.
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printOperand(MI, Op);
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@ -531,7 +532,9 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
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}
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O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
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if (unsigned ImmOffs = MO2.getImm()) {
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if (MO3.getReg())
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O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).Name;
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else if (unsigned ImmOffs = MO2.getImm()) {
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O << ", #" << ImmOffs;
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if (Scale > 1)
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O << " * " << Scale;
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@ -541,24 +544,15 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
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void
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ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
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if (MI->getOperand(Op+1).getReg())
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printThumbAddrModeRROperand(MI, Op);
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else
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printThumbAddrModeRI5Operand(MI, Op, 1);
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printThumbAddrModeRI5Operand(MI, Op, 1);
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}
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void
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ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
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if (MI->getOperand(Op+1).getReg())
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printThumbAddrModeRROperand(MI, Op);
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else
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printThumbAddrModeRI5Operand(MI, Op, 2);
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printThumbAddrModeRI5Operand(MI, Op, 2);
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}
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void
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ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
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if (MI->getOperand(Op+1).getReg())
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printThumbAddrModeRROperand(MI, Op);
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else
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printThumbAddrModeRI5Operand(MI, Op, 4);
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printThumbAddrModeRI5Operand(MI, Op, 4);
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}
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void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
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@ -72,14 +72,14 @@ public:
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bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset);
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bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm);
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SDOperand &Base, SDOperand &OffImm,
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SDOperand &Offset);
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bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm);
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SDOperand &OffImm, SDOperand &Offset);
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bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm);
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SDOperand &OffImm, SDOperand &Offset);
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bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm);
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SDOperand &OffImm, SDOperand &Offset);
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bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &OffImm);
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@ -375,7 +375,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
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bool
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ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
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unsigned Scale, SDOperand &Base,
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SDOperand &Offset, SDOperand &OffImm) {
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SDOperand &OffImm, SDOperand &Offset) {
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if (Scale == 4) {
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SDOperand TmpBase, TmpOffImm;
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if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
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@ -413,21 +413,21 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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return SelectThumbAddrModeRI5(Op, N, 1, Base, Offset, OffImm);
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SDOperand &Base, SDOperand &OffImm,
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SDOperand &Offset) {
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return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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return SelectThumbAddrModeRI5(Op, N, 2, Base, Offset, OffImm);
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SDOperand &Base, SDOperand &OffImm,
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SDOperand &Offset) {
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return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
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SDOperand &Base, SDOperand &Offset,
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SDOperand &OffImm) {
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return SelectThumbAddrModeRI5(Op, N, 4, Base, Offset, OffImm);
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SDOperand &Base, SDOperand &OffImm,
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SDOperand &Offset) {
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return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
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}
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bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
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@ -124,7 +124,7 @@ def t_addrmode_rr : Operand<i32>,
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def t_addrmode_s4 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
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let PrintMethod = "printThumbAddrModeS4Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_s2 := reg + reg
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@ -133,7 +133,7 @@ def t_addrmode_s4 : Operand<i32>,
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def t_addrmode_s2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
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let PrintMethod = "printThumbAddrModeS2Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_s1 := reg + reg
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@ -142,7 +142,7 @@ def t_addrmode_s2 : Operand<i32>,
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def t_addrmode_s1 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
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let PrintMethod = "printThumbAddrModeS1Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_sp := sp + imm8 * 4
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