forked from OSchip/llvm-project
[RISCV] Add additional half precision fnmadd/fnmsub tests with an fneg on the second operand instead of the first.
This matches the float/double tests added in defe11866a
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@ -302,6 +302,30 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
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ret half %1
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}
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define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmadd_s_2:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_s_2:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
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; RV64IZFH-NEXT: ret
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%b_ = fadd half 0.0, %b
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%c_ = fadd half 0.0, %c
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%negb = fsub half -0.0, %b_
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%negc = fsub half -0.0, %c_
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%1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
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ret half %1
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}
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define half @fnmsub_s(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmsub_s:
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; RV32IZFH: # %bb.0:
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@ -322,6 +346,26 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
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ret half %1
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}
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define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmsub_s_2:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
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; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmsub_s_2:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
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; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
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; RV64IZFH-NEXT: ret
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%b_ = fadd half 0.0, %b
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%negb = fsub half -0.0, %b_
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%1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
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ret half %1
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}
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define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fmadd_s_contract:
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; RV32IZFH: # %bb.0:
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