forked from OSchip/llvm-project
[AArch64][GlobalISel] Legalize vector G_PTR_ADD and enable selection.
Differential Revision: https://reviews.llvm.org/D81419
This commit is contained in:
Amara Emerson
parent
46529978bf
commit
1cbebd95de
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@ -1640,20 +1640,19 @@ bool AArch64InstructionSelector::convertPtrAddToAdd(
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if (PtrTy.getAddressSpace() != 0)
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return false;
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// Only do this for scalars for now.
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if (PtrTy.isVector())
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return false;
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MachineIRBuilder MIB(I);
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const LLT s64 = LLT::scalar(64);
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auto PtrToInt = MIB.buildPtrToInt(s64, AddOp1Reg);
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const LLT CastPtrTy = PtrTy.isVector() ? LLT::vector(2, 64) : LLT::scalar(64);
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auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
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// Set regbanks on the registers.
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if (PtrTy.isVector())
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MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID));
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else
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MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
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// Now turn the %dst(p0) = G_PTR_ADD %base, off into:
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// %dst(s64) = G_ADD %intbase, off
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// %dst(intty) = G_ADD %intbase, off
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I.setDesc(TII.get(TargetOpcode::G_ADD));
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MRI.setType(DstReg, s64);
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MRI.setType(DstReg, CastPtrTy);
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I.getOperand(1).setReg(PtrToInt.getReg(0));
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if (!select(*PtrToInt)) {
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LLVM_DEBUG(dbgs() << "Failed to select G_PTRTOINT in convertPtrAddToAdd");
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@ -2506,6 +2505,13 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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I.eraseFromParent();
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return true;
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}
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// We might have a vector G_PTRTOINT, in which case just emit a COPY.
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if (Opcode == TargetOpcode::G_PTRTOINT) {
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assert(DstTy.isVector() && "Expected an FPR ptrtoint to be a vector");
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I.setDesc(TII.get(TargetOpcode::COPY));
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return true;
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}
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}
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return false;
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@ -108,7 +108,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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.minScalarSameAs(1, 0);
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getActionDefinitionsBuilder(G_PTR_ADD)
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.legalFor({{p0, s64}})
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.legalFor({{p0, s64}, {v2p0, v2s64}})
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.clampScalar(1, s64, s64);
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getActionDefinitionsBuilder(G_PTRMASK).legalFor({{p0, s64}});
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@ -1,18 +1,18 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: test_gep_small
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name: test_ptr_add_small
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_gep_small
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; CHECK-LABEL: name: test_ptr_add_small
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
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; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[C]](s64)
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; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]](s64)
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; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[ASHR]](s64)
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; CHECK: $x0 = COPY [[GEP]](p0)
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[ASHR]](s64)
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; CHECK: $x0 = COPY [[PTR_ADD]](p0)
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%0:_(p0) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s8) = G_TRUNC %1(s64)
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@ -20,3 +20,18 @@ body: |
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$x0 = COPY %3(p0)
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...
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---
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name: test_ptr_add_vec_p0
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_ptr_add_vec_p0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(<2 x p0>) = G_PTR_ADD [[COPY]], [[COPY1]](<2 x s64>)
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; CHECK: $q0 = COPY [[PTR_ADD]](<2 x p0>)
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%0:_(<2 x p0>) = COPY $q0
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%1:_(<2 x s64>) = COPY $q1
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%3:_(<2 x p0>) = G_PTR_ADD %0, %1(<2 x s64>)
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$q0 = COPY %3(<2 x p0>)
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...
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@ -0,0 +1,74 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
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---
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name: ptr_add
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: ptr_add
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
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; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 42, 0
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; CHECK: $x0 = COPY [[ADDXri]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 42
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%2:gpr(p0) = G_PTR_ADD %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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name: ptr_add_no_constant
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: ptr_add_no_constant
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
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; CHECK: $x0 = COPY [[ADDXrr]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%2:gpr(p0) = G_PTR_ADD %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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name: ptr_add_bad_imm
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: ptr_add_bad_imm
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10000
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[SUBREG_TO_REG]]
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; CHECK: $x0 = COPY [[ADDXrr]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 10000
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%2:gpr(p0) = G_PTR_ADD %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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name: ptr_add_vec
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: ptr_add_vec
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[ADDv2i64_:%[0-9]+]]:fpr128 = ADDv2i64 [[COPY]], [[COPY1]]
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; CHECK: $q0 = COPY [[ADDv2i64_]]
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%0:fpr(<2 x p0>) = COPY $q0
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%1:fpr(<2 x s64>) = COPY $q1
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%3:fpr(<2 x p0>) = G_PTR_ADD %0, %1(<2 x s64>)
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$q0 = COPY %3(<2 x p0>)
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...
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@ -10,10 +10,6 @@
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ret void
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}
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define i8* @ptr_add(i8* %in) { ret i8* undef }
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define i8* @ptr_add_no_constant(i8* %in) { ret i8* undef }
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define i8* @ptr_add_bad_imm(i8* %in) { ret i8* undef }
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define i8* @ptr_mask(i8* %in) { ret i8* undef }
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@var_local = global i8 0
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@ -53,70 +49,6 @@ body: |
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...
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---
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# CHECK-LABEL: name: ptr_add
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name: ptr_add
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %{{[0-9]+}}:gpr64sp = ADDXri %{{[0-9]+}}, 42, 0
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body: |
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bb.0:
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liveins: $x0
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 42
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%2(p0) = G_PTR_ADD %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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# CHECK-LABEL: name: ptr_add_no_constant
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name: ptr_add_no_constant
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %{{[0-9]+}}:gpr64 = ADDXrr %{{[0-9]+}}, %{{[0-9]+}}
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body: |
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bb.0:
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liveins: $x0, $x1
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%0(p0) = COPY $x0
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%1(s64) = COPY $x1
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%2(p0) = G_PTR_ADD %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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# CHECK-LABEL: name: ptr_add_bad_imm
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name: ptr_add_bad_imm
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %0:gpr64 = COPY $x0
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# CHECK: %4:gpr32 = MOVi32imm 10000
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# CHECK: %1:gpr64 = SUBREG_TO_REG 0, %4, %subreg.sub_32
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# CHECK: %{{[0-9]+}}:gpr64 = ADDXrr %0, %1
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body: |
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bb.0:
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liveins: $x0, $x1
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 10000
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%2(p0) = G_PTR_ADD %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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# CHECK-LABEL: name: ptr_mask
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