forked from OSchip/llvm-project
[Hexagon] Change instruction type field in TSFlags to 7 bits
llvm-svn: 348171
This commit is contained in:
Krzysztof Parzyszek
parent
1e4b3709bb
commit
1cbc5cd364
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonDepITypes.h -------------------------------------------------===//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -9,7 +9,6 @@
|
|||
// Automatically generated file, please consult code owner before editing.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
namespace llvm {
|
||||
namespace HexagonII {
|
||||
enum Type {
|
||||
|
|
@ -18,48 +17,47 @@ enum Type {
|
|||
TypeALU32_ADDI = 2,
|
||||
TypeALU64 = 3,
|
||||
TypeCJ = 4,
|
||||
TypeCOPROC_VX = 5,
|
||||
TypeCR = 6,
|
||||
TypeCVI_4SLOT_MPY = 7,
|
||||
TypeCVI_GATHER = 8,
|
||||
TypeCVI_GATHER_RST = 9,
|
||||
TypeCVI_HIST = 10,
|
||||
TypeCVI_SCATTER = 11,
|
||||
TypeCVI_SCATTER_DV = 12,
|
||||
TypeCVI_SCATTER_NEW_RST = 13,
|
||||
TypeCVI_SCATTER_NEW_ST = 14,
|
||||
TypeCVI_SCATTER_RST = 15,
|
||||
TypeCVI_VA = 16,
|
||||
TypeCVI_VA_DV = 17,
|
||||
TypeCVI_VINLANESAT = 18,
|
||||
TypeCVI_VM_LD = 19,
|
||||
TypeCVI_VM_NEW_ST = 20,
|
||||
TypeCVI_VM_ST = 21,
|
||||
TypeCVI_VM_STU = 22,
|
||||
TypeCVI_VM_TMP_LD = 23,
|
||||
TypeCVI_VM_VP_LDU = 24,
|
||||
TypeCVI_VP = 25,
|
||||
TypeCVI_VP_VS = 26,
|
||||
TypeCVI_VS = 27,
|
||||
TypeCVI_VS_VX = 28,
|
||||
TypeCVI_VX = 29,
|
||||
TypeCVI_VX_DV = 30,
|
||||
TypeCVI_VX_LATE = 31,
|
||||
TypeDUPLEX = 33,
|
||||
TypeENDLOOP = 34,
|
||||
TypeEXTENDER = 35,
|
||||
TypeJ = 36,
|
||||
TypeLD = 37,
|
||||
TypeM = 38,
|
||||
TypeMAPPING = 39,
|
||||
TypeNCJ = 40,
|
||||
TypePSEUDO = 41,
|
||||
TypeST = 42,
|
||||
TypeSUBINSN = 43,
|
||||
TypeS_2op = 44,
|
||||
TypeS_3op = 45,
|
||||
TypeV2LDST = 48,
|
||||
TypeV4LDST = 49
|
||||
TypeCR = 5,
|
||||
TypeCVI_4SLOT_MPY = 6,
|
||||
TypeCVI_GATHER = 7,
|
||||
TypeCVI_GATHER_RST = 8,
|
||||
TypeCVI_HIST = 9,
|
||||
TypeCVI_SCATTER = 10,
|
||||
TypeCVI_SCATTER_DV = 11,
|
||||
TypeCVI_SCATTER_NEW_RST = 12,
|
||||
TypeCVI_SCATTER_NEW_ST = 13,
|
||||
TypeCVI_SCATTER_RST = 14,
|
||||
TypeCVI_VA = 15,
|
||||
TypeCVI_VA_DV = 16,
|
||||
TypeCVI_VINLANESAT = 17,
|
||||
TypeCVI_VM_LD = 18,
|
||||
TypeCVI_VM_NEW_ST = 19,
|
||||
TypeCVI_VM_ST = 20,
|
||||
TypeCVI_VM_STU = 21,
|
||||
TypeCVI_VM_TMP_LD = 22,
|
||||
TypeCVI_VM_VP_LDU = 23,
|
||||
TypeCVI_VP = 24,
|
||||
TypeCVI_VP_VS = 25,
|
||||
TypeCVI_VS = 26,
|
||||
TypeCVI_VS_VX = 27,
|
||||
TypeCVI_VX = 28,
|
||||
TypeCVI_VX_DV = 29,
|
||||
TypeCVI_VX_LATE = 30,
|
||||
TypeDUPLEX = 32,
|
||||
TypeENDLOOP = 33,
|
||||
TypeEXTENDER = 34,
|
||||
TypeJ = 35,
|
||||
TypeLD = 36,
|
||||
TypeM = 37,
|
||||
TypeMAPPING = 38,
|
||||
TypeNCJ = 39,
|
||||
TypePSEUDO = 40,
|
||||
TypeST = 41,
|
||||
TypeSUBINSN = 42,
|
||||
TypeS_2op = 43,
|
||||
TypeS_3op = 44,
|
||||
TypeV2LDST = 47,
|
||||
TypeV4LDST = 48,
|
||||
};
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===- HexagonDepITypes.td ------------------------------------------------===//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -9,52 +9,50 @@
|
|||
// Automatically generated file, please consult code owner before editing.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
||||
class IType<bits<6> t> { bits<6> Value = t; }
|
||||
class IType<bits<7> t> { bits<7> Value = t; }
|
||||
def TypeALU32_2op : IType<0>;
|
||||
def TypeALU32_3op : IType<1>;
|
||||
def TypeALU32_ADDI : IType<2>;
|
||||
def TypeALU64 : IType<3>;
|
||||
def TypeCJ : IType<4>;
|
||||
def TypeCOPROC_VX : IType<5>;
|
||||
def TypeCR : IType<6>;
|
||||
def TypeCVI_4SLOT_MPY : IType<7>;
|
||||
def TypeCVI_GATHER : IType<8>;
|
||||
def TypeCVI_GATHER_RST : IType<9>;
|
||||
def TypeCVI_HIST : IType<10>;
|
||||
def TypeCVI_SCATTER : IType<11>;
|
||||
def TypeCVI_SCATTER_DV : IType<12>;
|
||||
def TypeCVI_SCATTER_NEW_RST : IType<13>;
|
||||
def TypeCVI_SCATTER_NEW_ST : IType<14>;
|
||||
def TypeCVI_SCATTER_RST : IType<15>;
|
||||
def TypeCVI_VA : IType<16>;
|
||||
def TypeCVI_VA_DV : IType<17>;
|
||||
def TypeCVI_VINLANESAT : IType<18>;
|
||||
def TypeCVI_VM_LD : IType<19>;
|
||||
def TypeCVI_VM_NEW_ST : IType<20>;
|
||||
def TypeCVI_VM_ST : IType<21>;
|
||||
def TypeCVI_VM_STU : IType<22>;
|
||||
def TypeCVI_VM_TMP_LD : IType<23>;
|
||||
def TypeCVI_VM_VP_LDU : IType<24>;
|
||||
def TypeCVI_VP : IType<25>;
|
||||
def TypeCVI_VP_VS : IType<26>;
|
||||
def TypeCVI_VS : IType<27>;
|
||||
def TypeCVI_VS_VX : IType<28>;
|
||||
def TypeCVI_VX : IType<29>;
|
||||
def TypeCVI_VX_DV : IType<30>;
|
||||
def TypeCVI_VX_LATE : IType<31>;
|
||||
def TypeDUPLEX : IType<33>;
|
||||
def TypeENDLOOP : IType<34>;
|
||||
def TypeEXTENDER : IType<35>;
|
||||
def TypeJ : IType<36>;
|
||||
def TypeLD : IType<37>;
|
||||
def TypeM : IType<38>;
|
||||
def TypeMAPPING : IType<39>;
|
||||
def TypeNCJ : IType<40>;
|
||||
def TypePSEUDO : IType<41>;
|
||||
def TypeST : IType<42>;
|
||||
def TypeSUBINSN : IType<43>;
|
||||
def TypeS_2op : IType<44>;
|
||||
def TypeS_3op : IType<45>;
|
||||
def TypeV2LDST : IType<48>;
|
||||
def TypeV4LDST : IType<49>;
|
||||
def TypeCR : IType<5>;
|
||||
def TypeCVI_4SLOT_MPY : IType<6>;
|
||||
def TypeCVI_GATHER : IType<7>;
|
||||
def TypeCVI_GATHER_RST : IType<8>;
|
||||
def TypeCVI_HIST : IType<9>;
|
||||
def TypeCVI_SCATTER : IType<10>;
|
||||
def TypeCVI_SCATTER_DV : IType<11>;
|
||||
def TypeCVI_SCATTER_NEW_RST : IType<12>;
|
||||
def TypeCVI_SCATTER_NEW_ST : IType<13>;
|
||||
def TypeCVI_SCATTER_RST : IType<14>;
|
||||
def TypeCVI_VA : IType<15>;
|
||||
def TypeCVI_VA_DV : IType<16>;
|
||||
def TypeCVI_VINLANESAT : IType<17>;
|
||||
def TypeCVI_VM_LD : IType<18>;
|
||||
def TypeCVI_VM_NEW_ST : IType<19>;
|
||||
def TypeCVI_VM_ST : IType<20>;
|
||||
def TypeCVI_VM_STU : IType<21>;
|
||||
def TypeCVI_VM_TMP_LD : IType<22>;
|
||||
def TypeCVI_VM_VP_LDU : IType<23>;
|
||||
def TypeCVI_VP : IType<24>;
|
||||
def TypeCVI_VP_VS : IType<25>;
|
||||
def TypeCVI_VS : IType<26>;
|
||||
def TypeCVI_VS_VX : IType<27>;
|
||||
def TypeCVI_VX : IType<28>;
|
||||
def TypeCVI_VX_DV : IType<29>;
|
||||
def TypeCVI_VX_LATE : IType<30>;
|
||||
def TypeDUPLEX : IType<32>;
|
||||
def TypeENDLOOP : IType<33>;
|
||||
def TypeEXTENDER : IType<34>;
|
||||
def TypeJ : IType<35>;
|
||||
def TypeLD : IType<36>;
|
||||
def TypeM : IType<37>;
|
||||
def TypeMAPPING : IType<38>;
|
||||
def TypeNCJ : IType<39>;
|
||||
def TypePSEUDO : IType<40>;
|
||||
def TypeST : IType<41>;
|
||||
def TypeSUBINSN : IType<42>;
|
||||
def TypeS_2op : IType<43>;
|
||||
def TypeS_3op : IType<44>;
|
||||
def TypeV2LDST : IType<47>;
|
||||
def TypeV4LDST : IType<48>;
|
||||
|
|
|
|||
|
|
@ -69,101 +69,101 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
|
|||
|
||||
// Instruction type according to the ISA.
|
||||
IType Type = type;
|
||||
let TSFlags{5-0} = Type.Value;
|
||||
let TSFlags{6-0} = Type.Value;
|
||||
|
||||
// Solo instructions, i.e., those that cannot be in a packet with others.
|
||||
bits<1> isSolo = 0;
|
||||
let TSFlags{6} = isSolo;
|
||||
let TSFlags{7} = isSolo;
|
||||
// Packed only with A or X-type instructions.
|
||||
bits<1> isSoloAX = 0;
|
||||
let TSFlags{7} = isSoloAX;
|
||||
let TSFlags{8} = isSoloAX;
|
||||
// Restricts slot 1 to ALU-only instructions.
|
||||
bits<1> isRestrictSlot1AOK = 0;
|
||||
let TSFlags{8} = isRestrictSlot1AOK;
|
||||
let TSFlags{9} = isRestrictSlot1AOK;
|
||||
|
||||
// Predicated instructions.
|
||||
bits<1> isPredicated = 0;
|
||||
let TSFlags{9} = isPredicated;
|
||||
let TSFlags{10} = isPredicated;
|
||||
bits<1> isPredicatedFalse = 0;
|
||||
let TSFlags{10} = isPredicatedFalse;
|
||||
let TSFlags{11} = isPredicatedFalse;
|
||||
bits<1> isPredicatedNew = 0;
|
||||
let TSFlags{11} = isPredicatedNew;
|
||||
let TSFlags{12} = isPredicatedNew;
|
||||
bits<1> isPredicateLate = 0;
|
||||
let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
|
||||
let TSFlags{13} = isPredicateLate; // Late predicate producer insn.
|
||||
|
||||
// New-value insn helper fields.
|
||||
bits<1> isNewValue = 0;
|
||||
let TSFlags{13} = isNewValue; // New-value consumer insn.
|
||||
let TSFlags{14} = isNewValue; // New-value consumer insn.
|
||||
bits<1> hasNewValue = 0;
|
||||
let TSFlags{14} = hasNewValue; // New-value producer insn.
|
||||
let TSFlags{15} = hasNewValue; // New-value producer insn.
|
||||
bits<3> opNewValue = 0;
|
||||
let TSFlags{17-15} = opNewValue; // New-value produced operand.
|
||||
let TSFlags{18-16} = opNewValue; // New-value produced operand.
|
||||
bits<1> isNVStorable = 0;
|
||||
let TSFlags{18} = isNVStorable; // Store that can become new-value store.
|
||||
let TSFlags{19} = isNVStorable; // Store that can become new-value store.
|
||||
bits<1> isNVStore = 0;
|
||||
let TSFlags{19} = isNVStore; // New-value store insn.
|
||||
let TSFlags{20} = isNVStore; // New-value store insn.
|
||||
bits<1> isCVLoadable = 0;
|
||||
let TSFlags{20} = isCVLoadable; // Load that can become cur-value load.
|
||||
let TSFlags{21} = isCVLoadable; // Load that can become cur-value load.
|
||||
bits<1> isCVLoad = 0;
|
||||
let TSFlags{21} = isCVLoad; // Cur-value load insn.
|
||||
let TSFlags{22} = isCVLoad; // Cur-value load insn.
|
||||
|
||||
// Immediate extender helper fields.
|
||||
bits<1> isExtendable = 0;
|
||||
let TSFlags{22} = isExtendable; // Insn may be extended.
|
||||
let TSFlags{23} = isExtendable; // Insn may be extended.
|
||||
bits<1> isExtended = 0;
|
||||
let TSFlags{23} = isExtended; // Insn must be extended.
|
||||
let TSFlags{24} = isExtended; // Insn must be extended.
|
||||
bits<3> opExtendable = 0;
|
||||
let TSFlags{26-24} = opExtendable; // Which operand may be extended.
|
||||
let TSFlags{27-25} = opExtendable; // Which operand may be extended.
|
||||
bits<1> isExtentSigned = 0;
|
||||
let TSFlags{27} = isExtentSigned; // Signed or unsigned range.
|
||||
let TSFlags{28} = isExtentSigned; // Signed or unsigned range.
|
||||
bits<5> opExtentBits = 0;
|
||||
let TSFlags{32-28} = opExtentBits; //Number of bits of range before extending.
|
||||
let TSFlags{33-29} = opExtentBits; //Number of bits of range before extending.
|
||||
bits<2> opExtentAlign = 0;
|
||||
let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
|
||||
let TSFlags{35-34} = opExtentAlign; // Alignment exponent before extending.
|
||||
|
||||
bit cofMax1 = 0;
|
||||
let TSFlags{35} = cofMax1;
|
||||
let TSFlags{36} = cofMax1;
|
||||
bit cofRelax1 = 0;
|
||||
let TSFlags{36} = cofRelax1;
|
||||
let TSFlags{37} = cofRelax1;
|
||||
bit cofRelax2 = 0;
|
||||
let TSFlags{37} = cofRelax2;
|
||||
let TSFlags{38} = cofRelax2;
|
||||
|
||||
bit isRestrictNoSlot1Store = 0;
|
||||
let TSFlags{38} = isRestrictNoSlot1Store;
|
||||
let TSFlags{39} = isRestrictNoSlot1Store;
|
||||
|
||||
// Addressing mode for load/store instructions.
|
||||
AddrModeType addrMode = NoAddrMode;
|
||||
let TSFlags{43-41} = addrMode.Value;
|
||||
let TSFlags{44-42} = addrMode.Value;
|
||||
|
||||
// Memory access size for mem access instructions (load/store)
|
||||
MemAccessSize accessSize = NoMemAccess;
|
||||
let TSFlags{47-44} = accessSize.Value;
|
||||
let TSFlags{48-45} = accessSize.Value;
|
||||
|
||||
bits<1> isTaken = 0;
|
||||
let TSFlags {48} = isTaken; // Branch prediction.
|
||||
let TSFlags {49} = isTaken; // Branch prediction.
|
||||
|
||||
bits<1> isFP = 0;
|
||||
let TSFlags {49} = isFP; // Floating-point.
|
||||
let TSFlags {50} = isFP; // Floating-point.
|
||||
|
||||
bits<1> isSomeOK = 0;
|
||||
let TSFlags {50} = isSomeOK; // Relax some grouping constraints.
|
||||
let TSFlags {51} = isSomeOK; // Relax some grouping constraints.
|
||||
|
||||
bits<1> hasNewValue2 = 0;
|
||||
let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
|
||||
let TSFlags{52} = hasNewValue2; // Second New-value producer insn.
|
||||
bits<3> opNewValue2 = 0;
|
||||
let TSFlags{54-52} = opNewValue2; // Second New-value produced operand.
|
||||
let TSFlags{55-53} = opNewValue2; // Second New-value produced operand.
|
||||
|
||||
bits<1> isAccumulator = 0;
|
||||
let TSFlags{55} = isAccumulator;
|
||||
let TSFlags{56} = isAccumulator;
|
||||
|
||||
bits<1> prefersSlot3 = 0;
|
||||
let TSFlags{56} = prefersSlot3; // Complex XU
|
||||
let TSFlags{57} = prefersSlot3; // Complex XU
|
||||
|
||||
bits<1> hasTmpDst = 0;
|
||||
let TSFlags{59} = hasTmpDst; // v65 : 'fake" register VTMP is set
|
||||
let TSFlags{60} = hasTmpDst; // v65 : 'fake" register VTMP is set
|
||||
|
||||
bit CVINew = 0;
|
||||
let TSFlags{61} = CVINew;
|
||||
let TSFlags{62} = CVINew;
|
||||
|
||||
// Fields used for relation models.
|
||||
bit isNonTemporal = 0;
|
||||
|
|
|
|||
|
|
@ -49,39 +49,39 @@ class InstDuplex<bits<4> iClass, list<dag> pattern = [],
|
|||
|
||||
// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
|
||||
|
||||
let TSFlags{5-0} = Type.Value;
|
||||
let TSFlags{6-0} = Type.Value;
|
||||
|
||||
// Predicated instructions.
|
||||
bits<1> isPredicated = 0;
|
||||
let TSFlags{6} = isPredicated;
|
||||
let TSFlags{7} = isPredicated;
|
||||
bits<1> isPredicatedFalse = 0;
|
||||
let TSFlags{7} = isPredicatedFalse;
|
||||
let TSFlags{8} = isPredicatedFalse;
|
||||
bits<1> isPredicatedNew = 0;
|
||||
let TSFlags{8} = isPredicatedNew;
|
||||
let TSFlags{9} = isPredicatedNew;
|
||||
|
||||
// New-value insn helper fields.
|
||||
bits<1> isNewValue = 0;
|
||||
let TSFlags{9} = isNewValue; // New-value consumer insn.
|
||||
let TSFlags{10} = isNewValue; // New-value consumer insn.
|
||||
bits<1> hasNewValue = 0;
|
||||
let TSFlags{10} = hasNewValue; // New-value producer insn.
|
||||
let TSFlags{11} = hasNewValue; // New-value producer insn.
|
||||
bits<3> opNewValue = 0;
|
||||
let TSFlags{13-11} = opNewValue; // New-value produced operand.
|
||||
let TSFlags{14-12} = opNewValue; // New-value produced operand.
|
||||
bits<1> isNVStorable = 0;
|
||||
let TSFlags{14} = isNVStorable; // Store that can become new-value store.
|
||||
let TSFlags{15} = isNVStorable; // Store that can become new-value store.
|
||||
bits<1> isNVStore = 0;
|
||||
let TSFlags{15} = isNVStore; // New-value store insn.
|
||||
let TSFlags{16} = isNVStore; // New-value store insn.
|
||||
|
||||
// Immediate extender helper fields.
|
||||
bits<1> isExtendable = 0;
|
||||
let TSFlags{16} = isExtendable; // Insn may be extended.
|
||||
let TSFlags{17} = isExtendable; // Insn may be extended.
|
||||
bits<1> isExtended = 0;
|
||||
let TSFlags{17} = isExtended; // Insn must be extended.
|
||||
let TSFlags{18} = isExtended; // Insn must be extended.
|
||||
bits<3> opExtendable = 0;
|
||||
let TSFlags{20-18} = opExtendable; // Which operand may be extended.
|
||||
let TSFlags{21-19} = opExtendable; // Which operand may be extended.
|
||||
bits<1> isExtentSigned = 0;
|
||||
let TSFlags{21} = isExtentSigned; // Signed or unsigned range.
|
||||
let TSFlags{22} = isExtentSigned; // Signed or unsigned range.
|
||||
bits<5> opExtentBits = 0;
|
||||
let TSFlags{26-22} = opExtentBits; //Number of bits of range before extending.
|
||||
let TSFlags{27-23} = opExtentBits; //Number of bits of range before extending.
|
||||
bits<2> opExtentAlign = 0;
|
||||
let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
|
||||
let TSFlags{29-28} = opExtentAlign; // Alignment exponent before extending.
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,8 +29,6 @@ namespace HexagonII {
|
|||
unsigned const TypeCVI_LAST = TypeCVI_VX_LATE;
|
||||
|
||||
enum SubTarget {
|
||||
HasV4SubT = 0x3f,
|
||||
HasV5SubT = 0x3e,
|
||||
HasV55SubT = 0x3c,
|
||||
HasV60SubT = 0x38,
|
||||
};
|
||||
|
|
@ -57,117 +55,117 @@ namespace HexagonII {
|
|||
// MCInstrDesc TSFlags
|
||||
// *** Must match HexagonInstrFormat*.td ***
|
||||
enum {
|
||||
// This 5-bit field describes the insn type.
|
||||
TypePos = 0,
|
||||
TypeMask = 0x3f,
|
||||
// This 7-bit field describes the insn type.
|
||||
TypePos = 0,
|
||||
TypeMask = 0x7f,
|
||||
|
||||
// Solo instructions.
|
||||
SoloPos = 6,
|
||||
SoloPos = 7,
|
||||
SoloMask = 0x1,
|
||||
// Packed only with A or X-type instructions.
|
||||
SoloAXPos = 7,
|
||||
SoloAXPos = 8,
|
||||
SoloAXMask = 0x1,
|
||||
// Only A-type instruction in first slot or nothing.
|
||||
RestrictSlot1AOKPos = 8,
|
||||
RestrictSlot1AOKPos = 9,
|
||||
RestrictSlot1AOKMask = 0x1,
|
||||
|
||||
// Predicated instructions.
|
||||
PredicatedPos = 9,
|
||||
PredicatedPos = 10,
|
||||
PredicatedMask = 0x1,
|
||||
PredicatedFalsePos = 10,
|
||||
PredicatedFalsePos = 11,
|
||||
PredicatedFalseMask = 0x1,
|
||||
PredicatedNewPos = 11,
|
||||
PredicatedNewPos = 12,
|
||||
PredicatedNewMask = 0x1,
|
||||
PredicateLatePos = 12,
|
||||
PredicateLatePos = 13,
|
||||
PredicateLateMask = 0x1,
|
||||
|
||||
// New-Value consumer instructions.
|
||||
NewValuePos = 13,
|
||||
NewValuePos = 14,
|
||||
NewValueMask = 0x1,
|
||||
// New-Value producer instructions.
|
||||
hasNewValuePos = 14,
|
||||
hasNewValuePos = 15,
|
||||
hasNewValueMask = 0x1,
|
||||
// Which operand consumes or produces a new value.
|
||||
NewValueOpPos = 15,
|
||||
NewValueOpPos = 16,
|
||||
NewValueOpMask = 0x7,
|
||||
// Stores that can become new-value stores.
|
||||
mayNVStorePos = 18,
|
||||
mayNVStorePos = 19,
|
||||
mayNVStoreMask = 0x1,
|
||||
// New-value store instructions.
|
||||
NVStorePos = 19,
|
||||
NVStorePos = 20,
|
||||
NVStoreMask = 0x1,
|
||||
// Loads that can become current-value loads.
|
||||
mayCVLoadPos = 20,
|
||||
mayCVLoadPos = 21,
|
||||
mayCVLoadMask = 0x1,
|
||||
// Current-value load instructions.
|
||||
CVLoadPos = 21,
|
||||
CVLoadPos = 22,
|
||||
CVLoadMask = 0x1,
|
||||
|
||||
// Extendable insns.
|
||||
ExtendablePos = 22,
|
||||
ExtendablePos = 23,
|
||||
ExtendableMask = 0x1,
|
||||
// Insns must be extended.
|
||||
ExtendedPos = 23,
|
||||
ExtendedPos = 24,
|
||||
ExtendedMask = 0x1,
|
||||
// Which operand may be extended.
|
||||
ExtendableOpPos = 24,
|
||||
ExtendableOpPos = 25,
|
||||
ExtendableOpMask = 0x7,
|
||||
// Signed or unsigned range.
|
||||
ExtentSignedPos = 27,
|
||||
ExtentSignedPos = 28,
|
||||
ExtentSignedMask = 0x1,
|
||||
// Number of bits of range before extending operand.
|
||||
ExtentBitsPos = 28,
|
||||
ExtentBitsPos = 29,
|
||||
ExtentBitsMask = 0x1f,
|
||||
// Alignment power-of-two before extending operand.
|
||||
ExtentAlignPos = 33,
|
||||
ExtentAlignPos = 34,
|
||||
ExtentAlignMask = 0x3,
|
||||
|
||||
CofMax1Pos = 35,
|
||||
CofMax1Pos = 36,
|
||||
CofMax1Mask = 0x1,
|
||||
CofRelax1Pos = 36,
|
||||
CofRelax1Pos = 37,
|
||||
CofRelax1Mask = 0x1,
|
||||
CofRelax2Pos = 37,
|
||||
CofRelax2Pos = 38,
|
||||
CofRelax2Mask = 0x1,
|
||||
|
||||
RestrictNoSlot1StorePos = 38,
|
||||
RestrictNoSlot1StorePos = 39,
|
||||
RestrictNoSlot1StoreMask = 0x1,
|
||||
|
||||
// Addressing mode for load/store instructions.
|
||||
AddrModePos = 41,
|
||||
AddrModePos = 42,
|
||||
AddrModeMask = 0x7,
|
||||
// Access size for load/store instructions.
|
||||
MemAccessSizePos = 44,
|
||||
MemAccessSizePos = 45,
|
||||
MemAccesSizeMask = 0xf,
|
||||
|
||||
// Branch predicted taken.
|
||||
TakenPos = 48,
|
||||
TakenPos = 49,
|
||||
TakenMask = 0x1,
|
||||
|
||||
// Floating-point instructions.
|
||||
FPPos = 49,
|
||||
FPPos = 50,
|
||||
FPMask = 0x1,
|
||||
|
||||
// New-Value producer-2 instructions.
|
||||
hasNewValuePos2 = 51,
|
||||
hasNewValuePos2 = 52,
|
||||
hasNewValueMask2 = 0x1,
|
||||
// Which operand consumes or produces a new value.
|
||||
NewValueOpPos2 = 52,
|
||||
NewValueOpPos2 = 53,
|
||||
NewValueOpMask2 = 0x7,
|
||||
|
||||
// Accumulator instructions.
|
||||
AccumulatorPos = 55,
|
||||
AccumulatorPos = 56,
|
||||
AccumulatorMask = 0x1,
|
||||
|
||||
// Complex XU, prevent xu competition by preferring slot3
|
||||
PrefersSlot3Pos = 56,
|
||||
PrefersSlot3Pos = 57,
|
||||
PrefersSlot3Mask = 0x1,
|
||||
|
||||
// v65
|
||||
HasTmpDstPos = 59,
|
||||
HasTmpDstPos = 60,
|
||||
HasTmpDstMask = 0x1,
|
||||
|
||||
CVINewPos = 61,
|
||||
CVINewMask = 0x1
|
||||
CVINewPos = 62,
|
||||
CVINewMask = 0x1,
|
||||
};
|
||||
|
||||
// *** The code above must match HexagonInstrFormat*.td *** //
|
||||
|
|
@ -176,7 +174,7 @@ namespace HexagonII {
|
|||
enum HexagonMOTargetFlagVal {
|
||||
// Hexagon-specific MachineOperand target flags.
|
||||
//
|
||||
// When chaning these, make sure to update
|
||||
// When changing these, make sure to update
|
||||
// getSerializableDirectMachineOperandTargetFlags and
|
||||
// getSerializableBitmaskMachineOperandTargetFlags if needed.
|
||||
MO_NO_FLAG,
|
||||
|
|
@ -189,7 +187,8 @@ namespace HexagonII {
|
|||
MO_GOT,
|
||||
|
||||
// Low or high part of a symbol.
|
||||
MO_LO16, MO_HI16,
|
||||
MO_LO16,
|
||||
MO_HI16,
|
||||
|
||||
// Offset from the base of the SDA.
|
||||
MO_GPREL,
|
||||
|
|
|
|||
Loading…
Reference in New Issue