forked from OSchip/llvm-project
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
Added support for constraints 'I', 'J', 'B', 'C', 'DA', 'DB'. See https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints. Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D81651
This commit is contained in:
Dmitry Preobrazhensky
parent
3c72cafdf4
commit
1c9d681092
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@ -4146,7 +4146,13 @@ AMDGPU:
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- ``[0-9]v``: The 32-bit VGPR register, number 0-9.
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- ``[0-9]s``: The 32-bit SGPR register, number 0-9.
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- ``[0-9]a``: The 32-bit AGPR register, number 0-9.
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- ``I``: An integer inline constant in the range from -16 to 64.
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- ``J``: A 16-bit signed integer constant.
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- ``A``: An integer or a floating-point inline constant.
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- ``B``: A 32-bit signed integer constant.
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- ``C``: A 32-bit unsigned integer constant or an integer inline constant in the range from -16 to 64.
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- ``DA``: A 64-bit constant that can be split into two "A" constants.
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- ``DB``: A 64-bit constant that can be split into two "B" constants.
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All ARM modes:
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@ -1365,9 +1365,9 @@ bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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if (AMDGPU::isInlinableIntLiteral(Val)) {
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O << Val;
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} else if (isUInt<16>(Val)) {
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O << format("0x%" PRIx64, static_cast<uint16_t>(Val));
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O << format("0x%" PRIx16, static_cast<uint16_t>(Val));
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} else if (isUInt<32>(Val)) {
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O << format("0x%" PRIx64, static_cast<uint32_t>(Val));
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O << format("0x%" PRIx32, static_cast<uint32_t>(Val));
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} else {
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O << format("0x%" PRIx64, static_cast<uint64_t>(Val));
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}
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@ -11163,6 +11163,24 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
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}
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static bool isImmConstraint(StringRef Constraint) {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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default: break;
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case 'I':
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case 'J':
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case 'A':
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case 'B':
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case 'C':
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return true;
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}
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} else if (Constraint == "DA" ||
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Constraint == "DB") {
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return true;
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}
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return false;
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}
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SITargetLowering::ConstraintType
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SITargetLowering::getConstraintType(StringRef Constraint) const {
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if (Constraint.size() == 1) {
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@ -11172,67 +11190,115 @@ SITargetLowering::getConstraintType(StringRef Constraint) const {
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case 'v':
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case 'a':
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return C_RegisterClass;
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case 'A':
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return C_Other;
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}
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}
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if (isImmConstraint(Constraint)) {
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return C_Other;
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}
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return TargetLowering::getConstraintType(Constraint);
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}
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static uint64_t clearUnusedBits(uint64_t Val, unsigned Size) {
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if (!AMDGPU::isInlinableIntLiteral(Val)) {
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Val = Val & maskTrailingOnes<uint64_t>(Size);
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}
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return Val;
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}
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void SITargetLowering::LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const {
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if (Constraint.length() == 1 && Constraint[0] == 'A') {
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LowerAsmOperandForConstraintA(Op, Ops, DAG);
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if (isImmConstraint(Constraint)) {
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uint64_t Val;
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if (getAsmOperandConstVal(Op, Val) &&
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checkAsmConstraintVal(Op, Constraint, Val)) {
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Val = clearUnusedBits(Val, Op.getScalarValueSizeInBits());
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Ops.push_back(DAG.getTargetConstant(Val, SDLoc(Op), MVT::i64));
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}
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} else {
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TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
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}
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}
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void SITargetLowering::LowerAsmOperandForConstraintA(SDValue Op,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const {
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bool SITargetLowering::getAsmOperandConstVal(SDValue Op, uint64_t &Val) const {
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unsigned Size = Op.getScalarValueSizeInBits();
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if (Size > 64)
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return;
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return false;
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if (Size == 16 && !Subtarget->has16BitInsts())
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return false;
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uint64_t Val;
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bool IsConst = false;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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Val = C->getSExtValue();
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IsConst = true;
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} else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
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return true;
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}
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if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
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Val = C->getValueAPF().bitcastToAPInt().getSExtValue();
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IsConst = true;
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} else if (BuildVectorSDNode *V = dyn_cast<BuildVectorSDNode>(Op)) {
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return true;
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}
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if (BuildVectorSDNode *V = dyn_cast<BuildVectorSDNode>(Op)) {
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if (Size != 16 || Op.getNumOperands() != 2)
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return;
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return false;
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if (Op.getOperand(0).isUndef() || Op.getOperand(1).isUndef())
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return;
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return false;
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if (ConstantSDNode *C = V->getConstantSplatNode()) {
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Val = C->getSExtValue();
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IsConst = true;
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} else if (ConstantFPSDNode *C = V->getConstantFPSplatNode()) {
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return true;
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}
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if (ConstantFPSDNode *C = V->getConstantFPSplatNode()) {
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Val = C->getValueAPF().bitcastToAPInt().getSExtValue();
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IsConst = true;
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return true;
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}
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}
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if (IsConst) {
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bool HasInv2Pi = Subtarget->hasInv2PiInlineImm();
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if ((Size == 16 && AMDGPU::isInlinableLiteral16(Val, HasInv2Pi)) ||
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(Size == 32 && AMDGPU::isInlinableLiteral32(Val, HasInv2Pi)) ||
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(Size == 64 && AMDGPU::isInlinableLiteral64(Val, HasInv2Pi))) {
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// Clear unused bits of fp constants
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if (!AMDGPU::isInlinableIntLiteral(Val)) {
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unsigned UnusedBits = 64 - Size;
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Val = (Val << UnusedBits) >> UnusedBits;
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}
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auto Res = DAG.getTargetConstant(Val, SDLoc(Op), MVT::i64);
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Ops.push_back(Res);
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return false;
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}
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bool SITargetLowering::checkAsmConstraintVal(SDValue Op,
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const std::string &Constraint,
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uint64_t Val) const {
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'I':
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return AMDGPU::isInlinableIntLiteral(Val);
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case 'J':
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return isInt<16>(Val);
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case 'A':
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return checkAsmConstraintValA(Op, Val);
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case 'B':
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return isInt<32>(Val);
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case 'C':
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return isUInt<32>(clearUnusedBits(Val, Op.getScalarValueSizeInBits())) ||
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AMDGPU::isInlinableIntLiteral(Val);
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default:
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break;
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}
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} else if (Constraint.size() == 2) {
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if (Constraint == "DA") {
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int64_t HiBits = static_cast<int32_t>(Val >> 32);
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int64_t LoBits = static_cast<int32_t>(Val);
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return checkAsmConstraintValA(Op, HiBits, 32) &&
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checkAsmConstraintValA(Op, LoBits, 32);
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}
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if (Constraint == "DB") {
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return true;
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}
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}
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llvm_unreachable("Invalid asm constraint");
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}
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bool SITargetLowering::checkAsmConstraintValA(SDValue Op,
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uint64_t Val,
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unsigned MaxSize) const {
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unsigned Size = std::min<unsigned>(Op.getScalarValueSizeInBits(), MaxSize);
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bool HasInv2Pi = Subtarget->hasInv2PiInlineImm();
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if ((Size == 16 && AMDGPU::isInlinableLiteral16(Val, HasInv2Pi)) ||
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(Size == 32 && AMDGPU::isInlinableLiteral32(Val, HasInv2Pi)) ||
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(Size == 64 && AMDGPU::isInlinableLiteral64(Val, HasInv2Pi))) {
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return true;
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}
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return false;
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}
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// Figure out which registers should be reserved for stack access. Only after
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@ -397,9 +397,13 @@ public:
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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void LowerAsmOperandForConstraintA(SDValue Op,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const;
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bool checkAsmConstraintVal(SDValue Op,
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const std::string &Constraint,
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uint64_t Val) const;
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bool checkAsmConstraintValA(SDValue Op,
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uint64_t Val,
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unsigned MaxSize = 64) const;
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SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
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SDValue V) const;
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@ -347,3 +347,971 @@ define i32 @inline_A_constraint_E2() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i128 100000000000000000000)
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ret i32 %v0
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}
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;==============================================================================
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; 'I' constraint, 16-bit operand
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;==============================================================================
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; NOSI: error: invalid operand for inline asm constraint 'I'
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; VI-LABEL: {{^}}inline_I_constraint_H0:
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; VI: v_mov_b32 {{v[0-9]+}}, 64
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define i32 @inline_I_constraint_H0() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 64)
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ret i32 %v0
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}
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; NOSI: error: invalid operand for inline asm constraint 'I'
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; VI-LABEL: {{^}}inline_I_constraint_H1:
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; VI: v_mov_b32 {{v[0-9]+}}, -16
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define i32 @inline_I_constraint_H1() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(half bitcast (i16 -16 to half))
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_H6() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(half 1.0)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_H7() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 bitcast (half -1.0 to i16))
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_H8() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 -17)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_H9() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i16 65)
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ret i32 %v0
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}
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;==============================================================================
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; 'I' constraint, 32-bit operand
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;==============================================================================
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; GCN-LABEL: {{^}}inline_I_constraint_F0:
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; GCN: v_mov_b32 {{v[0-9]+}}, -16
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define i32 @inline_I_constraint_F0() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i32 -16)
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ret i32 %v0
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}
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; GCN-LABEL: {{^}}inline_I_constraint_F1:
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; GCN: v_mov_b32 {{v[0-9]+}}, -1
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define i32 @inline_I_constraint_F1() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(float bitcast (i32 -1 to float))
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_F8() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(float -4.0)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_F9() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i32 -17)
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ret i32 %v0
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}
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;==============================================================================
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; 'I' constraint, 64-bit operand
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;==============================================================================
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; GCN-LABEL: {{^}}inline_I_constraint_D0:
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; GCN: v_mov_b32 {{v[0-9]+}}, -16
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define i32 @inline_I_constraint_D0() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i64 -16)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_D8() {
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%v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,I"(double 0.5)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_D9() {
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%v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,I"(i64 65)
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ret i32 %v0
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}
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;==============================================================================
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; 'I' constraint, v2x16 operand
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;==============================================================================
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; NOSI: error: invalid operand for inline asm constraint 'I'
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; VI-LABEL: {{^}}inline_I_constraint_V0:
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; VI: v_mov_b32 {{v[0-9]+}}, -4
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define i32 @inline_I_constraint_V0() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> <i16 -4, i16 -4>)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_V1() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x half> <half -0.5, half -0.5>)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_V2() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> <i16 -4, i16 undef>)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_V3() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i16> <i16 1, i16 2>)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_V4() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<4 x i16> <i16 0, i16 0, i16 0, i16 0>)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_V5() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(<2 x i32> <i32 0, i32 0>)
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ret i32 %v0
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}
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;==============================================================================
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; 'I' constraint, type errors
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;==============================================================================
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_E1(i32 %x) {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i32 %x)
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ret i32 %v0
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}
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; NOGCN: error: invalid operand for inline asm constraint 'I'
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define i32 @inline_I_constraint_E2() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,I"(i128 100000000000000000000)
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ret i32 %v0
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}
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;==============================================================================
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; 'J' constraint, 16-bit operand
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;==============================================================================
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; NOSI: error: invalid operand for inline asm constraint 'J'
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; VI-LABEL: {{^}}inline_J_constraint_H0:
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; VI: v_mov_b32 {{v[0-9]+}}, -1
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define i32 @inline_J_constraint_H0() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i16 65535)
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ret i32 %v0
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}
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; NOSI: error: invalid operand for inline asm constraint 'J'
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; VI-LABEL: {{^}}inline_J_constraint_H1:
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; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
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define i32 @inline_J_constraint_H1() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i16 32767)
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ret i32 %v0
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}
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; NOSI: error: invalid operand for inline asm constraint 'J'
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; VI-LABEL: {{^}}inline_J_constraint_H2:
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; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
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define i32 @inline_J_constraint_H2() {
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%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i16 -32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'J'
|
||||
; VI-LABEL: {{^}}inline_J_constraint_H3:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x4800
|
||||
define i32 @inline_J_constraint_H3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(half 8.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'J'
|
||||
; VI-LABEL: {{^}}inline_J_constraint_H4:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -16
|
||||
define i32 @inline_J_constraint_H4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(half bitcast (i16 -16 to half))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'J' constraint, 32-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_J_constraint_F0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_J_constraint_F0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 -1)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_J_constraint_F1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_J_constraint_F1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 32767)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_J_constraint_F2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xffff8000
|
||||
define i32 @inline_J_constraint_F2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 -32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_F6() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_F7() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 -32769)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_F8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(float -4.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'J' constraint, 64-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_J_constraint_D0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_J_constraint_D0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 32767)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_J_constraint_D1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffffffff8000
|
||||
define i32 @inline_J_constraint_D1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 -32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_D8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_D9() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i64 -32769)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'J' constraint, v2x16 operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'J'
|
||||
; VI-LABEL: {{^}}inline_J_constraint_V0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -4
|
||||
define i32 @inline_J_constraint_V0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x i16> <i16 -4, i16 -4>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'J'
|
||||
; VI-LABEL: {{^}}inline_J_constraint_V1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_J_constraint_V1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x i16> <i16 32767, i16 32767>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'J'
|
||||
; VI-LABEL: {{^}}inline_J_constraint_V2:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
|
||||
define i32 @inline_J_constraint_V2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x i16> <i16 -32768, i16 -32768>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'J'
|
||||
; VI-LABEL: {{^}}inline_J_constraint_V3:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x4c00
|
||||
define i32 @inline_J_constraint_V3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(<2 x half> <half 16.0, half 16.0>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'J' constraint, type errors
|
||||
;==============================================================================
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_E1(i32 %x) {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i32 %x)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'J'
|
||||
define i32 @inline_J_constraint_E2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i128 100000000000000000000)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'B' constraint, 16-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_H0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_B_constraint_H0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 32767)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_H1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_B_constraint_H1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 65535)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_H3:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
|
||||
define i32 @inline_B_constraint_H3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 -32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_H4:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x4a80
|
||||
define i32 @inline_B_constraint_H4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(half 13.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'B' constraint, 32-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_B_constraint_F0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_B_constraint_F0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i32 4294967295)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_B_constraint_F1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
|
||||
define i32 @inline_B_constraint_F1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i32 2147483648)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_B_constraint_F2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x42000000
|
||||
define i32 @inline_B_constraint_F2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(float 32.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'B' constraint, 64-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_B_constraint_D0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fffffff
|
||||
define i32 @inline_B_constraint_D0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 2147483647)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_B_constraint_D1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_B_constraint_D1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 -1)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_B_constraint_D2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffff80000000
|
||||
define i32 @inline_B_constraint_D2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 -2147483648)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'B'
|
||||
define i32 @inline_B_constraint_D7() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 -2147483649)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'B'
|
||||
define i32 @inline_B_constraint_D8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 4294967295)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'B'
|
||||
define i32 @inline_B_constraint_D9() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i64 2147483648)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'B' constraint, v2x16 operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_V0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_B_constraint_V0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(<2 x i16> <i16 32767, i16 32767>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_V1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_B_constraint_V1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(<2 x i16> <i16 -1, i16 -1>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'B'
|
||||
; VI-LABEL: {{^}}inline_B_constraint_V2:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
|
||||
define i32 @inline_B_constraint_V2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(<2 x i16> <i16 -32768, i16 -32768>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'C' constraint, 16-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_H0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_C_constraint_H0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i16 32767)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_H1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_C_constraint_H1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i16 65535)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_H3:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
|
||||
define i32 @inline_C_constraint_H3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i16 -32768)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_H4:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x4a80
|
||||
define i32 @inline_C_constraint_H4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(half 13.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'C' constraint, 32-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_F0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_C_constraint_F0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 4294967295)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_F1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
|
||||
define i32 @inline_C_constraint_F1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 2147483648)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_F2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fffffff
|
||||
define i32 @inline_C_constraint_F2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 2147483647)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_F3:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x42000000
|
||||
define i32 @inline_C_constraint_F3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(float 32.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_F4:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -16
|
||||
define i32 @inline_C_constraint_F4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 -16)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_F5:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffef
|
||||
define i32 @inline_C_constraint_F5() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i32 -17)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'C' constraint, 64-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_D0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xffffffff
|
||||
define i32 @inline_C_constraint_D0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 4294967295)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_D1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
|
||||
define i32 @inline_C_constraint_D1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 2147483648)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_C_constraint_D2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -16
|
||||
define i32 @inline_C_constraint_D2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 -16)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'C'
|
||||
define i32 @inline_C_constraint_D8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 -17)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'C'
|
||||
define i32 @inline_C_constraint_D9() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(i64 4294967296)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'C' constraint, v2x16 operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_V0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_C_constraint_V0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 32767, i16 32767>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_V1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_C_constraint_V1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 -1, i16 -1>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'C'
|
||||
; VI-LABEL: {{^}}inline_C_constraint_V2:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
|
||||
define i32 @inline_C_constraint_V2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 -32768, i16 -32768>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DA' constraint, 16-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 64
|
||||
define i32 @inline_DA_constraint_H0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 64)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -16
|
||||
define i32 @inline_DA_constraint_H1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 -16)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H2:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x3c00
|
||||
define i32 @inline_DA_constraint_H2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half 1.0 to i16))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H3:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0xbc00
|
||||
define i32 @inline_DA_constraint_H3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half -1.0 to i16))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H4:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x3118
|
||||
define i32 @inline_DA_constraint_H4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(half 0xH3118)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H5:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x3118
|
||||
define i32 @inline_DA_constraint_H5() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half 0xH3118 to i16))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_H6:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0xb800
|
||||
define i32 @inline_DA_constraint_H6() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(half -0.5)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_H7() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 bitcast (half 0xH3119 to i16))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_H8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 -17)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_H9() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 65)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DA' constraint, 32-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_F0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -16
|
||||
define i32 @inline_DA_constraint_F0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 -16)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_F1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 1
|
||||
define i32 @inline_DA_constraint_F1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 1)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_F2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xbf000000
|
||||
define i32 @inline_DA_constraint_F2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 bitcast (float -0.5 to i32))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_F3:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x40000000
|
||||
define i32 @inline_DA_constraint_F3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 bitcast (float 2.0 to i32))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_F4:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xc0800000
|
||||
define i32 @inline_DA_constraint_F4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(float -4.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_F5:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x3e22f983
|
||||
define i32 @inline_DA_constraint_F5() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 1042479491)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_F6:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x3f000000
|
||||
define i32 @inline_DA_constraint_F6() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(float 0.5)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_F7() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 65)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_F8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 -17)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DA' constraint, 64-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_D0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x40fffffff0
|
||||
define i32 @inline_DA_constraint_D0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x40fffffff0 to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_D1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xfffffff000000040
|
||||
define i32 @inline_DA_constraint_D1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0xfffffff000000040 to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_D2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_DA_constraint_D2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 -1)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DA_constraint_D3:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0xbf000000c0800000
|
||||
define i32 @inline_DA_constraint_D3() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0xbf000000c0800000 to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_D4:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x3e22f9833e22f983
|
||||
define i32 @inline_DA_constraint_D4() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x3e22f9833e22f983 to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_D5() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x0000004000000041 to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_D8() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(i64 bitcast (double 0x0000004100000040 to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_D9() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DA"(double 100.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DA' constraint, v2x16 operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_V0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -4
|
||||
define i32 @inline_DA_constraint_V0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i16> <i16 -4, i16 -4>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DA'
|
||||
; VI-LABEL: {{^}}inline_DA_constraint_V1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0xb800
|
||||
define i32 @inline_DA_constraint_V1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x half> <half -0.5, half -0.5>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_V2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i16> <i16 -4, i16 undef>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_V6() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(<2 x i32> <i32 0, i32 0>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DA' constraint, type errors
|
||||
;==============================================================================
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_E1(i32 %x) {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i32 %x)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DA'
|
||||
define i32 @inline_DA_constraint_E2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i128 100000000000000000000)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DB' constraint, 16-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DB'
|
||||
; VI-LABEL: {{^}}inline_DB_constraint_H0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_DB_constraint_H0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i16 32767)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DB'
|
||||
; VI-LABEL: {{^}}inline_DB_constraint_H1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_DB_constraint_H1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i16 65535)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DB'
|
||||
; VI-LABEL: {{^}}inline_DB_constraint_H2:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x4a80
|
||||
define i32 @inline_DB_constraint_H2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(half 13.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DB' constraint, 32-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DB_constraint_F0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_DB_constraint_F0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i32 4294967295)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DB_constraint_F1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x80000000
|
||||
define i32 @inline_DB_constraint_F1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i32 2147483648)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DB_constraint_F2:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x42000000
|
||||
define i32 @inline_DB_constraint_F2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(float 32.0)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DB' constraint, 64-bit operand
|
||||
;==============================================================================
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DB_constraint_D0:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_DB_constraint_D0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DB"(i64 -1)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}inline_DB_constraint_D1:
|
||||
; GCN: v_mov_b32 {{v[0-9]+}}, 0x1234567890abcdef
|
||||
define i32 @inline_DB_constraint_D1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1 >> 32", "=v,^DB"(i64 bitcast (double 0x1234567890abcdef to i64))
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DB' constraint, v2x16 operand
|
||||
;==============================================================================
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DB'
|
||||
; VI-LABEL: {{^}}inline_DB_constraint_V0:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
|
||||
define i32 @inline_DB_constraint_V0() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(<2 x i16> <i16 32767, i16 32767>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DB'
|
||||
; VI-LABEL: {{^}}inline_DB_constraint_V1:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, -1
|
||||
define i32 @inline_DB_constraint_V1() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(<2 x i16> <i16 65535, i16 65535>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOSI: error: invalid operand for inline asm constraint 'DB'
|
||||
; VI-LABEL: {{^}}inline_DB_constraint_V2:
|
||||
; VI: v_mov_b32 {{v[0-9]+}}, 0xd640
|
||||
define i32 @inline_DB_constraint_V2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(<2 x half> <half -100.0, half -100.0>)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
;==============================================================================
|
||||
; 'DB' constraint, type errors
|
||||
;==============================================================================
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DB'
|
||||
define i32 @inline_DB_constraint_E1(i32 %x) {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i32 %x)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
||||
; NOGCN: error: invalid operand for inline asm constraint 'DB'
|
||||
define i32 @inline_DB_constraint_E2() {
|
||||
%v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DB"(i128 100000000000000000000)
|
||||
ret i32 %v0
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue