forked from OSchip/llvm-project
parent
4fbd8a2f78
commit
1c80d37765
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@ -295,7 +295,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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const MachineInstrDescriptor &Desc = get(Opcode);
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// Print instruction prefixes if neccesary
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if (Desc.TSFlags & X86II::OpSize) O << "66 "; // Operand size...
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if (Desc.TSFlags & X86II::TB) O << "0F "; // Two-byte opcode prefix
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@ -304,6 +303,7 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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O << "\t\t\t";
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O << "-"; MI->print(O, TM);
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode));
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O << "\n\t\t\t\t";
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@ -316,7 +316,6 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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O << "\n";
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return;
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case X86II::AddRegFrm: {
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// There are currently two forms of acceptable AddRegFrm instructions.
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// Either the instruction JUST takes a single register (like inc, dec, etc),
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