This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3.

llvm-svn: 183733

llvm/lib/Target/ARM/ARMInstrVFP.td

@@ -1331,6 +1331,10 @@ let Uses = [FPSCR] in {
                               "vmrs", "\t$Rt, mvfr0", []>;
   def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
                               "vmrs", "\t$Rt, mvfr1", []>;
+  def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
+                              "vmrs", "\t$Rt, fpinst", []>;
+  def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
+                                "vmrs", "\t$Rt, fpinst2", []>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1364,6 +1368,11 @@ let Defs = [FPSCR] in {
   // System level GPR -> FPSID
   def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
                       "vmsr", "\tfpsid, $src", []>;
+
+  def VMSR_FPINST : MovToVFP<0b1001 /* fpinst */, (outs), (ins GPR:$src),
+                              "vmsr", "\tfpinst, $src", []>;
+  def VMSR_FPINST2 : MovToVFP<0b1010 /* fpinst2 */, (outs), (ins GPR:$src),
+                                "vmsr", "\tfpinst2, $src", []>;
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/ARM/ARMRegisterInfo.td

@@ -171,10 +171,12 @@ def FPSCR_NZCV : ARMReg<3,  "fpscr_nzcv"> {
 def ITSTATE    : ARMReg<4, "itstate">;
 
 // Special Registers - only available in privileged mode.
-def FPSID   : ARMReg<0, "fpsid">;
+def FPSID   : ARMReg<0,  "fpsid">;
-def MVFR1   : ARMReg<6, "mvfr1">;
+def MVFR1   : ARMReg<6,  "mvfr1">;
-def MVFR0   : ARMReg<7, "mvfr0">;
+def MVFR0   : ARMReg<7,  "mvfr0">;
-def FPEXC   : ARMReg<8, "fpexc">;
+def FPEXC   : ARMReg<8,  "fpexc">;
+def FPINST  : ARMReg<9,  "fpinst">;
+def FPINST2 : ARMReg<10, "fpinst2">;
 
 // Register classes.
 //

llvm/test/MC/ARM/simple-fp-encoding.s

@@ -157,6 +157,10 @@
         vmrs  r0, fpexc
 @ CHECK: vmrs  r0, fpsid             @ encoding: [0x10,0x0a,0xf0,0xee]
         vmrs  r0, fpsid
+@ CHECK: vmrs	r1, fpinst           @ encoding: [0x10,0x1a,0xf9,0xee]
+        vmrs r1, fpinst
+@ CHECK: vmrs	r8, fpinst2          @ encoding: [0x10,0x8a,0xfa,0xee]
+        vmrs r8, fpinst2
 
 @ CHECK: vmsr fpscr, r0              @ encoding: [0x10,0x0a,0xe1,0xee]
         vmsr    fpscr, r0
@@ -164,6 +168,10 @@
         vmsr  fpexc, r0
 @ CHECK: vmsr  fpsid, r0             @ encoding: [0x10,0x0a,0xe0,0xee]
         vmsr  fpsid, r0
+@ CHECK: vmsr	fpinst, r3           @ encoding: [0x10,0x3a,0xe9,0xee]
+        vmsr fpinst, r3	
+@ CHECK: vmsr	fpinst2, r4          @ encoding: [0x10,0x4a,0xea,0xee]
+        vmsr fpinst2, r4
 
         vmov.f64        d16, #3.000000e+00
         vmov.f32        s0, #3.000000e+00

llvm/test/MC/Disassembler/ARM/fp-encoding.txt

@@ -117,18 +117,26 @@
 # CHECK: vmoveq  s0, r1
 
 0x10 0x0a 0xf1 0xee
-# CHECK: vmrs    r0, fpscr
+# CHECK: vmrs  r0, fpscr
 0x10 0x0a 0xf8 0xee
 # CHECK: vmrs  r0, fpexc
 0x10 0x0a 0xf0 0xee
 # CHECK: vmrs  r0, fpsid
+0x10 0x1a 0xf9 0xee
+# CHECK: vmrs  r1, fpinst
+0x10 0x8a 0xfa 0xee
+# CHECK: vmrs  r8, fpinst2
 
 0x10 0x0a 0xe1 0xee
-# CHECK: vmsr    fpscr, r0
+# CHECK: vmsr  fpscr, r0
 0x10 0x0a 0xe8 0xee
 # CHECK: vmsr  fpexc, r0
 0x10 0x0a 0xe0 0xee
 # CHECK: vmsr  fpsid, r0
+0x10 0x3a 0xe9 0xee
+# CHECK: vmsr  fpinst, r3
+0x10 0x4a 0xea 0xee
+# CHECK: vmsr fpinst2, r4
 
 0x10 0x0a 0x00 0xee
 0x90 0x1a 0x00 0xee