forked from OSchip/llvm-project
parent
da312809d4
commit
1c752d8f5e
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@ -4466,13 +4466,15 @@ multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
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def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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" \t{$src3, $src2, $src1, $dst|"
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"$dst, $src1, $src2, $src3}"),
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[]>, EVEX_4V;
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let mayLoad = 1 in
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def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2, i8imm:$src3),
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!strconcat(OpcodeStr,
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" \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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" \t{$src3, $src2, $src1, $dst|"
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"$dst, $src1, $src2, $src3}"),
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[]>, EVEX_4V;
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}
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defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
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