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Fix miscompilation caused by trivial logic error in the reassignVReg() 

interference check.

llvm-svn: 121519
This commit is contained in:
Jakob Stoklund Olesen 2010-12-10 20:45:04 +00:00
parent 704e7c2332
commit 1c6196228a
1 changed files with 16 additions and 10 deletions
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26
llvm/lib/CodeGen/RegAllocGreedy.cpp
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@ -81,6 +81,7 @@ public:
static char ID; static char ID;
private: private:
bool checkUncachedInterference(LiveInterval &, unsigned);
bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg); bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg); bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
}; };
@ -146,6 +147,20 @@ float RAGreedy::getPriority(LiveInterval *LI) {
return Priority; return Priority;
} }
// Check interference without using the cache.
bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg,
unsigned PhysReg) {
LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[PhysReg]);
if (subQ.checkInterference())
return true;
for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
subQ.init(&VirtReg, &PhysReg2LiveUnion[*AliasI]);
if (subQ.checkInterference())
return true;
}
return false;
}
// Attempt to reassign this virtual register to a different physical register. // Attempt to reassign this virtual register to a different physical register.
// //
// FIXME: we are not yet caching these "second-level" interferences discovered // FIXME: we are not yet caching these "second-level" interferences discovered
@ -168,18 +183,9 @@ bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg)) if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
continue; continue;
// Instantiate a "subquery", not to be confused with the Queries array. if (checkUncachedInterference(InterferingVReg, PhysReg))
LiveIntervalUnion::Query subQ(&InterferingVReg,
&PhysReg2LiveUnion[PhysReg]);
if (subQ.checkInterference())
continue; continue;
for (const unsigned *AliasI = TRI->getAliasSet(PhysReg);
*AliasI; ++AliasI) {
subQ.init(&InterferingVReg, &PhysReg2LiveUnion[*AliasI]);
if (subQ.checkInterference())
continue;
}
DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " << DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
TRI->getName(OldPhysReg) << " to " << TRI->getName(PhysReg) << '\n'); TRI->getName(OldPhysReg) << " to " << TRI->getName(PhysReg) << '\n');