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[X86] Add patterns with and_flag_nocf for BLSI and TBM instructions. 

Fixes similar issues to r352306.

llvm-svn: 365705
This commit is contained in:
Craig Topper 2019-07-10 22:44:32 +00:00
parent 472ad62b70
commit 1c327c7e0a
3 changed files with 26 additions and 36 deletions
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25
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -2462,15 +2462,20 @@ let Predicates = [HasBMI] in {
(BLSI64rr GR64:$src)>;
// Versions to match flag producing ops.
def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, -1)),
(BLSR32rr GR32:$src)>;
def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, -1)),
(BLSR64rr GR64:$src)>;
def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, -1)),
(BLSMSK32rr GR32:$src)>;
def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, -1)),
(BLSMSK64rr GR64:$src)>;
def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, -1)),
(BLSR32rr GR32:$src)>;
def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, -1)),
(BLSR64rr GR64:$src)>;
def : Pat<(and_flag_nocf GR32:$src, (ineg GR32:$src)),
(BLSI32rr GR32:$src)>;
def : Pat<(and_flag_nocf GR64:$src, (ineg GR64:$src)),
(BLSI64rr GR64:$src)>;
}
multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC,
@ -2896,8 +2901,6 @@ let Predicates = [HasTBM] in {
(TZMSK64rr GR64:$src)>;
// Patterns to match flag producing ops.
// X86and_flag nodes are rarely created. Those should use CMP+AND. We do
// TESTrr matching in PostProcessISelDAG to allow BLSR/BLSI to be formed.
def : Pat<(or_flag_nocf GR32:$src, (not (add GR32:$src, 1))),
(BLCI32rr GR32:$src)>;
def : Pat<(or_flag_nocf GR64:$src, (not (add GR64:$src, 1))),
@ -2909,6 +2912,11 @@ let Predicates = [HasTBM] in {
def : Pat<(or_flag_nocf GR64:$src, (sub -2, GR64:$src)),
(BLCI64rr GR64:$src)>;
def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, 1)),
(BLCIC32rr GR32:$src)>;
def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, 1)),
(BLCIC64rr GR64:$src)>;
def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, 1)),
(BLCMSK32rr GR32:$src)>;
def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, 1)),
@ -2933,6 +2941,11 @@ let Predicates = [HasTBM] in {
(T1MSKC32rr GR32:$src)>;
def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, 1)),
(T1MSKC64rr GR64:$src)>;
def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, -1)),
(TZMSK32rr GR32:$src)>;
def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, -1)),
(TZMSK64rr GR64:$src)>;
} // HasTBM
//===----------------------------------------------------------------------===//

13
llvm/test/CodeGen/X86/bmi.ll
View File

@ -1154,10 +1154,7 @@ define i32 @blsi32_branch(i32 %x) {
; X86-NEXT: pushl %esi
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, %esi
; X86-NEXT: negl %esi
; X86-NEXT: andl %eax, %esi
; X86-NEXT: blsil {{[0-9]+}}(%esp), %esi
; X86-NEXT: jne .LBB48_2
; X86-NEXT: # %bb.1:
; X86-NEXT: calll bar
@ -1172,9 +1169,7 @@ define i32 @blsi32_branch(i32 %x) {
; X64-NEXT: pushq %rbx
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: movl %edi, %ebx
; X64-NEXT: negl %ebx
; X64-NEXT: andl %edi, %ebx
; X64-NEXT: blsil %edi, %ebx
; X64-NEXT: jne .LBB48_2
; X64-NEXT: # %bb.1:
; X64-NEXT: callq bar
@ -1229,9 +1224,7 @@ define i64 @blsi64_branch(i64 %x) {
; X64-NEXT: pushq %rbx
; X64-NEXT: .cfi_def_cfa_offset 16
; X64-NEXT: .cfi_offset %rbx, -16
; X64-NEXT: movq %rdi, %rbx
; X64-NEXT: negq %rbx
; X64-NEXT: andq %rdi, %rbx
; X64-NEXT: blsiq %rdi, %rbx
; X64-NEXT: jne .LBB49_2
; X64-NEXT: # %bb.1:
; X64-NEXT: callq bar

24
llvm/test/CodeGen/X86/tbm_patterns.ll
View File

@ -876,11 +876,7 @@ define i32 @blcic32_branch(i32 %x) nounwind {
; CHECK-LABEL: blcic32_branch:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: notl %eax
; CHECK-NEXT: incl %ebx
; CHECK-NEXT: andl %eax, %ebx
; CHECK-NEXT: blcicl %edi, %ebx
; CHECK-NEXT: jne .LBB69_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar
@ -903,11 +899,7 @@ define i64 @blcic64_branch(i64 %x) nounwind {
; CHECK-LABEL: blcic64_branch:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: incq %rbx
; CHECK-NEXT: andq %rax, %rbx
; CHECK-NEXT: blcicq %rdi, %rbx
; CHECK-NEXT: jne .LBB70_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar
@ -930,11 +922,7 @@ define i32 @tzmsk32_branch(i32 %x) nounwind {
; CHECK-LABEL: tzmsk32_branch:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movl %edi, %ebx
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: notl %eax
; CHECK-NEXT: decl %ebx
; CHECK-NEXT: andl %eax, %ebx
; CHECK-NEXT: tzmskl %edi, %ebx
; CHECK-NEXT: jne .LBB71_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar
@ -957,11 +945,7 @@ define i64 @tzmsk64_branch(i64 %x) nounwind {
; CHECK-LABEL: tzmsk64_branch:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: notq %rax
; CHECK-NEXT: decq %rbx
; CHECK-NEXT: andq %rax, %rbx
; CHECK-NEXT: tzmskq %rdi, %rbx
; CHECK-NEXT: jne .LBB72_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: callq bar