forked from OSchip/llvm-project
[GlobalISel][X86] Support vector type G_INSERT legalization/selection.
Summary: Support vector type G_INSERT legalization/selection. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33956 llvm-svn: 305989
This commit is contained in:
Igor Breger
parent
b489e56ae2
commit
1c29be7e4f
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@ -75,6 +75,12 @@ private:
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bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
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bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
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MachineFunction &MF) const;
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// emit insert subreg instruction and insert it before MachineInstr &I
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bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
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MachineRegisterInfo &MRI, MachineFunction &MF) const;
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const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
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const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
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@ -259,6 +265,8 @@ bool X86InstructionSelector::select(MachineInstr &I) const {
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return true;
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if (selectUadde(I, MRI, MF))
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return true;
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if (selectInsert(I, MRI, MF))
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return true;
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return false;
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}
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@ -703,6 +711,105 @@ bool X86InstructionSelector::selectUadde(MachineInstr &I,
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return true;
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}
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bool X86InstructionSelector::emitInsertSubreg(unsigned DstReg, unsigned SrcReg,
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MachineInstr &I,
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MachineRegisterInfo &MRI,
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MachineFunction &MF) const {
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const LLT DstTy = MRI.getType(DstReg);
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const LLT SrcTy = MRI.getType(SrcReg);
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unsigned SubIdx = X86::NoSubRegister;
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// TODO: support scalar types
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if (!DstTy.isVector() || !SrcTy.isVector())
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return false;
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assert(SrcTy.getSizeInBits() < DstTy.getSizeInBits() &&
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"Incorrect Src/Dst register size");
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if (SrcTy.getSizeInBits() == 128)
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SubIdx = X86::sub_xmm;
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else if (SrcTy.getSizeInBits() == 256)
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SubIdx = X86::sub_ymm;
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else
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return false;
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const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
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const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
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if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
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!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
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DEBUG(dbgs() << "Failed to constrain INSERT_SUBREG\n");
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return false;
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}
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BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
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.addReg(DstReg, RegState::DefineNoRead, SubIdx)
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.addReg(SrcReg);
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return true;
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}
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bool X86InstructionSelector::selectInsert(MachineInstr &I,
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MachineRegisterInfo &MRI,
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MachineFunction &MF) const {
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if (I.getOpcode() != TargetOpcode::G_INSERT)
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return false;
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const unsigned DstReg = I.getOperand(0).getReg();
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const unsigned SrcReg = I.getOperand(1).getReg();
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const unsigned InsertReg = I.getOperand(2).getReg();
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int64_t Index = I.getOperand(3).getImm();
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const LLT DstTy = MRI.getType(DstReg);
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const LLT InsertRegTy = MRI.getType(InsertReg);
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// Meanwile handle vector type only.
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if (!DstTy.isVector())
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return false;
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if (Index % InsertRegTy.getSizeInBits() != 0)
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return false; // Not insert subvector.
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if (Index == 0 && MRI.getVRegDef(SrcReg)->isImplicitDef()) {
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// Replace by subreg copy.
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if (!emitInsertSubreg(DstReg, InsertReg, I, MRI, MF))
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return false;
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I.eraseFromParent();
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return true;
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}
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bool HasAVX = STI.hasAVX();
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bool HasAVX512 = STI.hasAVX512();
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bool HasVLX = STI.hasVLX();
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if (DstTy.getSizeInBits() == 256 && InsertRegTy.getSizeInBits() == 128) {
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if (HasVLX)
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I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
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else if (HasAVX)
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I.setDesc(TII.get(X86::VINSERTF128rr));
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else
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return false;
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} else if (DstTy.getSizeInBits() == 512 && HasAVX512) {
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if (InsertRegTy.getSizeInBits() == 128)
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I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
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else if (InsertRegTy.getSizeInBits() == 256)
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I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
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else
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return false;
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} else
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return false;
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// Convert to X86 VINSERT immediate.
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Index = Index / InsertRegTy.getSizeInBits();
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I.getOperand(3).setImm(Index);
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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InstructionSelector *
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llvm::createX86InstructionSelector(const X86TargetMachine &TM,
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X86Subtarget &Subtarget,
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@ -214,12 +214,24 @@ void X86LegalizerInfo::setLegalizerInfoAVX() {
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if (!Subtarget.hasAVX())
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return;
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT v32s8 = LLT::vector(32, 8);
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const LLT v16s16 = LLT::vector(16, 16);
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const LLT v8s32 = LLT::vector(8, 32);
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const LLT v4s64 = LLT::vector(4, 64);
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for (unsigned MemOp : {G_LOAD, G_STORE})
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for (auto Ty : {v8s32, v4s64})
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setAction({MemOp, Ty}, Legal);
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for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
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setAction({G_INSERT, Ty}, Legal);
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for (auto Ty : {v16s8, v8s16, v4s32, v2s64})
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setAction({G_INSERT, 1, Ty}, Legal);
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}
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void X86LegalizerInfo::setLegalizerInfoAVX2() {
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@ -243,6 +255,18 @@ void X86LegalizerInfo::setLegalizerInfoAVX512() {
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if (!Subtarget.hasAVX512())
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return;
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const LLT v16s8 = LLT::vector(16, 8);
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const LLT v8s16 = LLT::vector(8, 16);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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const LLT v32s8 = LLT::vector(32, 8);
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const LLT v16s16 = LLT::vector(16, 16);
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const LLT v8s32 = LLT::vector(8, 32);
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const LLT v4s64 = LLT::vector(4, 64);
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const LLT v64s8 = LLT::vector(64, 8);
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const LLT v32s16 = LLT::vector(32, 16);
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const LLT v16s32 = LLT::vector(16, 32);
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const LLT v8s64 = LLT::vector(8, 64);
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@ -256,13 +280,15 @@ void X86LegalizerInfo::setLegalizerInfoAVX512() {
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for (auto Ty : {v16s32, v8s64})
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setAction({MemOp, Ty}, Legal);
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for (auto Ty : {v64s8, v32s16, v16s32, v8s64})
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setAction({G_INSERT, Ty}, Legal);
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for (auto Ty : {v32s8, v16s16, v8s32, v4s64, v16s8, v8s16, v4s32, v2s64})
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setAction({G_INSERT, 1, Ty}, Legal);
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/************ VLX *******************/
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if (!Subtarget.hasVLX())
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return;
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v8s32 = LLT::vector(8, 32);
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for (auto Ty : {v4s32, v8s32})
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setAction({G_MUL, Ty}, Legal);
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}
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@ -0,0 +1,33 @@
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
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--- |
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define void @test_insert_128() {
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ret void
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}
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...
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---
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name: test_insert_128
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# ALL-LABEL: name: test_insert_128
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<8 x s32>) = COPY %ymm0
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# ALL-NEXT: %1(<4 x s32>) = COPY %xmm1
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# ALL-NEXT: %2(<8 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
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# ALL-NEXT: %ymm0 = COPY %2(<8 x s32>)
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# ALL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = COPY %ymm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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@ -0,0 +1,63 @@
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define void @test_insert_128() {
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ret void
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}
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define void @test_insert_256() {
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ret void
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}
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...
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---
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name: test_insert_128
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# ALL-LABEL: name: test_insert_128
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<16 x s32>) = COPY %zmm0
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# ALL-NEXT: %1(<4 x s32>) = COPY %xmm1
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# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<4 x s32>), 0
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# ALL-NEXT: %ymm0 = COPY %2(<16 x s32>)
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# ALL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %zmm0, %ymm1
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%0(<16 x s32>) = COPY %zmm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
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%ymm0 = COPY %2(<16 x s32>)
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RET 0, implicit %ymm0
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...
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---
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name: test_insert_256
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# ALL-LABEL: name: test_insert_256
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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# ALL: %0(<16 x s32>) = COPY %zmm0
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# ALL-NEXT: %1(<8 x s32>) = COPY %ymm1
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# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<8 x s32>), 0
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# ALL-NEXT: %ymm0 = COPY %2(<16 x s32>)
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# ALL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %zmm0, %ymm1
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%0(<16 x s32>) = COPY %zmm0
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%1(<8 x s32>) = COPY %ymm1
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%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
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%ymm0 = COPY %2(<16 x s32>)
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RET 0, implicit %ymm0
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...
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@ -0,0 +1,176 @@
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
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--- |
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define void @test_insert_128_idx0() {
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ret void
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}
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define void @test_insert_128_idx0_undef() {
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ret void
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}
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define void @test_insert_128_idx1() {
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ret void
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}
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define void @test_insert_128_idx1_undef() {
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ret void
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}
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...
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---
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name: test_insert_128_idx0
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# ALL-LABEL: name: test_insert_128_idx0
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# AVX: %0 = COPY %ymm0
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# AVX-NEXT: %1 = COPY %xmm1
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# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 0
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# AVX-NEXT: %ymm0 = COPY %2
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# AVX-NEXT: RET 0, implicit %ymm0
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#
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# AVX512VL: %0 = COPY %ymm0
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# AVX512VL-NEXT: %1 = COPY %xmm1
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# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 0
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# AVX512VL-NEXT: %ymm0 = COPY %2
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# AVX512VL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = COPY %ymm0
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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---
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name: test_insert_128_idx0_undef
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# ALL-LABEL: name: test_insert_128_idx0_undef
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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# ALL: %1 = COPY %xmm1
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# ALL-NEXT: undef %2.sub_xmm = COPY %1
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# ALL-NEXT: %ymm0 = COPY %2
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# ALL-NEXT: RET 0, implicit %ymm0
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body: |
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bb.1 (%ir-block.0):
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liveins: %ymm0, %ymm1
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%0(<8 x s32>) = IMPLICIT_DEF
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%1(<4 x s32>) = COPY %xmm1
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%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 0
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%ymm0 = COPY %2(<8 x s32>)
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RET 0, implicit %ymm0
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...
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---
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name: test_insert_128_idx1
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# ALL-LABEL: name: test_insert_128_idx1
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alignment: 4
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legalized: true
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regBankSelected: true
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# AVX: registers:
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# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
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# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
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# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
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#
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# AVX512VL: registers:
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# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
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# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
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registers:
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- { id: 0, class: vecr }
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||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# AVX: %0 = COPY %ymm0
|
||||
# AVX-NEXT: %1 = COPY %xmm1
|
||||
# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1
|
||||
# AVX-NEXT: %ymm0 = COPY %2
|
||||
# AVX-NEXT: RET 0, implicit %ymm0
|
||||
#
|
||||
# AVX512VL: %0 = COPY %ymm0
|
||||
# AVX512VL-NEXT: %1 = COPY %xmm1
|
||||
# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1
|
||||
# AVX512VL-NEXT: %ymm0 = COPY %2
|
||||
# AVX512VL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<8 x s32>) = COPY %ymm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
|
||||
%ymm0 = COPY %2(<8 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx1_undef
|
||||
# ALL-LABEL: name: test_insert_128_idx1_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# AVX: registers:
|
||||
# AVX-NEXT: - { id: 0, class: vr256, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 1, class: vr128, preferred-register: '' }
|
||||
# AVX-NEXT: - { id: 2, class: vr256, preferred-register: '' }
|
||||
#
|
||||
# AVX512VL: registers:
|
||||
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# AVX: %0 = IMPLICIT_DEF
|
||||
# AVX-NEXT: %1 = COPY %xmm1
|
||||
# AVX-NEXT: %2 = VINSERTF128rr %0, %1, 1
|
||||
# AVX-NEXT: %ymm0 = COPY %2
|
||||
# AVX-NEXT: RET 0, implicit %ymm0
|
||||
#
|
||||
# AVX512VL: %0 = IMPLICIT_DEF
|
||||
# AVX512VL-NEXT: %1 = COPY %xmm1
|
||||
# AVX512VL-NEXT: %2 = VINSERTF32x4Z256rr %0, %1, 1
|
||||
# AVX512VL-NEXT: %ymm0 = COPY %2
|
||||
# AVX512VL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<8 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<8 x s32>) = G_INSERT %0(<8 x s32>), %1(<4 x s32>), 128
|
||||
%ymm0 = COPY %2(<8 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
...
|
||||
|
||||
|
|
@ -0,0 +1,271 @@
|
|||
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
|
||||
|
||||
--- |
|
||||
define void @test_insert_128_idx0() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_128_idx0_undef() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_128_idx1() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_128_idx1_undef() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_256_idx0() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_256_idx0_undef() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_256_idx1() {
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_insert_256_idx1_undef() {
|
||||
ret void
|
||||
}
|
||||
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx0
|
||||
# ALL-LABEL: name: test_insert_128_idx0
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %xmm1
|
||||
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 0
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx0_undef
|
||||
# ALL-LABEL: name: test_insert_128_idx0_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %1 = COPY %xmm1
|
||||
# ALL-NEXT: undef %2.sub_xmm = COPY %1
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx1
|
||||
# ALL-LABEL: name: test_insert_128_idx1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %xmm1
|
||||
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
...
|
||||
---
|
||||
name: test_insert_128_idx1_undef
|
||||
# ALL-LABEL: name: test_insert_128_idx1_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr128x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %1 = COPY %xmm1
|
||||
# ALL-NEXT: %2 = VINSERTF32x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<4 x s32>) = COPY %xmm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx0
|
||||
# ALL-LABEL: name: test_insert_256_idx0
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %ymm1
|
||||
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 0
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %zmm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx0_undef
|
||||
# ALL-LABEL: name: test_insert_256_idx0_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vecr, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %1 = COPY %ymm1
|
||||
# ALL-NEXT: undef %2.sub_ymm = COPY %1
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx1
|
||||
# ALL-LABEL: name: test_insert_256_idx1
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = COPY %zmm0
|
||||
# ALL-NEXT: %1 = COPY %ymm1
|
||||
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = COPY %zmm0
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
...
|
||||
---
|
||||
name: test_insert_256_idx1_undef
|
||||
# ALL-LABEL: name: test_insert_256_idx1_undef
|
||||
alignment: 4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
# ALL: registers:
|
||||
# ALL-NEXT: - { id: 0, class: vr512, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
|
||||
# ALL-NEXT: - { id: 2, class: vr512, preferred-register: '' }
|
||||
registers:
|
||||
- { id: 0, class: vecr }
|
||||
- { id: 1, class: vecr }
|
||||
- { id: 2, class: vecr }
|
||||
# ALL: %0 = IMPLICIT_DEF
|
||||
# ALL-NEXT: %1 = COPY %ymm1
|
||||
# ALL-NEXT: %2 = VINSERTF64x4Zrr %0, %1, 1
|
||||
# ALL-NEXT: %ymm0 = COPY %2
|
||||
# ALL-NEXT: RET 0, implicit %ymm0
|
||||
body: |
|
||||
bb.1 (%ir-block.0):
|
||||
liveins: %ymm0, %ymm1
|
||||
|
||||
%0(<16 x s32>) = IMPLICIT_DEF
|
||||
%1(<8 x s32>) = COPY %ymm1
|
||||
%2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256
|
||||
%ymm0 = COPY %2(<16 x s32>)
|
||||
RET 0, implicit %ymm0
|
||||
...
|
||||
|
||||
Loading…
Reference in New Issue