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The subtarget in MipsTargetLowering isn't going to change and 

so doesn't need to be a pointer, but a reference.

llvm-svn: 213422
This commit is contained in:
Eric Christopher 2014-07-18 22:55:25 +00:00
parent 2f12195b1d
commit 1c29a657c7
4 changed files with 144 additions and 143 deletions
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2
llvm/lib/Target/Mips/Mips16ISelLowering.cpp
View File

@ -427,7 +427,7 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
const char* Mips16HelperFunction = nullptr; const char* Mips16HelperFunction = nullptr;
bool NeedMips16Helper = false; bool NeedMips16Helper = false;
if (Subtarget->inMips16HardFloat()) { if (Subtarget.inMips16HardFloat()) {
// //
// currently we don't have symbols tagged with the mips16 or mips32 // currently we don't have symbols tagged with the mips16 or mips32
// qualifier so we will assume that we don't know what kind it is. // qualifier so we will assume that we don't know what kind it is.

185
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -210,14 +210,14 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
: TargetLowering(TM, new MipsTargetObjectFile()), : TargetLowering(TM, new MipsTargetObjectFile()),
Subtarget(&TM.getSubtarget<MipsSubtarget>()) { Subtarget(TM.getSubtarget<MipsSubtarget>()) {
// Mips does not have i1 type, so use i32 for // Mips does not have i1 type, so use i32 for
// setcc operations results (slt, sgt, ...). // setcc operations results (slt, sgt, ...).
setBooleanContents(ZeroOrOneBooleanContent); setBooleanContents(ZeroOrOneBooleanContent);
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
// The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
// does. Integer booleans still use 0 and 1. // does. Integer booleans still use 0 and 1.
if (Subtarget->hasMips32r6()) if (Subtarget.hasMips32r6())
setBooleanContents(ZeroOrOneBooleanContent, setBooleanContents(ZeroOrOneBooleanContent,
ZeroOrNegativeOneBooleanContent); ZeroOrNegativeOneBooleanContent);
@ -256,7 +256,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
if (Subtarget->isGP64bit()) { if (Subtarget.isGP64bit()) {
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom); setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
@ -268,14 +268,14 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
} }
if (!Subtarget->isGP64bit()) { if (!Subtarget.isGP64bit()) {
setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
} }
setOperationAction(ISD::ADD, MVT::i32, Custom); setOperationAction(ISD::ADD, MVT::i32, Custom);
if (Subtarget->isGP64bit()) if (Subtarget.isGP64bit())
setOperationAction(ISD::ADD, MVT::i64, Custom); setOperationAction(ISD::ADD, MVT::i64, Custom);
setOperationAction(ISD::SDIV, MVT::i32, Expand); setOperationAction(ISD::SDIV, MVT::i32, Expand);
@ -299,7 +299,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
if (Subtarget->hasCnMips()) { if (Subtarget.hasCnMips()) {
setOperationAction(ISD::CTPOP, MVT::i32, Legal); setOperationAction(ISD::CTPOP, MVT::i32, Legal);
setOperationAction(ISD::CTPOP, MVT::i64, Legal); setOperationAction(ISD::CTPOP, MVT::i64, Legal);
} else { } else {
@ -317,10 +317,10 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
if (!Subtarget->hasMips32r2()) if (!Subtarget.hasMips32r2())
setOperationAction(ISD::ROTR, MVT::i32, Expand); setOperationAction(ISD::ROTR, MVT::i32, Expand);
if (!Subtarget->hasMips64r2()) if (!Subtarget.hasMips64r2())
setOperationAction(ISD::ROTR, MVT::i64, Expand); setOperationAction(ISD::ROTR, MVT::i64, Expand);
setOperationAction(ISD::FSIN, MVT::f32, Expand); setOperationAction(ISD::FSIN, MVT::f32, Expand);
@ -358,23 +358,23 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setInsertFencesForAtomic(true); setInsertFencesForAtomic(true);
if (!Subtarget->hasMips32r2()) { if (!Subtarget.hasMips32r2()) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
} }
// MIPS16 lacks MIPS32's clz and clo instructions. // MIPS16 lacks MIPS32's clz and clo instructions.
if (!Subtarget->hasMips32() || Subtarget->inMips16Mode()) if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
setOperationAction(ISD::CTLZ, MVT::i32, Expand); setOperationAction(ISD::CTLZ, MVT::i32, Expand);
if (!Subtarget->hasMips64()) if (!Subtarget.hasMips64())
setOperationAction(ISD::CTLZ, MVT::i64, Expand); setOperationAction(ISD::CTLZ, MVT::i64, Expand);
if (!Subtarget->hasMips32r2()) if (!Subtarget.hasMips32r2())
setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand);
if (!Subtarget->hasMips64r2()) if (!Subtarget.hasMips64r2())
setOperationAction(ISD::BSWAP, MVT::i64, Expand); setOperationAction(ISD::BSWAP, MVT::i64, Expand);
if (Subtarget->isGP64bit()) { if (Subtarget.isGP64bit()) {
setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
@ -390,17 +390,17 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setTargetDAGCombine(ISD::OR); setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::ADD);
setMinFunctionAlignment(Subtarget->isGP64bit() ? 3 : 2); setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
setStackPointerRegisterToSaveRestore(Subtarget->isABI_N64() ? Mips::SP_64 setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64
: Mips::SP); : Mips::SP);
setExceptionPointerRegister(Subtarget->isABI_N64() ? Mips::A0_64 : Mips::A0); setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0);
setExceptionSelectorRegister(Subtarget->isABI_N64() ? Mips::A1_64 : Mips::A1); setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1);
MaxStoresPerMemcpy = 16; MaxStoresPerMemcpy = 16;
isMicroMips = Subtarget->inMicroMipsMode(); isMicroMips = Subtarget.inMicroMipsMode();
} }
const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) {
@ -427,7 +427,7 @@ EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
if (DCI.isBeforeLegalizeOps()) if (DCI.isBeforeLegalizeOps())
return SDValue(); return SDValue();
@ -537,7 +537,7 @@ static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
if (DCI.isBeforeLegalizeOps()) if (DCI.isBeforeLegalizeOps())
return SDValue(); return SDValue();
@ -616,11 +616,11 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
// Pattern match EXT. // Pattern match EXT.
// $dst = and ((sra or srl) $src , pos), (2**size - 1) // $dst = and ((sra or srl) $src , pos), (2**size - 1)
// => ext $dst, $src, size, pos // => ext $dst, $src, size, pos
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
return SDValue(); return SDValue();
SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
@ -656,12 +656,12 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
// Pattern match INS. // Pattern match INS.
// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
// where mask1 = (2**size - 1) << pos, mask0 = ~mask1 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
// => ins $dst, $src, size, pos, $src1 // => ins $dst, $src, size, pos, $src1
if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
return SDValue(); return SDValue();
SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
@ -710,7 +710,7 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
if (DCI.isBeforeLegalizeOps()) if (DCI.isBeforeLegalizeOps())
@ -968,16 +968,16 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
LL = Mips::LL_MM; LL = Mips::LL_MM;
SC = Mips::SC_MM; SC = Mips::SC_MM;
} else { } else {
LL = Subtarget->hasMips32r6() ? Mips::LL : Mips::LL_R6; LL = Subtarget.hasMips32r6() ? Mips::LL : Mips::LL_R6;
SC = Subtarget->hasMips32r6() ? Mips::SC : Mips::SC_R6; SC = Subtarget.hasMips32r6() ? Mips::SC : Mips::SC_R6;
} }
AND = Mips::AND; AND = Mips::AND;
NOR = Mips::NOR; NOR = Mips::NOR;
ZERO = Mips::ZERO; ZERO = Mips::ZERO;
BEQ = Mips::BEQ; BEQ = Mips::BEQ;
} else { } else {
LL = Subtarget->hasMips64r6() ? Mips::LLD : Mips::LLD_R6; LL = Subtarget.hasMips64r6() ? Mips::LLD : Mips::LLD_R6;
SC = Subtarget->hasMips64r6() ? Mips::SCD : Mips::SCD_R6; SC = Subtarget.hasMips64r6() ? Mips::SCD : Mips::SCD_R6;
AND = Mips::AND64; AND = Mips::AND64;
NOR = Mips::NOR64; NOR = Mips::NOR64;
ZERO = Mips::ZERO_64; ZERO = Mips::ZERO_64;
@ -1045,12 +1045,12 @@ MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
if (Subtarget->hasMips32r2() && Size == 1) { if (Subtarget.hasMips32r2() && Size == 1) {
BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
return BB; return BB;
} }
if (Subtarget->hasMips32r2() && Size == 2) { if (Subtarget.hasMips32r2() && Size == 2) {
BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
return BB; return BB;
} }
@ -1140,7 +1140,7 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
.addReg(Ptr).addReg(MaskLSB2); .addReg(Ptr).addReg(MaskLSB2);
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
if (Subtarget->isLittle()) { if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else { } else {
unsigned Off = RegInfo.createVirtualRegister(RC); unsigned Off = RegInfo.createVirtualRegister(RC);
@ -1380,7 +1380,7 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
.addReg(Ptr).addReg(MaskLSB2); .addReg(Ptr).addReg(MaskLSB2);
BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
if (Subtarget->isLittle()) { if (Subtarget.isLittle()) {
BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
} else { } else {
unsigned Off = RegInfo.createVirtualRegister(RC); unsigned Off = RegInfo.createVirtualRegister(RC);
@ -1491,7 +1491,7 @@ SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
Chain = Addr.getValue(1); Chain = Addr.getValue(1);
if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) ||
Subtarget->isABI_N64()) { Subtarget.isABI_N64()) {
// For PIC, the sequence is: // For PIC, the sequence is:
// BRIND(load(Jumptable + index) + RelocBase) // BRIND(load(Jumptable + index) + RelocBase)
// RelocBase can be JumpTable, GOT or some sort of global base. // RelocBase can be JumpTable, GOT or some sort of global base.
@ -1509,7 +1509,7 @@ SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
SDValue Dest = Op.getOperand(2); SDValue Dest = Op.getOperand(2);
SDLoc DL(Op); SDLoc DL(Op);
assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6()); assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
// Return if flag is not set by a floating point comparison. // Return if flag is not set by a floating point comparison.
@ -1529,7 +1529,7 @@ SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
lowerSELECT(SDValue Op, SelectionDAG &DAG) const lowerSELECT(SDValue Op, SelectionDAG &DAG) const
{ {
assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6()); assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
// Return if flag is not set by a floating point comparison. // Return if flag is not set by a floating point comparison.
@ -1555,7 +1555,7 @@ lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
} }
SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6()); assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue Cond = createFPCmp(DAG, Op); SDValue Cond = createFPCmp(DAG, Op);
assert(Cond.getOpcode() == MipsISD::FPCmp && assert(Cond.getOpcode() == MipsISD::FPCmp &&
@ -1576,7 +1576,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
const GlobalValue *GV = N->getGlobal(); const GlobalValue *GV = N->getGlobal();
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64()) { !Subtarget.isABI_N64()) {
const MipsTargetObjectFile &TLOF = const MipsTargetObjectFile &TLOF =
(const MipsTargetObjectFile&)getObjFileLowering(); (const MipsTargetObjectFile&)getObjFileLowering();
@ -1596,7 +1596,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
return getAddrLocal(N, Ty, DAG, return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64()); Subtarget.isABI_N32() || Subtarget.isABI_N64());
if (LargeGOT) if (LargeGOT)
return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16,
@ -1604,7 +1604,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
MachinePointerInfo::getGOT()); MachinePointerInfo::getGOT());
return getAddrGlobal(N, Ty, DAG, return getAddrGlobal(N, Ty, DAG,
(Subtarget->isABI_N32() || Subtarget->isABI_N64()) (Subtarget.isABI_N32() || Subtarget.isABI_N64())
? MipsII::MO_GOT_DISP ? MipsII::MO_GOT_DISP
: MipsII::MO_GOT16, : MipsII::MO_GOT16,
DAG.getEntryNode(), MachinePointerInfo::getGOT()); DAG.getEntryNode(), MachinePointerInfo::getGOT());
@ -1616,11 +1616,11 @@ SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
EVT Ty = Op.getValueType(); EVT Ty = Op.getValueType();
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64()) !Subtarget.isABI_N64())
return getAddrNonPIC(N, Ty, DAG); return getAddrNonPIC(N, Ty, DAG);
return getAddrLocal(N, Ty, DAG, return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64()); Subtarget.isABI_N32() || Subtarget.isABI_N64());
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
@ -1709,11 +1709,11 @@ lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
EVT Ty = Op.getValueType(); EVT Ty = Op.getValueType();
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64()) !Subtarget.isABI_N64())
return getAddrNonPIC(N, Ty, DAG); return getAddrNonPIC(N, Ty, DAG);
return getAddrLocal(N, Ty, DAG, return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64()); Subtarget.isABI_N32() || Subtarget.isABI_N64());
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
@ -1732,11 +1732,11 @@ lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
EVT Ty = Op.getValueType(); EVT Ty = Op.getValueType();
if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && if (getTargetMachine().getRelocationModel() != Reloc::PIC_ &&
!Subtarget->isABI_N64()) !Subtarget.isABI_N64())
return getAddrNonPIC(N, Ty, DAG); return getAddrNonPIC(N, Ty, DAG);
return getAddrLocal(N, Ty, DAG, return getAddrLocal(N, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64()); Subtarget.isABI_N32() || Subtarget.isABI_N64());
} }
SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
@ -1851,10 +1851,10 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
SDValue SDValue
MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
if (Subtarget->isGP64bit()) if (Subtarget.isGP64bit())
return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert()); return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
@ -1869,7 +1869,7 @@ lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op); SDLoc DL(Op);
SDValue FrameAddr = SDValue FrameAddr =
DAG.getCopyFromReg(DAG.getEntryNode(), DL, DAG.getCopyFromReg(DAG.getEntryNode(), DL,
Subtarget->isABI_N64() ? Mips::FP_64 : Mips::FP, VT); Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT);
return FrameAddr; return FrameAddr;
} }
@ -1885,7 +1885,7 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
unsigned RA = Subtarget->isABI_N64() ? Mips::RA_64 : Mips::RA; unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA;
MFI->setReturnAddressIsTaken(true); MFI->setReturnAddressIsTaken(true);
// Return RA, which contains the return address. Mark it an implicit live-in. // Return RA, which contains the return address. Mark it an implicit live-in.
@ -1907,12 +1907,12 @@ SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
SDValue Offset = Op.getOperand(1); SDValue Offset = Op.getOperand(1);
SDValue Handler = Op.getOperand(2); SDValue Handler = Op.getOperand(2);
SDLoc DL(Op); SDLoc DL(Op);
EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32; EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
// Store stack offset in V1, store jump target in V0. Glue CopyToReg and // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
// EH_RETURN nodes, so that instructions are emitted back-to-back. // EH_RETURN nodes, so that instructions are emitted back-to-back.
unsigned OffsetReg = Subtarget->isABI_N64() ? Mips::V1_64 : Mips::V1; unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1;
unsigned AddrReg = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0; unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
@ -2025,7 +2025,7 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
LoadSDNode *LD = cast<LoadSDNode>(Op); LoadSDNode *LD = cast<LoadSDNode>(Op);
EVT MemVT = LD->getMemoryVT(); EVT MemVT = LD->getMemoryVT();
if (Subtarget->systemSupportsUnalignedAccess()) if (Subtarget.systemSupportsUnalignedAccess())
return Op; return Op;
// Return if load is aligned or if MemVT is neither i32 nor i64. // Return if load is aligned or if MemVT is neither i32 nor i64.
@ -2033,7 +2033,7 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
((MemVT != MVT::i32) && (MemVT != MVT::i64))) ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
return SDValue(); return SDValue();
bool IsLittle = Subtarget->isLittle(); bool IsLittle = Subtarget.isLittle();
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
ISD::LoadExtType ExtType = LD->getExtensionType(); ISD::LoadExtType ExtType = LD->getExtensionType();
SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
@ -2151,10 +2151,10 @@ SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
EVT MemVT = SD->getMemoryVT(); EVT MemVT = SD->getMemoryVT();
// Lower unaligned integer stores. // Lower unaligned integer stores.
if (!Subtarget->systemSupportsUnalignedAccess() && if (!Subtarget.systemSupportsUnalignedAccess() &&
(SD->getAlignment() < MemVT.getSizeInBits() / 8) && (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
((MemVT == MVT::i32) || (MemVT == MVT::i64))) ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
return lowerFP_TO_SINT_STORE(SD, DAG); return lowerFP_TO_SINT_STORE(SD, DAG);
} }
@ -2340,8 +2340,8 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
// in PIC mode) allow symbols to be resolved via lazy binding. // in PIC mode) allow symbols to be resolved via lazy binding.
// The lazy binding stub requires GP to point to the GOT. // The lazy binding stub requires GP to point to the GOT.
if (IsPICCall && !InternalLinkage) { if (IsPICCall && !InternalLinkage) {
unsigned GPReg = Subtarget->isABI_N64() ? Mips::GP_64 : Mips::GP; unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP;
EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32; EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32;
RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
} }
@ -2367,7 +2367,7 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv);
assert(Mask && "Missing call preserved mask for calling convention"); assert(Mask && "Missing call preserved mask for calling convention");
if (Subtarget->inMips16HardFloat()) { if (Subtarget.inMips16HardFloat()) {
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
llvm::StringRef Sym = G->getGlobal()->getName(); llvm::StringRef Sym = G->getGlobal()->getName();
Function *F = G->getGlobal()->getParent()->getFunction(Sym); Function *F = G->getGlobal()->getParent()->getFunction(Sym);
@ -2410,11 +2410,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
getTargetMachine(), ArgLocs, *DAG.getContext()); getTargetMachine(), ArgLocs, *DAG.getContext());
MipsCC::SpecialCallingConvType SpecialCallingConv = MipsCC::SpecialCallingConvType SpecialCallingConv =
getSpecialCallingConv(Callee); getSpecialCallingConv(Callee);
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
CCInfo, SpecialCallingConv); CCInfo, SpecialCallingConv);
MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, MipsCCInfo.analyzeCallOperands(Outs, IsVarArg,
Subtarget->abiUsesSoftFloat(), Subtarget.abiUsesSoftFloat(),
Callee.getNode(), CLI.getArgs()); Callee.getNode(), CLI.getArgs());
// Get a count of how many bytes are to be pushed on the stack. // Get a count of how many bytes are to be pushed on the stack.
@ -2444,7 +2444,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
SDValue StackPtr = DAG.getCopyFromReg( SDValue StackPtr = DAG.getCopyFromReg(
Chain, DL, Subtarget->isABI_N64() ? Mips::SP_64 : Mips::SP, Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP,
getPointerTy()); getPointerTy());
// With EABI is it possible to have 16 args on registers. // With EABI is it possible to have 16 args on registers.
@ -2467,7 +2467,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
assert(!IsTailCall && assert(!IsTailCall &&
"Do not tail-call optimize if there is a byval argument."); "Do not tail-call optimize if there is a byval argument.");
passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); MipsCCInfo, *ByValArg, Flags, Subtarget.isLittle());
++ByValArg; ++ByValArg;
continue; continue;
} }
@ -2486,7 +2486,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
Arg, DAG.getConstant(0, MVT::i32)); Arg, DAG.getConstant(0, MVT::i32));
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Arg, DAG.getConstant(1, MVT::i32)); Arg, DAG.getConstant(1, MVT::i32));
if (!Subtarget->isLittle()) if (!Subtarget.isLittle())
std::swap(Lo, Hi); std::swap(Lo, Hi);
unsigned LocRegLo = VA.getLocReg(); unsigned LocRegLo = VA.getLocReg();
unsigned LocRegHigh = getNextIntArgReg(LocRegLo); unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
@ -2532,7 +2532,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it. // node so that legalize doesn't hack it.
bool IsPICCall = bool IsPICCall =
(Subtarget->isABI_N64() || IsPIC); // true if calls are translated to (Subtarget.isABI_N64() || IsPIC); // true if calls are translated to
// jalr $25 // jalr $25
bool GlobalOrExternal = false, InternalLinkage = false; bool GlobalOrExternal = false, InternalLinkage = false;
SDValue CalleeLo; SDValue CalleeLo;
@ -2545,7 +2545,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (InternalLinkage) if (InternalLinkage)
Callee = getAddrLocal(G, Ty, DAG, Callee = getAddrLocal(G, Ty, DAG,
Subtarget->isABI_N32() || Subtarget->isABI_N64()); Subtarget.isABI_N32() || Subtarget.isABI_N64());
else if (LargeGOT) else if (LargeGOT)
Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16,
MipsII::MO_CALL_LO16, Chain, MipsII::MO_CALL_LO16, Chain,
@ -2561,7 +2561,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
const char *Sym = S->getSymbol(); const char *Sym = S->getSymbol();
if (!Subtarget->isABI_N64() && !IsPIC) // !N64 && static if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static
Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(),
MipsII::MO_NO_FLAG); MipsII::MO_NO_FLAG);
else if (LargeGOT) else if (LargeGOT)
@ -2612,10 +2612,10 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
getTargetMachine(), RVLocs, *DAG.getContext()); getTargetMachine(), RVLocs, *DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
CCInfo); CCInfo);
MipsCCInfo.analyzeCallResult(Ins, Subtarget->abiUsesSoftFloat(), MipsCCInfo.analyzeCallResult(Ins, Subtarget.abiUsesSoftFloat(),
CallNode, RetTy); CallNode, RetTy);
// Copy all of the result registers out of their specified physreg. // Copy all of the result registers out of their specified physreg.
@ -2660,11 +2660,11 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
getTargetMachine(), ArgLocs, *DAG.getContext()); getTargetMachine(), ArgLocs, *DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
CCInfo); CCInfo);
Function::const_arg_iterator FuncArg = Function::const_arg_iterator FuncArg =
DAG.getMachineFunction().getFunction()->arg_begin(); DAG.getMachineFunction().getFunction()->arg_begin();
bool UseSoftFloat = Subtarget->abiUsesSoftFloat(); bool UseSoftFloat = Subtarget.abiUsesSoftFloat();
MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg);
MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
@ -2723,12 +2723,12 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
(RegVT == MVT::i64 && ValVT == MVT::f64) || (RegVT == MVT::i64 && ValVT == MVT::f64) ||
(RegVT == MVT::f64 && ValVT == MVT::i64)) (RegVT == MVT::f64 && ValVT == MVT::i64))
ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
else if (Subtarget->isABI_O32() && RegVT == MVT::i32 && else if (Subtarget.isABI_O32() && RegVT == MVT::i32 &&
ValVT == MVT::f64) { ValVT == MVT::f64) {
unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
getNextIntArgReg(ArgReg), RC); getNextIntArgReg(ArgReg), RC);
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
if (!Subtarget->isLittle()) if (!Subtarget.isLittle())
std::swap(ArgValue, ArgValue2); std::swap(ArgValue, ArgValue2);
ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
ArgValue, ArgValue2); ArgValue, ArgValue2);
@ -2762,7 +2762,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
unsigned Reg = MipsFI->getSRetReturnReg(); unsigned Reg = MipsFI->getSRetReturnReg();
if (!Reg) { if (!Reg) {
Reg = MF.getRegInfo().createVirtualRegister( Reg = MF.getRegInfo().createVirtualRegister(
getRegClassFor(Subtarget->isABI_N64() ? MVT::i64 : MVT::i32)); getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32));
MipsFI->setSRetReturnReg(Reg); MipsFI->setSRetReturnReg(Reg);
} }
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
@ -2813,11 +2813,11 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
// CCState - Info about the registers and stack slot. // CCState - Info about the registers and stack slot.
CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs,
*DAG.getContext()); *DAG.getContext());
MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), MipsCC MipsCCInfo(CallConv, Subtarget.isABI_O32(), Subtarget.isFP64bit(),
CCInfo); CCInfo);
// Analyze return values. // Analyze return values.
MipsCCInfo.analyzeReturn(Outs, Subtarget->abiUsesSoftFloat(), MipsCCInfo.analyzeReturn(Outs, Subtarget.abiUsesSoftFloat(),
MF.getFunction()->getReturnType()); MF.getFunction()->getReturnType());
SDValue Flag; SDValue Flag;
@ -2850,7 +2850,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
if (!Reg) if (!Reg)
llvm_unreachable("sret virtual register not created in the entry block"); llvm_unreachable("sret virtual register not created in the entry block");
SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
unsigned V0 = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0; unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0;
Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
Flag = Chain.getValue(1); Flag = Chain.getValue(1);
@ -2928,7 +2928,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
weight = CW_Register; weight = CW_Register;
break; break;
case 'f': // FPU or MSA register case 'f': // FPU or MSA register
if (Subtarget->hasMSA() && type->isVectorTy() && if (Subtarget.hasMSA() && type->isVectorTy() &&
cast<VectorType>(type)->getBitWidth() == 128) cast<VectorType>(type)->getBitWidth() == 128)
weight = CW_Register; weight = CW_Register;
else if (type->isFloatTy()) else if (type->isFloatTy())
@ -3034,7 +3034,7 @@ parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
// If the size of FP registers is 64-bit or Reg is an even number, select // If the size of FP registers is 64-bit or Reg is an even number, select
// the 64-bit register class. Otherwise, select the 32-bit register class. // the 64-bit register class. Otherwise, select the 32-bit register class.
if (VT == MVT::Other) if (VT == MVT::Other)
VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
RC = getRegClassFor(VT); RC = getRegClassFor(VT);
@ -3067,13 +3067,13 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
case 'y': // Same as 'r'. Exists for compatibility. case 'y': // Same as 'r'. Exists for compatibility.
case 'r': case 'r':
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
if (Subtarget->inMips16Mode()) if (Subtarget.inMips16Mode())
return std::make_pair(0U, &Mips::CPU16RegsRegClass); return std::make_pair(0U, &Mips::CPU16RegsRegClass);
return std::make_pair(0U, &Mips::GPR32RegClass); return std::make_pair(0U, &Mips::GPR32RegClass);
} }
if (VT == MVT::i64 && !Subtarget->isGP64bit()) if (VT == MVT::i64 && !Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR32RegClass); return std::make_pair(0U, &Mips::GPR32RegClass);
if (VT == MVT::i64 && Subtarget->isGP64bit()) if (VT == MVT::i64 && Subtarget.isGP64bit())
return std::make_pair(0U, &Mips::GPR64RegClass); return std::make_pair(0U, &Mips::GPR64RegClass);
// This will generate an error message // This will generate an error message
return std::make_pair(0U, nullptr); return std::make_pair(0U, nullptr);
@ -3088,8 +3088,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
return std::make_pair(0U, &Mips::MSA128DRegClass); return std::make_pair(0U, &Mips::MSA128DRegClass);
else if (VT == MVT::f32) else if (VT == MVT::f32)
return std::make_pair(0U, &Mips::FGR32RegClass); return std::make_pair(0U, &Mips::FGR32RegClass);
else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
if (Subtarget->isFP64bit()) if (Subtarget.isFP64bit())
return std::make_pair(0U, &Mips::FGR64RegClass); return std::make_pair(0U, &Mips::FGR64RegClass);
return std::make_pair(0U, &Mips::AFGR64RegClass); return std::make_pair(0U, &Mips::AFGR64RegClass);
} }
@ -3245,7 +3245,7 @@ EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
bool IsMemset, bool ZeroMemset, bool IsMemset, bool ZeroMemset,
bool MemcpyStrSrc, bool MemcpyStrSrc,
MachineFunction &MF) const { MachineFunction &MF) const {
if (Subtarget->hasMips64()) if (Subtarget.hasMips64())
return MVT::i64; return MVT::i64;
return MVT::i32; return MVT::i32;
@ -3260,7 +3260,7 @@ bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
} }
unsigned MipsTargetLowering::getJumpTableEncoding() const { unsigned MipsTargetLowering::getJumpTableEncoding() const {
if (Subtarget->isABI_N64()) if (Subtarget.isABI_N64())
return MachineJumpTableInfo::EK_GPRel64BlockAddress; return MachineJumpTableInfo::EK_GPRel64BlockAddress;
return TargetLowering::getJumpTableEncoding(); return TargetLowering::getJumpTableEncoding();
@ -3310,7 +3310,7 @@ MipsTargetLowering::MipsCC::SpecialCallingConvType
MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const {
MipsCC::SpecialCallingConvType SpecialCallingConv = MipsCC::SpecialCallingConvType SpecialCallingConv =
MipsCC::NoSpecialCallingConv; MipsCC::NoSpecialCallingConv;
if (Subtarget->inMips16HardFloat()) { if (Subtarget.inMips16HardFloat()) {
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
llvm::StringRef Sym = G->getGlobal()->getName(); llvm::StringRef Sym = G->getGlobal()->getName();
Function *F = G->getGlobal()->getParent()->getFunction(Sym); Function *F = G->getGlobal()->getParent()->getFunction(Sym);
@ -3707,7 +3707,8 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
MachinePointerInfo(), false, false, 0); MachinePointerInfo(), false, false, 0);
cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue((Value*)nullptr); cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
(Value *)nullptr);
OutChains.push_back(Store); OutChains.push_back(Store);
} }
} }

2
llvm/lib/Target/Mips/MipsISelLowering.h
View File

@ -436,7 +436,7 @@ namespace llvm {
SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
// Subtarget Info // Subtarget Info
const MipsSubtarget *Subtarget; const MipsSubtarget &Subtarget;
private: private:
// Create a TargetGlobalAddress node. // Create a TargetGlobalAddress node.

98
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -39,10 +39,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
// Set up the register classes // Set up the register classes
addRegisterClass(MVT::i32, &Mips::GPR32RegClass); addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
if (Subtarget->isGP64bit()) if (Subtarget.isGP64bit())
addRegisterClass(MVT::i64, &Mips::GPR64RegClass); addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
if (Subtarget->hasDSP() || Subtarget->hasMSA()) { if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
// Expand all truncating stores and extending loads. // Expand all truncating stores and extending loads.
unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
@ -58,7 +58,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
} }
} }
if (Subtarget->hasDSP()) { if (Subtarget.hasDSP()) {
MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
@ -82,10 +82,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setTargetDAGCombine(ISD::VSELECT); setTargetDAGCombine(ISD::VSELECT);
} }
if (Subtarget->hasDSPR2()) if (Subtarget.hasDSPR2())
setOperationAction(ISD::MUL, MVT::v2i16, Legal); setOperationAction(ISD::MUL, MVT::v2i16, Legal);
if (Subtarget->hasMSA()) { if (Subtarget.hasMSA()) {
addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
@ -101,12 +101,12 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setTargetDAGCombine(ISD::XOR); setTargetDAGCombine(ISD::XOR);
} }
if (!Subtarget->abiUsesSoftFloat()) { if (!Subtarget.abiUsesSoftFloat()) {
addRegisterClass(MVT::f32, &Mips::FGR32RegClass); addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
// When dealing with single precision only, use libcalls // When dealing with single precision only, use libcalls
if (!Subtarget->isSingleFloat()) { if (!Subtarget.isSingleFloat()) {
if (Subtarget->isFP64bit()) if (Subtarget.isFP64bit())
addRegisterClass(MVT::f64, &Mips::FGR64RegClass); addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
else else
addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
@ -118,12 +118,12 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::MULHS, MVT::i32, Custom); setOperationAction(ISD::MULHS, MVT::i32, Custom);
setOperationAction(ISD::MULHU, MVT::i32, Custom); setOperationAction(ISD::MULHU, MVT::i32, Custom);
if (Subtarget->hasCnMips()) if (Subtarget.hasCnMips())
setOperationAction(ISD::MUL, MVT::i64, Legal); setOperationAction(ISD::MUL, MVT::i64, Legal);
else if (Subtarget->isGP64bit()) else if (Subtarget.isGP64bit())
setOperationAction(ISD::MUL, MVT::i64, Custom); setOperationAction(ISD::MUL, MVT::i64, Custom);
if (Subtarget->isGP64bit()) { if (Subtarget.isGP64bit()) {
setOperationAction(ISD::MULHS, MVT::i64, Custom); setOperationAction(ISD::MULHS, MVT::i64, Custom);
setOperationAction(ISD::MULHU, MVT::i64, Custom); setOperationAction(ISD::MULHU, MVT::i64, Custom);
} }
@ -152,7 +152,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::STORE, MVT::f64, Custom); setOperationAction(ISD::STORE, MVT::f64, Custom);
} }
if (Subtarget->hasMips32r6()) { if (Subtarget.hasMips32r6()) {
// MIPS32r6 replaces the accumulator-based multiplies with a three register // MIPS32r6 replaces the accumulator-based multiplies with a three register
// instruction // instruction
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
@ -180,7 +180,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::SELECT, MVT::f32, Legal); setOperationAction(ISD::SELECT, MVT::f32, Legal);
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
assert(Subtarget->isFP64bit() && "FR=1 is required for MIPS32r6"); assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
setOperationAction(ISD::SETCC, MVT::f64, Legal); setOperationAction(ISD::SETCC, MVT::f64, Legal);
setOperationAction(ISD::SELECT, MVT::f64, Legal); setOperationAction(ISD::SELECT, MVT::f64, Legal);
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
@ -199,7 +199,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
} }
if (Subtarget->hasMips64r6()) { if (Subtarget.hasMips64r6()) {
// MIPS64r6 replaces the accumulator-based multiplies with a three register // MIPS64r6 replaces the accumulator-based multiplies with a three register
// instruction // instruction
setOperationAction(ISD::MUL, MVT::i64, Legal); setOperationAction(ISD::MUL, MVT::i64, Legal);
@ -233,7 +233,7 @@ llvm::createMipsSETargetLowering(MipsTargetMachine &TM) {
const TargetRegisterClass * const TargetRegisterClass *
MipsSETargetLowering::getRepRegClassFor(MVT VT) const { MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
if (VT == MVT::Untyped) if (VT == MVT::Untyped)
return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
return TargetLowering::getRepRegClassFor(VT); return TargetLowering::getRepRegClassFor(VT);
} }
@ -332,7 +332,7 @@ MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
bool *Fast) const { bool *Fast) const {
MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
if (Subtarget->systemSupportsUnalignedAccess()) { if (Subtarget.systemSupportsUnalignedAccess()) {
// MIPS32r6/MIPS64r6 is required to support unaligned access. It's // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
// implementation defined whether this is handled by hardware, software, or // implementation defined whether this is handled by hardware, software, or
// a hybrid of the two but it's expected that most implementations will // a hybrid of the two but it's expected that most implementations will
@ -523,11 +523,11 @@ static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
if (DCI.isBeforeLegalize()) if (DCI.isBeforeLegalize())
return SDValue(); return SDValue();
if (Subtarget->hasMips32() && !Subtarget->hasMips32r6() && if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG)) N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
return SDValue(N, 0); return SDValue(N, 0);
@ -543,8 +543,8 @@ static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
// - Removes redundant zero extensions performed by an ISD::AND. // - Removes redundant zero extensions performed by an ISD::AND.
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
if (!Subtarget->hasMSA()) if (!Subtarget.hasMSA())
return SDValue(); return SDValue();
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
@ -659,8 +659,8 @@ static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
// vector type. // vector type.
static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
if (!Subtarget->hasMSA()) if (!Subtarget.hasMSA())
return SDValue(); return SDValue();
EVT Ty = N->getValueType(0); EVT Ty = N->getValueType(0);
@ -676,7 +676,7 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
SDValue Op0Op1 = Op0->getOperand(1); SDValue Op0Op1 = Op0->getOperand(1);
SDValue Op1Op0 = Op1->getOperand(0); SDValue Op1Op0 = Op1->getOperand(0);
SDValue Op1Op1 = Op1->getOperand(1); SDValue Op1Op1 = Op1->getOperand(1);
bool IsLittleEndian = !Subtarget->isLittle(); bool IsLittleEndian = !Subtarget.isLittle();
SDValue IfSet, IfClr, Cond; SDValue IfSet, IfClr, Cond;
bool IsConstantMask = false; bool IsConstantMask = false;
@ -779,11 +779,11 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
if (DCI.isBeforeLegalize()) if (DCI.isBeforeLegalize())
return SDValue(); return SDValue();
if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
selectMSUB(N, &DAG)) selectMSUB(N, &DAG))
return SDValue(N, 0); return SDValue(N, 0);
@ -843,7 +843,7 @@ static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
SelectionDAG &DAG, SelectionDAG &DAG,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
// See if this is a vector splat immediate node. // See if this is a vector splat immediate node.
APInt SplatValue, SplatUndef; APInt SplatValue, SplatUndef;
unsigned SplatBitSize; unsigned SplatBitSize;
@ -851,12 +851,12 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
if (!Subtarget->hasDSP()) if (!Subtarget.hasDSP())
return SDValue(); return SDValue();
if (!BV || if (!BV ||
!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
EltSize, !Subtarget->isLittle()) || EltSize, !Subtarget.isLittle()) ||
(SplatBitSize != EltSize) || (SplatBitSize != EltSize) ||
(SplatValue.getZExtValue() >= EltSize)) (SplatValue.getZExtValue() >= EltSize))
return SDValue(); return SDValue();
@ -867,7 +867,7 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
EVT Ty = N->getValueType(0); EVT Ty = N->getValueType(0);
if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
@ -890,10 +890,10 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
// used for DSPr2. // used for DSPr2.
static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
EVT Ty = N->getValueType(0); EVT Ty = N->getValueType(0);
if (Subtarget->hasMSA()) { if (Subtarget.hasMSA()) {
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1); SDValue Op1 = N->getOperand(1);
@ -928,7 +928,7 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
} }
} }
if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
return SDValue(); return SDValue();
return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
@ -937,10 +937,10 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI, TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
EVT Ty = N->getValueType(0); EVT Ty = N->getValueType(0);
if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
return SDValue(); return SDValue();
return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
@ -1034,10 +1034,10 @@ static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
} }
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
const MipsSubtarget *Subtarget) { const MipsSubtarget &Subtarget) {
EVT Ty = N->getValueType(0); EVT Ty = N->getValueType(0);
if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
// Try the following combines: // Try the following combines:
// (xor (or $a, $b), (build_vector allones)) // (xor (or $a, $b), (build_vector allones))
// (xor (or $a, $b), (bitcast (build_vector allones))) // (xor (or $a, $b), (bitcast (build_vector allones)))
@ -1215,7 +1215,7 @@ SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
Nd.isNonTemporal(), Nd.isInvariant(), Nd.isNonTemporal(), Nd.isInvariant(),
std::min(Nd.getAlignment(), 4U)); std::min(Nd.getAlignment(), 4U));
if (!Subtarget->isLittle()) if (!Subtarget.isLittle())
std::swap(Lo, Hi); std::swap(Lo, Hi);
SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
@ -1238,7 +1238,7 @@ SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Val, DAG.getConstant(1, MVT::i32)); Val, DAG.getConstant(1, MVT::i32));
if (!Subtarget->isLittle()) if (!Subtarget.isLittle())
std::swap(Lo, Hi); std::swap(Lo, Hi);
// i32 store to lower address. // i32 store to lower address.
@ -1257,7 +1257,7 @@ SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
bool HasLo, bool HasHi, bool HasLo, bool HasHi,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
// MIPS32r6/MIPS64r6 removed accumulator based multiplies. // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
assert(!Subtarget->hasMips32r6()); assert(!Subtarget.hasMips32r6());
EVT Ty = Op.getOperand(0).getValueType(); EVT Ty = Op.getOperand(0).getValueType();
SDLoc DL(Op); SDLoc DL(Op);
@ -1621,7 +1621,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_bnegi_w: case Intrinsic::mips_bnegi_w:
case Intrinsic::mips_bnegi_d: case Intrinsic::mips_bnegi_d:
return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
!Subtarget->isLittle()); !Subtarget.isLittle());
case Intrinsic::mips_bnz_b: case Intrinsic::mips_bnz_b:
case Intrinsic::mips_bnz_h: case Intrinsic::mips_bnz_h:
case Intrinsic::mips_bnz_w: case Intrinsic::mips_bnz_w:
@ -1657,7 +1657,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_bseti_w: case Intrinsic::mips_bseti_w:
case Intrinsic::mips_bseti_d: case Intrinsic::mips_bseti_d:
return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
!Subtarget->isLittle()); !Subtarget.isLittle());
case Intrinsic::mips_bz_b: case Intrinsic::mips_bz_b:
case Intrinsic::mips_bz_h: case Intrinsic::mips_bz_h:
case Intrinsic::mips_bz_w: case Intrinsic::mips_bz_w:
@ -1732,7 +1732,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_copy_s_w: case Intrinsic::mips_copy_s_w:
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
case Intrinsic::mips_copy_s_d: case Intrinsic::mips_copy_s_d:
if (Subtarget->hasMips64()) if (Subtarget.hasMips64())
// Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64. // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
else { else {
@ -1747,7 +1747,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
case Intrinsic::mips_copy_u_w: case Intrinsic::mips_copy_u_w:
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
case Intrinsic::mips_copy_u_d: case Intrinsic::mips_copy_u_d:
if (Subtarget->hasMips64()) if (Subtarget.hasMips64())
// Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64. // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
else { else {
@ -2324,12 +2324,12 @@ SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
unsigned SplatBitSize; unsigned SplatBitSize;
bool HasAnyUndefs; bool HasAnyUndefs;
if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
return SDValue(); return SDValue();
if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
HasAnyUndefs, 8, HasAnyUndefs, 8,
!Subtarget->isLittle()) && SplatBitSize <= 64) { !Subtarget.isLittle()) && SplatBitSize <= 64) {
// We can only cope with 8, 16, 32, or 64-bit elements // We can only cope with 8, 16, 32, or 64-bit elements
if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
SplatBitSize != 64) SplatBitSize != 64)
@ -2902,7 +2902,7 @@ emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
// valid because FR=1 mode which is the only supported mode in MSA. // valid because FR=1 mode which is the only supported mode in MSA.
MachineBasicBlock * MipsSETargetLowering:: MachineBasicBlock * MipsSETargetLowering::
emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
assert(Subtarget->isFP64bit()); assert(Subtarget.isFP64bit());
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
@ -2965,7 +2965,7 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
MachineBasicBlock * MachineBasicBlock *
MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
assert(Subtarget->isFP64bit()); assert(Subtarget.isFP64bit());
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
@ -3025,7 +3025,7 @@ MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
const TargetRegisterClass *VecRC = nullptr; const TargetRegisterClass *VecRC = nullptr;
const TargetRegisterClass *GPRRC = const TargetRegisterClass *GPRRC =
Subtarget->isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; Subtarget.isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
unsigned EltLog2Size; unsigned EltLog2Size;
unsigned InsertOp = 0; unsigned InsertOp = 0;
unsigned InsveOp = 0; unsigned InsveOp = 0;
@ -3154,7 +3154,7 @@ MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
MachineBasicBlock * MachineBasicBlock *
MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
assert(Subtarget->isFP64bit()); assert(Subtarget.isFP64bit());
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();