forked from OSchip/llvm-project
Rename load/store instructions to include an RI suffix
llvm-svn: 24784
This commit is contained in:
Chris Lattner
parent
4fa86e1d55
commit
1c02c45f18
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@ -372,7 +372,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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assert (IAR != IAREnd
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&& "About to dereference past end of IncomingArgRegs");
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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ArgOffset += 4;
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}
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// Reset the pointers now that we're done.
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@ -392,7 +392,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
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}
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ArgOffset += 4;
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} else if (getClassB (A.getType ()) == cFloat) {
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@ -403,7 +403,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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assert (IAR != IAREnd
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&& "About to dereference past end of IncomingArgRegs");
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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@ -418,19 +418,19 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
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if (ArgOffset < 92 && IAR != IAREnd) {
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
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}
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ArgOffset += 4;
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if (ArgOffset < 92 && IAR != IAREnd) {
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
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}
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ArgOffset += 4;
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BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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@ -442,7 +442,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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}
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ArgOffset += 4;
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// ...then do the second half
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@ -452,7 +452,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
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}
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ArgOffset += 4;
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} else {
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@ -644,7 +644,7 @@ void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
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BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
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.addReg (TempReg);
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unsigned TempReg2 = makeAnotherReg (newTy);
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BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::LDri, 3, TempReg2).addFrameIndex (FI).addSImm (0);
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emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
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}
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@ -698,7 +698,7 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
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// it using ldf into a floating point register. then do fitos.
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unsigned TmpReg = makeAnotherReg (newTy);
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (SrcReg);
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BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
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@ -720,7 +720,7 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
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unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
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unsigned TmpReg = makeAnotherReg (newTy);
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int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
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BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (SrcReg);
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BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
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@ -774,22 +774,22 @@ void V8ISel::visitLoadInst(LoadInst &I) {
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switch (getClassB (I.getType ())) {
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case cByte:
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if (I.getType ()->isSigned ())
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BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDSBri, 2, DestReg).addReg (PtrReg).addSImm(0);
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else
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BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDUBri, 2, DestReg).addReg (PtrReg).addSImm(0);
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return;
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case cShort:
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if (I.getType ()->isSigned ())
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BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDSHri, 2, DestReg).addReg (PtrReg).addSImm(0);
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else
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BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDUHri, 2, DestReg).addReg (PtrReg).addSImm(0);
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return;
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case cInt:
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BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
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return;
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case cLong:
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BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
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BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (PtrReg).addSImm(4);
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return;
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case cFloat:
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BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
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@ -810,17 +810,17 @@ void V8ISel::visitStoreInst(StoreInst &I) {
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unsigned PtrReg = getReg (I.getOperand (1));
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switch (getClassB (SrcVal->getType ())) {
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case cByte:
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BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STBri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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case cShort:
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BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STHri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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case cInt:
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BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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case cLong:
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BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
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BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
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return;
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case cFloat:
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BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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@ -879,7 +879,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
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} else {
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (ArgReg);
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}
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ArgOffset += 4;
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@ -892,7 +892,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
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assert (OAR != OAREnd &&
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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} else {
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BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (ArgReg);
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@ -909,22 +909,22 @@ void V8ISel::visitCallInst(CallInst &I) {
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if (ArgOffset < 92 && OAR != OAREnd) {
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assert (OAR != OAREnd &&
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (TempReg);
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}
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ArgOffset += 4;
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if (ArgOffset < 92 && OAR != OAREnd) {
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assert (OAR != OAREnd &&
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (4);
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (TempReg);
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}
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ArgOffset += 4;
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@ -935,7 +935,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
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} else {
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (ArgReg);
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}
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ArgOffset += 4;
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@ -945,7 +945,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
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} else {
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (ArgReg+1);
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}
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ArgOffset += 4;
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@ -1756,7 +1756,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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unsigned DestReg = getReg (CI.getOperand(1));
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unsigned Tmp = makeAnotherReg(Type::IntTy);
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BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
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BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
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BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
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return;
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}
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@ -1767,7 +1767,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
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case Intrinsic::vacopy: {
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// Copy the va_list ptr (arg1) to the result.
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unsigned DestReg = getReg (CI.getOperand(1)), SrcReg = getReg (CI.getOperand (2));
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BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
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BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
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return;
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}
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}
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@ -1778,21 +1778,21 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
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unsigned DestReg = getReg (I);
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unsigned Size;
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unsigned VAList = makeAnotherReg(Type::IntTy);
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BuildMI(BB, V8::LD, 2, VAList).addReg(VAListPtr).addSImm(0);
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BuildMI(BB, V8::LDri, 2, VAList).addReg(VAListPtr).addSImm(0);
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switch (I.getType ()->getTypeID ()) {
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case Type::PointerTyID:
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case Type::UIntTyID:
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case Type::IntTyID:
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Size = 4;
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BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
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BuildMI (BB, V8::LDri, 2, DestReg).addReg (VAList).addSImm (0);
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break;
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case Type::ULongTyID:
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case Type::LongTyID:
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Size = 8;
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BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
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BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
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BuildMI (BB, V8::LDri, 2, DestReg).addReg (VAList).addSImm (0);
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BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (VAList).addSImm (4);
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break;
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case Type::DoubleTyID: {
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@ -1801,10 +1801,10 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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unsigned TempReg2 = makeAnotherReg (Type::IntTy);
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int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
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BuildMI (BB, V8::LD, 2, TempReg).addReg (VAList).addSImm (0);
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BuildMI (BB, V8::LD, 2, TempReg2).addReg (VAList).addSImm (4);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
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BuildMI (BB, V8::LDri, 2, TempReg).addReg (VAList).addSImm (0);
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BuildMI (BB, V8::LDri, 2, TempReg2).addReg (VAList).addSImm (4);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
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BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
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break;
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}
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@ -1817,6 +1817,6 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
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}
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unsigned tmp = makeAnotherReg(Type::IntTy);
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BuildMI (BB, V8::ADDri, 2, tmp).addReg(VAList).addSImm(Size);
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BuildMI(BB, V8::ST, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
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BuildMI(BB, V8::STri, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
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return;
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}
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@ -41,12 +41,10 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
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void SparcV8RegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *rc) const {
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const TargetRegisterClass *RC = getClass(SrcReg);
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const TargetRegisterClass *RC) const {
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == V8::IntRegsRegisterClass)
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BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
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BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
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.addReg (SrcReg);
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else if (RC == V8::FPRegsRegisterClass)
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BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
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|
@ -61,10 +59,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||
void SparcV8RegisterInfo::
|
||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
unsigned DestReg, int FrameIdx,
|
||||
const TargetRegisterClass *rc) const {
|
||||
const TargetRegisterClass *RC = getClass(DestReg);
|
||||
const TargetRegisterClass *RC) const {
|
||||
if (RC == V8::IntRegsRegisterClass)
|
||||
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
|
||||
BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
|
||||
else if (RC == V8::FPRegsRegisterClass)
|
||||
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
|
||||
.addSImm (0);
|
||||
|
|
|
|||
Loading…
Reference in New Issue