forked from OSchip/llvm-project
[LoopVectorize] propagate fast-math-flags from induction instructions
This code assumed that FP math was only permissable if it was fully "fast", so it hard-coded "fast" when creating new instructions. The underlying code already allows matching recurrences/reductions that are only "reassoc", so this change should prevent the potential miscompile seen in the test diffs (we created "fast" ops even though none existed in the original code). I don't know if we need to create the temporary IRBuilder objects used here, so that could be follow-up clean-up. There's an open question about whether we should require "nsz" in addition to "reassoc" here. InstCombine uses that combo for its reassociative folds, but I think codegen is not as strict.
This commit is contained in:
Sanjay Patel
parent
51bd42ef9b
commit
1bee549737
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@ -395,13 +395,6 @@ static bool hasIrregularType(Type *Ty, const DataLayout &DL, ElementCount VF) {
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/// we always assume predicated blocks have a 50% chance of executing.
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static unsigned getReciprocalPredBlockProb() { return 2; }
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/// A helper function that adds a 'fast' flag to floating-point operations.
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static Value *addFastMathFlag(Value *V) {
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if (isa<FPMathOperator>(V))
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cast<Instruction>(V)->setFastMathFlags(FastMathFlags::getFast());
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return V;
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}
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/// A helper function that returns an integer or floating-point constant with
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/// value C.
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static Constant *getSignedIntOrFpConstant(Type *Ty, int64_t C) {
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@ -2247,7 +2240,7 @@ void InnerLoopVectorizer::createVectorIntOrFpInductionPHI(
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// floating-point arithmetic as appropriate.
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Value *ConstVF =
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getSignedIntOrFpConstant(Step->getType(), VF.getKnownMinValue());
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Value *Mul = addFastMathFlag(Builder.CreateBinOp(MulOp, Step, ConstVF));
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Value *Mul = Builder.CreateBinOp(MulOp, Step, ConstVF);
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// Create a vector splat to use in the induction update.
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//
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@ -2274,8 +2267,8 @@ void InnerLoopVectorizer::createVectorIntOrFpInductionPHI(
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recordVectorLoopValueForInductionCast(II, EntryVal, LastInduction, CastDef,
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State, Part);
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LastInduction = cast<Instruction>(addFastMathFlag(
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Builder.CreateBinOp(AddOp, LastInduction, SplatVF, "step.add")));
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LastInduction = cast<Instruction>(
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Builder.CreateBinOp(AddOp, LastInduction, SplatVF, "step.add"));
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LastInduction->setDebugLoc(EntryVal->getDebugLoc());
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}
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@ -2407,6 +2400,11 @@ void InnerLoopVectorizer::widenIntOrFpInduction(PHINode *IV, Value *Start,
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}
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};
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// Fast-math-flags propagate from the original induction instruction.
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IRBuilder<>::FastMathFlagGuard FMFG(Builder);
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if (ID.getInductionBinOp() && isa<FPMathOperator>(ID.getInductionBinOp()))
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Builder.setFastMathFlags(ID.getInductionBinOp()->getFastMathFlags());
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// Now do the actual transformations, and start with creating the step value.
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Value *Step = CreateStepValue(ID.getStep());
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if (VF.isZero() || VF.isScalar()) {
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@ -2486,23 +2484,11 @@ Value *InnerLoopVectorizer::getStepVector(Value *Val, int StartIdx, Value *Step,
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Indices.push_back(ConstantFP::get(STy, (double)(StartIdx + i)));
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// Add the consecutive indices to the vector value.
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// Floating-point operations inherit FMF via the builder's flags.
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Constant *Cv = ConstantVector::get(Indices);
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Step = Builder.CreateVectorSplat(VLen, Step);
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// Floating point operations had to be 'fast' to enable the induction.
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FastMathFlags Flags;
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Flags.setFast();
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Value *MulOp = Builder.CreateFMul(Cv, Step);
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if (isa<Instruction>(MulOp))
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// Have to check, MulOp may be a constant
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cast<Instruction>(MulOp)->setFastMathFlags(Flags);
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Value *BOp = Builder.CreateBinOp(BinOp, Val, MulOp, "induction");
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if (isa<Instruction>(BOp))
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cast<Instruction>(BOp)->setFastMathFlags(Flags);
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return BOp;
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return Builder.CreateBinOp(BinOp, Val, MulOp, "induction");
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}
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void InnerLoopVectorizer::buildScalarSteps(Value *ScalarIV, Value *Step,
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@ -2547,15 +2533,15 @@ void InnerLoopVectorizer::buildScalarSteps(Value *ScalarIV, Value *Step,
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createStepForVF(Builder, ConstantInt::get(IntStepTy, Part), VF);
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if (ScalarIVTy->isFloatingPointTy())
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StartIdx = Builder.CreateSIToFP(StartIdx, ScalarIVTy);
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StartIdx = addFastMathFlag(Builder.CreateBinOp(
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AddOp, StartIdx, getSignedIntOrFpConstant(ScalarIVTy, Lane)));
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StartIdx = Builder.CreateBinOp(
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AddOp, StartIdx, getSignedIntOrFpConstant(ScalarIVTy, Lane));
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// The step returned by `createStepForVF` is a runtime-evaluated value
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// when VF is scalable. Otherwise, it should be folded into a Constant.
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assert((VF.isScalable() || isa<Constant>(StartIdx)) &&
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"Expected StartIdx to be folded to a constant when VF is not "
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"scalable");
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auto *Mul = addFastMathFlag(Builder.CreateBinOp(MulOp, StartIdx, Step));
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auto *Add = addFastMathFlag(Builder.CreateBinOp(AddOp, ScalarIV, Mul));
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auto *Mul = Builder.CreateBinOp(MulOp, StartIdx, Step);
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auto *Add = Builder.CreateBinOp(AddOp, ScalarIV, Mul);
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State.set(Def, Add, VPIteration(Part, Lane));
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recordVectorLoopValueForInductionCast(ID, EntryVal, Add, CastDef, State,
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Part, Lane);
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@ -3325,6 +3311,7 @@ Value *InnerLoopVectorizer::emitTransformedIndex(
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return LoopVectorBody->getTerminator();
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return &*B.GetInsertPoint();
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};
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switch (ID.getKind()) {
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case InductionDescriptor::IK_IntInduction: {
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assert(Index->getType() == StartValue->getType() &&
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@ -3352,22 +3339,9 @@ Value *InnerLoopVectorizer::emitTransformedIndex(
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"Original bin op should be defined for FP induction");
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Value *StepValue = cast<SCEVUnknown>(Step)->getValue();
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// Floating point operations had to be 'fast' to enable the induction.
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FastMathFlags Flags;
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Flags.setFast();
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Value *MulExp = B.CreateFMul(StepValue, Index);
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if (isa<Instruction>(MulExp))
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// We have to check, the MulExp may be a constant.
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cast<Instruction>(MulExp)->setFastMathFlags(Flags);
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Value *BOp = B.CreateBinOp(InductionBinOp->getOpcode(), StartValue, MulExp,
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"induction");
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if (isa<Instruction>(BOp))
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cast<Instruction>(BOp)->setFastMathFlags(Flags);
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return BOp;
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return B.CreateBinOp(InductionBinOp->getOpcode(), StartValue, MulExp,
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"induction");
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}
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case InductionDescriptor::IK_NoInduction:
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return nullptr;
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@ -3454,6 +3428,11 @@ void InnerLoopVectorizer::createInductionResumeValues(
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EndValue = VectorTripCount;
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} else {
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IRBuilder<> B(L->getLoopPreheader()->getTerminator());
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// Fast-math-flags propagate from the original induction instruction.
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if (II.getInductionBinOp() && isa<FPMathOperator>(II.getInductionBinOp()))
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B.setFastMathFlags(II.getInductionBinOp()->getFastMathFlags());
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Type *StepType = II.getStep()->getType();
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Instruction::CastOps CastOp =
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CastInst::getCastOpcode(VectorTripCount, true, StepType, true);
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@ -3675,6 +3654,11 @@ void InnerLoopVectorizer::fixupIVUsers(PHINode *OrigPhi,
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assert(isa<PHINode>(UI) && "Expected LCSSA form");
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IRBuilder<> B(MiddleBlock->getTerminator());
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// Fast-math-flags propagate from the original induction instruction.
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if (II.getInductionBinOp() && isa<FPMathOperator>(II.getInductionBinOp()))
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B.setFastMathFlags(II.getInductionBinOp()->getFastMathFlags());
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Value *CountMinusOne = B.CreateSub(
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CountRoundDown, ConstantInt::get(CountRoundDown->getType(), 1));
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Value *CMO =
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@ -7889,9 +7873,9 @@ Value *InnerLoopUnroller::getStepVector(Value *Val, int StartIdx, Value *Step,
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if (Ty->isFloatingPointTy()) {
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Constant *C = ConstantFP::get(Ty, (double)StartIdx);
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// Floating point operations had to be 'fast' to enable the unrolling.
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Value *MulOp = addFastMathFlag(Builder.CreateFMul(C, Step));
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return addFastMathFlag(Builder.CreateBinOp(BinOp, Val, MulOp));
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// Floating-point operations inherit FMF via the builder's flags.
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Value *MulOp = Builder.CreateFMul(C, Step);
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return Builder.CreateBinOp(BinOp, Val, MulOp);
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}
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Constant *C = ConstantInt::get(Ty, StartIdx);
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return Builder.CreateAdd(Val, Builder.CreateMul(C, Step), "induction");
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@ -105,8 +105,8 @@ for.end: ; preds = %for.end.loopexit, %
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ret void
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}
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; FIXME: We do not need the full 'fast' FMF to vectorize the loop, but the code can't become
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; 'fast' spontaneously. Something is wrong with FMF expectations/propagation.
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; We do not need the full 'fast' FMF to vectorize the loop, but the code can't become
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; 'fast' spontaneously - FMF should propagate from the original IR.
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define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i32 %N) {
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; VEC4_INTERL1-LABEL: @fp_iv_loop1_reassoc_FMF(
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@ -123,15 +123,15 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i
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; VEC4_INTERL1: vector.ph:
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; VEC4_INTERL1-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 8589934588
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; VEC4_INTERL1-NEXT: [[CAST_CRD:%.*]] = sitofp i64 [[N_VEC]] to float
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; VEC4_INTERL1-NEXT: [[TMP3:%.*]] = fmul fast float [[FPINC]], [[CAST_CRD]]
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; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP3]]
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; VEC4_INTERL1-NEXT: [[TMP3:%.*]] = fmul reassoc float [[FPINC]], [[CAST_CRD]]
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; VEC4_INTERL1-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP3]]
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; VEC4_INTERL1-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[INIT]], i32 0
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; VEC4_INTERL1-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
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; VEC4_INTERL1-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x float> poison, float [[FPINC]], i32 0
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; VEC4_INTERL1-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT2]], <4 x float> poison, <4 x i32> zeroinitializer
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; VEC4_INTERL1-NEXT: [[TMP4:%.*]] = fmul fast <4 x float> [[DOTSPLAT3]], <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>
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; VEC4_INTERL1-NEXT: [[INDUCTION:%.*]] = fsub fast <4 x float> [[DOTSPLAT]], [[TMP4]]
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; VEC4_INTERL1-NEXT: [[TMP5:%.*]] = fmul fast float [[FPINC]], 4.000000e+00
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; VEC4_INTERL1-NEXT: [[TMP4:%.*]] = fmul reassoc <4 x float> [[DOTSPLAT3]], <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>
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; VEC4_INTERL1-NEXT: [[INDUCTION:%.*]] = fsub reassoc <4 x float> [[DOTSPLAT]], [[TMP4]]
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; VEC4_INTERL1-NEXT: [[TMP5:%.*]] = fmul reassoc float [[FPINC]], 4.000000e+00
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; VEC4_INTERL1-NEXT: [[DOTSPLATINSERT4:%.*]] = insertelement <4 x float> poison, float [[TMP5]], i32 0
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; VEC4_INTERL1-NEXT: [[DOTSPLAT5:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT4]], <4 x float> poison, <4 x i32> zeroinitializer
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; VEC4_INTERL1-NEXT: br label [[VECTOR_BODY:%.*]]
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@ -142,7 +142,7 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i
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; VEC4_INTERL1-NEXT: [[TMP7:%.*]] = bitcast float* [[TMP6]] to <4 x float>*
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; VEC4_INTERL1-NEXT: store <4 x float> [[VEC_IND]], <4 x float>* [[TMP7]], align 4
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; VEC4_INTERL1-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
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; VEC4_INTERL1-NEXT: [[VEC_IND_NEXT]] = fsub fast <4 x float> [[VEC_IND]], [[DOTSPLAT5]]
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; VEC4_INTERL1-NEXT: [[VEC_IND_NEXT]] = fsub reassoc <4 x float> [[VEC_IND]], [[DOTSPLAT5]]
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; VEC4_INTERL1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VEC4_INTERL1-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]]
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; VEC4_INTERL1: middle.block:
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@ -181,22 +181,22 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i
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; VEC4_INTERL2: vector.ph:
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; VEC4_INTERL2-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 8589934584
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; VEC4_INTERL2-NEXT: [[CAST_CRD:%.*]] = sitofp i64 [[N_VEC]] to float
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; VEC4_INTERL2-NEXT: [[TMP3:%.*]] = fmul fast float [[FPINC]], [[CAST_CRD]]
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; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP3]]
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; VEC4_INTERL2-NEXT: [[TMP3:%.*]] = fmul reassoc float [[FPINC]], [[CAST_CRD]]
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; VEC4_INTERL2-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP3]]
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; VEC4_INTERL2-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[INIT]], i32 0
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; VEC4_INTERL2-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
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; VEC4_INTERL2-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <4 x float> poison, float [[FPINC]], i32 0
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; VEC4_INTERL2-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT2]], <4 x float> poison, <4 x i32> zeroinitializer
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; VEC4_INTERL2-NEXT: [[TMP4:%.*]] = fmul fast <4 x float> [[DOTSPLAT3]], <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>
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; VEC4_INTERL2-NEXT: [[INDUCTION:%.*]] = fsub fast <4 x float> [[DOTSPLAT]], [[TMP4]]
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; VEC4_INTERL2-NEXT: [[TMP5:%.*]] = fmul fast float [[FPINC]], 4.000000e+00
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; VEC4_INTERL2-NEXT: [[TMP4:%.*]] = fmul reassoc <4 x float> [[DOTSPLAT3]], <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>
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; VEC4_INTERL2-NEXT: [[INDUCTION:%.*]] = fsub reassoc <4 x float> [[DOTSPLAT]], [[TMP4]]
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; VEC4_INTERL2-NEXT: [[TMP5:%.*]] = fmul reassoc float [[FPINC]], 4.000000e+00
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; VEC4_INTERL2-NEXT: [[DOTSPLATINSERT4:%.*]] = insertelement <4 x float> poison, float [[TMP5]], i32 0
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; VEC4_INTERL2-NEXT: [[DOTSPLAT5:%.*]] = shufflevector <4 x float> [[DOTSPLATINSERT4]], <4 x float> poison, <4 x i32> zeroinitializer
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; VEC4_INTERL2-NEXT: br label [[VECTOR_BODY:%.*]]
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; VEC4_INTERL2: vector.body:
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; VEC4_INTERL2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; VEC4_INTERL2-NEXT: [[VEC_IND:%.*]] = phi <4 x float> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; VEC4_INTERL2-NEXT: [[STEP_ADD:%.*]] = fsub fast <4 x float> [[VEC_IND]], [[DOTSPLAT5]]
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; VEC4_INTERL2-NEXT: [[STEP_ADD:%.*]] = fsub reassoc <4 x float> [[VEC_IND]], [[DOTSPLAT5]]
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; VEC4_INTERL2-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[INDEX]]
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; VEC4_INTERL2-NEXT: [[TMP7:%.*]] = bitcast float* [[TMP6]] to <4 x float>*
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; VEC4_INTERL2-NEXT: store <4 x float> [[VEC_IND]], <4 x float>* [[TMP7]], align 4
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@ -204,7 +204,7 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i
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; VEC4_INTERL2-NEXT: [[TMP9:%.*]] = bitcast float* [[TMP8]] to <4 x float>*
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; VEC4_INTERL2-NEXT: store <4 x float> [[STEP_ADD]], <4 x float>* [[TMP9]], align 4
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; VEC4_INTERL2-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
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; VEC4_INTERL2-NEXT: [[VEC_IND_NEXT]] = fsub fast <4 x float> [[STEP_ADD]], [[DOTSPLAT5]]
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; VEC4_INTERL2-NEXT: [[VEC_IND_NEXT]] = fsub reassoc <4 x float> [[STEP_ADD]], [[DOTSPLAT5]]
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; VEC4_INTERL2-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VEC4_INTERL2-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]]
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; VEC4_INTERL2: middle.block:
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@ -265,15 +265,15 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i
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; VEC2_INTERL1_PRED_STORE: vector.ph:
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; VEC2_INTERL1_PRED_STORE-NEXT: [[N_VEC:%.*]] = and i64 [[TMP2]], 8589934590
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; VEC2_INTERL1_PRED_STORE-NEXT: [[CAST_CRD:%.*]] = sitofp i64 [[N_VEC]] to float
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP3:%.*]] = fmul fast float [[FPINC]], [[CAST_CRD]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fsub fast float [[INIT:%.*]], [[TMP3]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP3:%.*]] = fmul reassoc float [[FPINC]], [[CAST_CRD]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[IND_END:%.*]] = fsub reassoc float [[INIT:%.*]], [[TMP3]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <2 x float> poison, float [[INIT]], i32 0
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; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTSPLAT:%.*]] = shufflevector <2 x float> [[DOTSPLATINSERT]], <2 x float> poison, <2 x i32> zeroinitializer
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; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <2 x float> poison, float [[FPINC]], i32 0
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; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <2 x float> [[DOTSPLATINSERT2]], <2 x float> poison, <2 x i32> zeroinitializer
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP4:%.*]] = fmul fast <2 x float> [[DOTSPLAT3]], <float 0.000000e+00, float 1.000000e+00>
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; VEC2_INTERL1_PRED_STORE-NEXT: [[INDUCTION:%.*]] = fsub fast <2 x float> [[DOTSPLAT]], [[TMP4]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP5:%.*]] = fmul fast float [[FPINC]], 2.000000e+00
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP4:%.*]] = fmul reassoc <2 x float> [[DOTSPLAT3]], <float 0.000000e+00, float 1.000000e+00>
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; VEC2_INTERL1_PRED_STORE-NEXT: [[INDUCTION:%.*]] = fsub reassoc <2 x float> [[DOTSPLAT]], [[TMP4]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP5:%.*]] = fmul reassoc float [[FPINC]], 2.000000e+00
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; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTSPLATINSERT4:%.*]] = insertelement <2 x float> poison, float [[TMP5]], i32 0
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; VEC2_INTERL1_PRED_STORE-NEXT: [[DOTSPLAT5:%.*]] = shufflevector <2 x float> [[DOTSPLATINSERT4]], <2 x float> poison, <2 x i32> zeroinitializer
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; VEC2_INTERL1_PRED_STORE-NEXT: br label [[VECTOR_BODY:%.*]]
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@ -284,7 +284,7 @@ define void @fp_iv_loop1_reassoc_FMF(float %init, float* noalias nocapture %A, i
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP7:%.*]] = bitcast float* [[TMP6]] to <2 x float>*
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; VEC2_INTERL1_PRED_STORE-NEXT: store <2 x float> [[VEC_IND]], <2 x float>* [[TMP7]], align 4
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; VEC2_INTERL1_PRED_STORE-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2
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; VEC2_INTERL1_PRED_STORE-NEXT: [[VEC_IND_NEXT]] = fsub fast <2 x float> [[VEC_IND]], [[DOTSPLAT5]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[VEC_IND_NEXT]] = fsub reassoc <2 x float> [[VEC_IND]], [[DOTSPLAT5]]
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; VEC2_INTERL1_PRED_STORE-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; VEC2_INTERL1_PRED_STORE-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]]
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; VEC2_INTERL1_PRED_STORE: middle.block:
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Loading…
Reference in New Issue