forked from OSchip/llvm-project
[AArch64][GlobalISel] Define some legalization rules for G_ROTR and G_ROTL.
For imported pattern purposes, we have a custom rule that promotes the rotate amount to 64b as well. Differential Revision: https://reviews.llvm.org/D99463
This commit is contained in:
Amara Emerson
parent
91887cd4ec
commit
1bc90847ee
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@ -703,6 +703,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
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getActionDefinitionsBuilder(G_ROTR)
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.legalFor({{s32, s64}, {s64, s64}})
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.customIf([=](const LegalityQuery &Q) {
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return Q.Types[0].isScalar() && Q.Types[1].getScalarSizeInBits() < 64;
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})
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.lower();
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getActionDefinitionsBuilder(G_ROTL).lower();
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getActionDefinitionsBuilder({G_SBFX, G_UBFX}).customFor({s32, s64});
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computeTables();
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@ -734,11 +742,29 @@ bool AArch64LegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
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case TargetOpcode::G_SBFX:
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case TargetOpcode::G_UBFX:
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return legalizeBitfieldExtract(MI, MRI, Helper);
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case TargetOpcode::G_ROTR:
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return legalizeRotate(MI, MRI, Helper);
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}
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llvm_unreachable("expected switch to return");
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}
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bool AArch64LegalizerInfo::legalizeRotate(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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LegalizerHelper &Helper) const {
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// To allow for imported patterns to match, we ensure that the rotate amount
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// is 64b with an extension.
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Register AmtReg = MI.getOperand(2).getReg();
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LLT AmtTy = MRI.getType(AmtReg);
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assert(AmtTy.isScalar() && "Expected a scalar rotate");
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assert(AmtTy.getSizeInBits() < 64 && "Expected this rotate to be legal");
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auto NewAmt = Helper.MIRBuilder.buildSExt(LLT::scalar(64), AmtReg);
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Helper.Observer.changingInstr(MI);
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MI.getOperand(2).setReg(NewAmt.getReg(0));
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Helper.Observer.changedInstr(MI);
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return true;
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}
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static void extractParts(Register Reg, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder, LLT Ty, int NumParts,
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SmallVectorImpl<Register> &VRegs) {
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@ -17,6 +17,7 @@
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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@ -49,6 +50,8 @@ private:
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bool legalizeVectorTrunc(MachineInstr &MI, LegalizerHelper &Helper) const;
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bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
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LegalizerHelper &Helper) const;
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bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
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LegalizerHelper &Helper) const;
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const AArch64Subtarget *ST;
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};
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} // End llvm namespace.
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@ -0,0 +1,154 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
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---
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name: rotr_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: rotr_s32
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
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; CHECK: %rot:_(s32) = G_ROTR [[COPY]], [[SEXT]](s64)
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; CHECK: $w0 = COPY %rot(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%rot:_(s32) = G_ROTR %0(s32), %1(s32)
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$w0 = COPY %rot(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotr_s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: rotr_s64
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: %rot:_(s64) = G_ROTR [[COPY]], [[COPY1]](s64)
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; CHECK: $x0 = COPY %rot(s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%rot:_(s64) = G_ROTR %0(s64), %1(s64)
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$x0 = COPY %rot(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: rotl_s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: rotl_s32
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]
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; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SUB]](s32)
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; CHECK: %rot:_(s32) = G_ROTR [[COPY]], [[SEXT]](s64)
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; CHECK: $w0 = COPY %rot(s32)
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; CHECK: RET_ReallyLR implicit $w0
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%rot:_(s32) = G_ROTL %0(s32), %1(s32)
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$w0 = COPY %rot(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: rotl_s64
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: rotl_s64
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
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; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY1]]
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; CHECK: %rot:_(s64) = G_ROTR [[COPY]], [[SUB]](s64)
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; CHECK: $x0 = COPY %rot(s64)
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; CHECK: RET_ReallyLR implicit $x0
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%rot:_(s64) = G_ROTL %0(s64), %1(s64)
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$x0 = COPY %rot(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: test_rotl_v4s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: test_rotl_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
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; CHECK: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY1]]
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; CHECK: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR1]]
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; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND]](<4 x s32>)
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; CHECK: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]]
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; CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND1]](<4 x s32>)
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; CHECK: %rot:_(<4 x s32>) = G_OR [[SHL]], [[LSHR]]
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; CHECK: $q0 = COPY %rot(<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%rot:_(<4 x s32>) = G_ROTL %0(<4 x s32>), %1(<4 x s32>)
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$q0 = COPY %rot(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_rotr_v4s32
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: test_rotr_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
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; CHECK: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR]], [[COPY1]]
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; CHECK: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR1]]
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; CHECK: [[LSHR:%[0-9]+]]:_(<4 x s32>) = G_LSHR [[COPY]], [[AND]](<4 x s32>)
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; CHECK: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[SUB]], [[BUILD_VECTOR1]]
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; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY]], [[AND1]](<4 x s32>)
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; CHECK: %rot:_(<4 x s32>) = G_OR [[LSHR]], [[SHL]]
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; CHECK: $q0 = COPY %rot(<4 x s32>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(<4 x s32>) = COPY $q0
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%1:_(<4 x s32>) = COPY $q1
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%rot:_(<4 x s32>) = G_ROTR %0(<4 x s32>), %1(<4 x s32>)
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$q0 = COPY %rot(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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@ -292,11 +292,11 @@
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_ROTR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_ROTL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: G_ICMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
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