From 1ba86188cf4db26c79323ba15c5a4545ac6a602f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 4 Nov 2018 02:10:18 +0000 Subject: [PATCH] [SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG nodes. Move asserts into getNode. These methods were just wrappers around getNode with additional asserts (identical and repeated 3 times). But getNode already has a switch that can be used to hold these asserts that allows them to be shared for all 3 opcodes. This also enables checking on the places that create these nodes without using the wrappers. The rest of the patch is just changing all callers to use getNode directly. llvm-svn: 346087 --- llvm/include/llvm/CodeGen/SelectionDAG.h | 18 -------- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 ++- .../SelectionDAG/LegalizeVectorOps.cpp | 2 +- .../SelectionDAG/LegalizeVectorTypes.cpp | 14 +++--- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 44 +++++-------------- .../Target/Hexagon/HexagonISelLoweringHVX.cpp | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 33 ++++++++------ .../CodeGen/AArch64SelectionDAGTest.cpp | 4 +- 8 files changed, 45 insertions(+), 79 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 973a3ddb1bac..3b144b92e2a6 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -786,24 +786,6 @@ public: /// value assuming it was the smaller SrcTy value. SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT); - /// Return an operation which will any-extend the low lanes of the operand - /// into the specified vector type. For example, - /// this can convert a v16i8 into a v4i32 by any-extending the low four - /// lanes of the operand from i8 to i32. - SDValue getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT); - - /// Return an operation which will sign extend the low lanes of the operand - /// into the specified vector type. For example, - /// this can convert a v16i8 into a v4i32 by sign extending the low four - /// lanes of the operand from i8 to i32. - SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT); - - /// Return an operation which will zero extend the low lanes of the operand - /// into the specified vector type. For example, - /// this can convert a v16i8 into a v4i32 by zero extending the low four - /// lanes of the operand from i8 to i32. - SDValue getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT); - /// Convert Op, which must be of integer type, to the integer type VT, /// by using an extension appropriate for the target's /// BooleanContent for type OpVT or truncating it. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f318b7fdb392..83e9f2c23cab 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9402,7 +9402,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { N0.getOperand(0).getScalarValueSizeInBits() == EVTBits) { if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)) - return DAG.getSignExtendVectorInReg(N0.getOperand(0), SDLoc(N), VT); + return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, + N0.getOperand(0)); } // fold (sext_in_reg (zext x)) -> (sext x) @@ -17049,7 +17050,8 @@ static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN, if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) return DAG.getBitcast(VT, - DAG.getAnyExtendVectorInReg(N0, SDLoc(SVN), OutVT)); + DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, + SDLoc(SVN), OutVT, N0)); } return SDValue(); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 284c4e5b3dd2..bfc00ea28efe 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -872,7 +872,7 @@ SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) { // First build an any-extend node which can be legalized above when we // recurse through it. - Op = DAG.getAnyExtendVectorInReg(Src, DL, VT); + Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src); // Now we need sign extend. Do this by shifting the elements. Even if these // aren't legal operations, they have a better chance of being legalized diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 59bd751f4ec4..6b52b374cd0d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -2811,9 +2811,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which // accepts fewer elements in the result than in the input. if (Opcode == ISD::SIGN_EXTEND) - return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT); + return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); if (Opcode == ISD::ZERO_EXTEND) - return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT); + return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); } } @@ -2883,11 +2883,9 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) { if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) { switch (Opcode) { case ISD::ANY_EXTEND_VECTOR_INREG: - return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT); case ISD::SIGN_EXTEND_VECTOR_INREG: - return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT); case ISD::ZERO_EXTEND_VECTOR_INREG: - return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT); + return DAG.getNode(Opcode, DL, WidenVT, InOp); } } } @@ -3722,11 +3720,11 @@ SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) { default: llvm_unreachable("Extend legalization on extend operation!"); case ISD::ANY_EXTEND: - return DAG.getAnyExtendVectorInReg(InOp, DL, VT); + return DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, InOp); case ISD::SIGN_EXTEND: - return DAG.getSignExtendVectorInReg(InOp, DL, VT); + return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp); case ISD::ZERO_EXTEND: - return DAG.getZeroExtendVectorInReg(InOp, DL, VT); + return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, InOp); } } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 4d509c99c2e6..66121c10a35a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1118,39 +1118,6 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { getConstant(Imm, DL, Op.getValueType())); } -SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL, - EVT VT) { - assert(VT.isVector() && "This DAG node is restricted to vector types."); - assert(VT.getSizeInBits() == Op.getValueSizeInBits() && - "The sizes of the input and result must match in order to perform the " - "extend in-register."); - assert(VT.getVectorNumElements() < Op.getValueType().getVectorNumElements() && - "The destination vector type must have fewer lanes than the input."); - return getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Op); -} - -SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, - EVT VT) { - assert(VT.isVector() && "This DAG node is restricted to vector types."); - assert(VT.getSizeInBits() == Op.getValueSizeInBits() && - "The sizes of the input and result must match in order to perform the " - "extend in-register."); - assert(VT.getVectorNumElements() < Op.getValueType().getVectorNumElements() && - "The destination vector type must have fewer lanes than the input."); - return getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, Op); -} - -SDValue SelectionDAG::getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL, - EVT VT) { - assert(VT.isVector() && "This DAG node is restricted to vector types."); - assert(VT.getSizeInBits() == Op.getValueSizeInBits() && - "The sizes of the input and result must match in order to perform the " - "extend in-register."); - assert(VT.getVectorNumElements() < Op.getValueType().getVectorNumElements() && - "The destination vector type must have fewer lanes than the input."); - return getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, Op); -} - /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { EVT EltVT = VT.getScalarType(); @@ -4196,6 +4163,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT, if (OpOpcode == ISD::UNDEF) return getUNDEF(VT); break; + case ISD::ANY_EXTEND_VECTOR_INREG: + case ISD::ZERO_EXTEND_VECTOR_INREG: + case ISD::SIGN_EXTEND_VECTOR_INREG: + assert(VT.isVector() && "This DAG node is restricted to vector types."); + assert(VT.getSizeInBits() == Operand.getValueSizeInBits() && + "The sizes of the input and result must match in order to perform the " + "extend in-register."); + assert(VT.getVectorNumElements() < + Operand.getValueType().getVectorNumElements() && + "The destination vector type must have fewer lanes than the input."); + break; case ISD::ABS: assert(VT.isInteger() && VT == Operand.getValueType() && "Invalid ABS!"); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index b931f606ee55..a6400b5d8266 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -1426,7 +1426,8 @@ SDValue HexagonTargetLowering::LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const { // Sign- and zero-extends are legal. assert(Op.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG); - return DAG.getZeroExtendVectorInReg(Op.getOperand(0), SDLoc(Op), ty(Op)); + return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(Op), ty(Op), + Op.getOperand(0)); } SDValue diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0a97bf39641f..905b99590a61 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5453,8 +5453,9 @@ static SDValue getExtendInVec(unsigned Opc, const SDLoc &DL, EVT VT, SDValue In, assert((X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && "Unexpected opcode"); if (VT.is128BitVector() && InVT.is128BitVector()) - return X86ISD::VSEXT == Opc ? DAG.getSignExtendVectorInReg(In, DL, VT) - : DAG.getZeroExtendVectorInReg(In, DL, VT); + return DAG.getNode(X86ISD::VSEXT == Opc ? ISD::SIGN_EXTEND_VECTOR_INREG + : ISD::ZERO_EXTEND_VECTOR_INREG, + DL, VT, In); // For 256-bit vectors, we only need the lower (128-bit) input half. // For 512-bit vectors, we only need the lower input half or quarter. @@ -17459,7 +17460,7 @@ static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG, MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), VT.getVectorNumElements() / 2); - SDValue OpLo = DAG.getZeroExtendVectorInReg(In, dl, HalfVT); + SDValue OpLo = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, dl, HalfVT, In); SDValue ZeroVec = DAG.getConstant(0, dl, InVT); SDValue Undef = DAG.getUNDEF(InVT); @@ -19884,7 +19885,7 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget, MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), VT.getVectorNumElements() / 2); - SDValue OpLo = DAG.getSignExtendVectorInReg(In, dl, HalfVT); + SDValue OpLo = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, HalfVT, In); unsigned NumElems = InVT.getVectorNumElements(); SmallVector ShufMask(NumElems, -1); @@ -19892,7 +19893,7 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget &Subtarget, ShufMask[i] = i + NumElems/2; SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, In, ShufMask); - OpHi = DAG.getSignExtendVectorInReg(OpHi, dl, HalfVT); + OpHi = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, HalfVT, OpHi); return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi); } @@ -20138,7 +20139,8 @@ static SDValue LowerLoad(SDValue Op, const X86Subtarget &Subtarget, assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) && "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!"); - SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT); + SDValue Shuff = DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, dl, RegVT, + SlicedVec); return DAG.getMergeValues({Shuff, TF}, dl); } @@ -20823,7 +20825,8 @@ static SDValue getTargetVShiftNode(unsigned Opc, const SDLoc &dl, MVT VT, MVT AmtTy = ShAmt.getSimpleValueType() == MVT::i8 ? MVT::v16i8 : MVT::v8i16; ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), AmtTy, ShAmt); if (Subtarget.hasSSE41()) - ShAmt = DAG.getZeroExtendVectorInReg(ShAmt, SDLoc(ShAmt), MVT::v2i64); + ShAmt = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(ShAmt), + MVT::v2i64, ShAmt); else { SDValue ByteShift = DAG.getConstant( (128 - AmtTy.getScalarSizeInBits()) / 8, SDLoc(ShAmt), MVT::i8); @@ -20836,7 +20839,8 @@ static SDValue getTargetVShiftNode(unsigned Opc, const SDLoc &dl, MVT VT, } else if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { ShAmt = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(ShAmt), MVT::v4i32, ShAmt); - ShAmt = DAG.getZeroExtendVectorInReg(ShAmt, SDLoc(ShAmt), MVT::v2i64); + ShAmt = DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, SDLoc(ShAmt), + MVT::v2i64, ShAmt); } else { SDValue ShOps[4] = {ShAmt, DAG.getConstant(0, dl, SVT), DAG.getUNDEF(SVT), DAG.getUNDEF(SVT)}; @@ -38349,9 +38353,9 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG, (VT.is256BitVector() && Subtarget.hasAVX()) || (VT.is512BitVector() && Subtarget.useAVX512Regs())) { SDValue ExOp = ExtendVecSize(DL, N0, VT.getSizeInBits()); - return Opcode == ISD::SIGN_EXTEND - ? DAG.getSignExtendVectorInReg(ExOp, DL, VT) - : DAG.getZeroExtendVectorInReg(ExOp, DL, VT); + Opcode = Opcode == ISD::SIGN_EXTEND ? ISD::SIGN_EXTEND_VECTOR_INREG + : ISD::ZERO_EXTEND_VECTOR_INREG; + return DAG.getNode(Opcode, DL, VT, ExOp); } auto SplitAndExtendInReg = [&](unsigned SplitSize) { @@ -38360,14 +38364,15 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG, EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts); EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts); + unsigned IROpc = Opcode == ISD::SIGN_EXTEND ? ISD::SIGN_EXTEND_VECTOR_INREG + : ISD::ZERO_EXTEND_VECTOR_INREG; + SmallVector Opnds; for (unsigned i = 0, Offset = 0; i != NumVecs; ++i, Offset += NumSubElts) { SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0, DAG.getIntPtrConstant(Offset, DL)); SrcVec = ExtendVecSize(DL, SrcVec, SplitSize); - SrcVec = Opcode == ISD::SIGN_EXTEND - ? DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT) - : DAG.getZeroExtendVectorInReg(SrcVec, DL, SubVT); + SrcVec = DAG.getNode(IROpc, DL, SubVT, SrcVec); Opnds.push_back(SrcVec); } return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds); diff --git a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp index 620dfc8d234b..dc2d1f9a3576 100644 --- a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp +++ b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp @@ -86,7 +86,7 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) { auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4); auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2); auto InVec = DAG->getConstant(0, Loc, InVecVT); - auto Op = DAG->getZeroExtendVectorInReg(InVec, Loc, OutVecVT); + auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); auto DemandedElts = APInt(4, 15); KnownBits Known; DAG->computeKnownBits(Op, Known, DemandedElts); @@ -118,7 +118,7 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) { auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4); auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2); auto InVec = DAG->getConstant(1, Loc, InVecVT); - auto Op = DAG->getSignExtendVectorInReg(InVec, Loc, OutVecVT); + auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); auto DemandedElts = APInt(4, 15); EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 15u); }