forked from OSchip/llvm-project
Complete conditionalization of Dwarf reg numbers.
Would somebody not on Darwin please make sure this doesn't break anything. Exception handling failures would be the most likely symptom. llvm-svn: 43844
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Dale Johannesen
parent
ef2d838fef
commit
1b9de4dd6f
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@ -657,15 +657,55 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
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// getDwarfRegNum - This function maps LLVM register identifiers to the
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// Dwarf specific numbering, used in debug info and exception tables.
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// The registers are given "basic" dwarf numbers in the .td files,
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// which are collected by TableGen into X86GenRegisterInfo::getDwarfRegNum.
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// This wrapper allows for target-specific overrides.
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// which are for the 64-bit target. These are collected by TableGen
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// into X86GenRegisterInfo::getDwarfRegNum and overridden here for
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// other targets.
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// FIXME: Comments in gcc indicate that Darwin uses different numbering
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// for debug info and exception handling info:( The numbering here is
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// for exception handling.
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int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
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int n = X86GenRegisterInfo::getDwarfRegNum(RegNo);
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const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
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if (Subtarget->isDarwin) {
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// ESP and EBP are switched.
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if (n==4) return 5;
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if (n==5) return 4;
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if (!Subtarget->is64Bit()) {
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// Numbers are all different for 32-bit. Further, some of them
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// differ between Darwin and other targets.
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switch (n) {
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default: assert(0 && "Invalid argument to getDwarfRegNum");
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return n;
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case 0: return 0; // ax
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case 1: return 2; // dx
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case 2: return 1; // cx
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case 3: return 3; // bx
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case 4: return 6; // si
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case 5: return 7; // di
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case 6: return (Subtarget->isDarwin) ? 4 : 5; // bp
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case 7: return (Subtarget->isDarwin) ? 5 : 4; // sp
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case 8: case 9: case 10: case 11: // r8..r15
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case 12: case 13: case 14: case 15:
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assert(0 && "Invalid register in 32-bit mode");
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return n;
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case 16: return 8; // ip
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case 17: case 18: case 19: case 20: // xmm0..xmm7
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case 21: case 22: case 23: case 24:
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return n+4;
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case 25: case 26: case 27: case 28: // xmm8..xmm15
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case 29: case 30: case 31: case 32:
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assert(0 && "Invalid register in 32-bit mode");
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return n;
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case 33: case 34: case 35: case 36: // st0..st7
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case 37: case 38: case 39: case 40:
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return (Subtarget->isDarwin) ? n-21 : n-22;
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case 41: case 42: case 43: case 44: // mm0..mm7
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case 45: case 46: case 47: case 48:
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return n-12;
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}
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}
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return n;
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}
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@ -23,12 +23,17 @@ let Namespace = "X86" in {
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// FIXME: X86-64 have different Dwarf numbers.
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// Dwarf numbering is different for 32-bit and 64-bit, and there are
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// variations by target as well. The numbers here are for 64-bit.
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// They are altered by X86RegisterInfo::getDwarfRegNum at runtime. Note
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// that we can't assign the same number here to different registers, as
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// getDwarfRegNum has only the number here to work with.
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// 8-bit registers
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// Low registers
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def AL : Register<"AL">, DwarfRegNum<0>;
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def CL : Register<"CL">, DwarfRegNum<1>;
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def DL : Register<"DL">, DwarfRegNum<2>;
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def DL : Register<"DL">, DwarfRegNum<1>;
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def CL : Register<"CL">, DwarfRegNum<2>;
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def BL : Register<"BL">, DwarfRegNum<3>;
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// X86-64 only
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@ -47,20 +52,20 @@ let Namespace = "X86" in {
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// High registers X86-32 only
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def AH : Register<"AH">, DwarfRegNum<0>;
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def CH : Register<"CH">, DwarfRegNum<1>;
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def DH : Register<"DH">, DwarfRegNum<2>;
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def DH : Register<"DH">, DwarfRegNum<1>;
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def CH : Register<"CH">, DwarfRegNum<2>;
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def BH : Register<"BH">, DwarfRegNum<3>;
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// 16-bit registers
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def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
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def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<1>;
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def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<2>;
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def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<1>;
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def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<2>;
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def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
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def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<4>;
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def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>;
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def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>;
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def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>;
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def IP : Register<"IP">, DwarfRegNum<8>;
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def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<4>;
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def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<5>;
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def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<6>;
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def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<7>;
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def IP : Register<"IP">, DwarfRegNum<16>;
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// X86-64 only
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def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
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@ -74,14 +79,14 @@ let Namespace = "X86" in {
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// 32-bit registers
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def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
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def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<1>;
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def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<2>;
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def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<1>;
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def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<2>;
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def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
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def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<4>;
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def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>;
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def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>;
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def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>;
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def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<8>;
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def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<4>;
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def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<5>;
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def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<6>;
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def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<7>;
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def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<16>;
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// X86-64 only
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def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
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@ -114,14 +119,14 @@ let Namespace = "X86" in {
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def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>;
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : Register<"MM0">, DwarfRegNum<29>;
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def MM1 : Register<"MM1">, DwarfRegNum<30>;
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def MM2 : Register<"MM2">, DwarfRegNum<31>;
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def MM3 : Register<"MM3">, DwarfRegNum<32>;
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def MM4 : Register<"MM4">, DwarfRegNum<33>;
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def MM5 : Register<"MM5">, DwarfRegNum<34>;
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def MM6 : Register<"MM6">, DwarfRegNum<35>;
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def MM7 : Register<"MM7">, DwarfRegNum<36>;
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def MM0 : Register<"MM0">, DwarfRegNum<41>;
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def MM1 : Register<"MM1">, DwarfRegNum<42>;
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def MM2 : Register<"MM2">, DwarfRegNum<43>;
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def MM3 : Register<"MM3">, DwarfRegNum<44>;
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def MM4 : Register<"MM4">, DwarfRegNum<45>;
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def MM5 : Register<"MM5">, DwarfRegNum<46>;
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def MM6 : Register<"MM6">, DwarfRegNum<47>;
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def MM7 : Register<"MM7">, DwarfRegNum<48>;
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// Pseudo Floating Point registers
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def FP0 : Register<"FP0">, DwarfRegNum<-1>;
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@ -153,14 +158,14 @@ let Namespace = "X86" in {
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def XMM15: Register<"XMM15">, DwarfRegNum<32>;
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// Floating point stack registers
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def ST0 : Register<"ST(0)">, DwarfRegNum<11>;
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def ST1 : Register<"ST(1)">, DwarfRegNum<12>;
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def ST2 : Register<"ST(2)">, DwarfRegNum<13>;
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def ST3 : Register<"ST(3)">, DwarfRegNum<14>;
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def ST4 : Register<"ST(4)">, DwarfRegNum<15>;
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def ST5 : Register<"ST(5)">, DwarfRegNum<16>;
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def ST6 : Register<"ST(6)">, DwarfRegNum<17>;
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def ST7 : Register<"ST(7)">, DwarfRegNum<18>;
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def ST0 : Register<"ST(0)">, DwarfRegNum<33>;
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def ST1 : Register<"ST(1)">, DwarfRegNum<34>;
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def ST2 : Register<"ST(2)">, DwarfRegNum<35>;
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def ST3 : Register<"ST(3)">, DwarfRegNum<36>;
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def ST4 : Register<"ST(4)">, DwarfRegNum<37>;
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def ST5 : Register<"ST(5)">, DwarfRegNum<38>;
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def ST6 : Register<"ST(6)">, DwarfRegNum<39>;
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def ST7 : Register<"ST(7)">, DwarfRegNum<40>;
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// Status flags register
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def EFLAGS : Register<"EFLAGS">;
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