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TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<int>. NFCI. 

Changing mask argument type from const SmallVectorImpl<int>& to
ArrayRef<int>.

This came up in D35700 where a mask is received as an ArrayRef<int> and
we want to pass it to TargetLowering::isShuffleMaskLegal().
Also saves a few lines of code.

llvm-svn: 309085
This commit is contained in:
Zvi Rackover 2017-07-26 08:06:58 +00:00
parent 60bc7e0f0a
commit 1b73682243
12 changed files with 13 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/include/llvm/Target/TargetLowering.h
View File

@ -733,8 +733,7 @@ public:
/// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
/// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
/// legal.
virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
EVT /*VT*/) const {
virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
return true;
}

3
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -6912,8 +6912,7 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
return SDValue();
}
bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
EVT VT) const {
bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
if (VT.getVectorNumElements() == 4 &&
(VT.is128BitVector() || VT.is64BitVector())) {
unsigned PFIndexes[4];

2
llvm/lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -290,7 +290,7 @@ public:
/// Return true if the given shuffle mask can be codegen'd directly, or if it
/// should be stack expanded.
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
/// Return the ISD::SETCC ValueType.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,

3
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -528,8 +528,7 @@ const SISubtarget *SITargetLowering::getSubtarget() const {
// TargetLowering queries
//===----------------------------------------------------------------------===//
bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
EVT) const {
bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
// SI has some legal vector types, but no legal vector operations. Say no
// shuffles are legal in order to prefer scalarizing some vector operations.
return false;

3
llvm/lib/Target/AMDGPU/SIISelLowering.h
View File

@ -140,8 +140,7 @@ public:
const SISubtarget *getSubtarget() const;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
EVT /*VT*/) const override;
bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
unsigned IntrinsicID) const override;

4
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -6520,9 +6520,7 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
bool
ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
EVT VT) const {
bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
if (VT.getVectorNumElements() == 4 &&
(VT.is128BitVector() || VT.is64BitVector())) {
unsigned PFIndexes[4];

2
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -440,7 +440,7 @@ class InstrItineraryData;
Sched::Preference getSchedulingPreference(SDNode *N) const override;
bool
isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
/// isFPImmLegal - Returns true if the target can instruction select the

4
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -2278,8 +2278,8 @@ static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
return StridedLoadKind::NoPattern;
}
bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const {
bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
EVT VT) const {
if (Subtarget.useHVXOps())
return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
return true;

3
llvm/lib/Target/Hexagon/HexagonISelLowering.h
View File

@ -113,8 +113,7 @@ namespace HexagonISD {
bool shouldExpandBuildVectorWithShuffles(EVT VT,
unsigned DefinedValues) const override;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, EVT VT)
const override;
bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
const char *getTargetNodeName(unsigned Opcode) const override;

3
llvm/lib/Target/Mips/MipsSEISelLowering.h
View File

@ -43,8 +43,7 @@ namespace llvm {
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const override;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const override {
bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
return false;
}

4
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -24888,9 +24888,7 @@ bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
/// VECTOR_SHUFFLE operations, those with specific masks.
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
/// are assumed to be legal.
bool
X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
EVT VT) const {
bool X86TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
if (!VT.isSimple())
return false;

3
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -978,8 +978,7 @@ namespace llvm {
/// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
/// target supports the VECTOR_SHUFFLE node, all mask values are assumed to
/// be legal.
bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
EVT VT) const override;
bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
/// Similar to isShuffleMaskLegal. This is used by Targets can use this to
/// indicate if there is a suitable VECTOR_SHUFFLE that can be used to