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Stop traping on sNaN in __builtin_isinf 

__builtin_isinf currently generates a floating-point compare operation
which triggers a trap when faced with a signaling NaN in StrictFP mode.
This commit uses integer operations instead to not generate any trap in
such a case.

Reviewed By: mibintc

Differential Revision: https://reviews.llvm.org/D97125
This commit is contained in:
Thomas Preud'homme 2020-12-09 22:18:32 +00:00
parent e4540812fd
commit 1b6eb56aa0
5 changed files with 133 additions and 27 deletions
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24
clang/lib/CodeGen/CGBuiltin.cpp
View File

@ -3078,8 +3078,11 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
// isfinite(x) --> fabs(x) != infinity // isfinite(x) --> fabs(x) != infinity
// x != NaN via the ordered compare in either case. // x != NaN via the ordered compare in either case.
CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E); CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);
// FIXME: for strictfp/IEEE-754 we need to not trap on SNaN here.
Value *V = EmitScalarExpr(E->getArg(0)); Value *V = EmitScalarExpr(E->getArg(0));
llvm::Type *Ty = V->getType();
if (!Builder.getIsFPConstrained() ||
Builder.getDefaultConstrainedExcept() == fp::ebIgnore ||
!Ty->isIEEE()) {
Value *Fabs = EmitFAbs(*this, V); Value *Fabs = EmitFAbs(*this, V);
Constant *Infinity = ConstantFP::getInfinity(V->getType()); Constant *Infinity = ConstantFP::getInfinity(V->getType());
CmpInst::Predicate Pred = (BuiltinID == Builtin::BI__builtin_isinf) CmpInst::Predicate Pred = (BuiltinID == Builtin::BI__builtin_isinf)
@ -3089,6 +3092,25 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
return RValue::get(Builder.CreateZExt(FCmp, ConvertType(E->getType()))); return RValue::get(Builder.CreateZExt(FCmp, ConvertType(E->getType())));
} }
if (Value *Result = getTargetHooks().testFPKind(V, BuiltinID, Builder, CGM))
return RValue::get(Result);
// Inf values have all exp bits set and a zero significand. Therefore:
// isinf(V) == ((V << 1) == ((exp mask) << 1))
unsigned bitsize = Ty->getScalarSizeInBits();
llvm::IntegerType *IntTy = Builder.getIntNTy(bitsize);
Value *IntV = Builder.CreateBitCast(V, IntTy);
Value *Shl1 = Builder.CreateShl(IntV, 1);
const llvm::fltSemantics &Semantics = Ty->getFltSemantics();
APInt ExpMask = APFloat::getInf(Semantics).bitcastToAPInt();
Value *ExpMaskShl1 = llvm::ConstantInt::get(IntTy, ExpMask.shl(1));
if (BuiltinID == Builtin::BI__builtin_isinf)
V = Builder.CreateICmpEQ(Shl1, ExpMaskShl1);
else
V = Builder.CreateICmpNE(Shl1, ExpMaskShl1);
return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
}
case Builtin::BI__builtin_isinf_sign: { case Builtin::BI__builtin_isinf_sign: {
// isinf_sign(x) -> fabs(x) == infinity ? (signbit(x) ? -1 : 1) : 0 // isinf_sign(x) -> fabs(x) == infinity ? (signbit(x) ? -1 : 1) : 0
CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E); CodeGenFunction::CGFPOptionsRAII FPOptsRAII(*this, E);

20
clang/test/CodeGen/X86/strictfp_builtins.c
View File

@ -26,6 +26,24 @@ void p(char *str, int x) {
#define P(n,args) p(#n #args, __builtin_##n args) #define P(n,args) p(#n #args, __builtin_##n args)
// CHECK-LABEL: @test_long_double_isinf(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca x86_fp80, align 16
// CHECK-NEXT: store x86_fp80 [[D:%.*]], x86_fp80* [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load x86_fp80, x86_fp80* [[LD_ADDR]], align 16
// CHECK-NEXT: [[BITCAST:%.*]] = bitcast x86_fp80 [[TMP0]] to i80
// CHECK-NEXT: [[SHL1:%.*]] = shl i80 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp eq i80 [[SHL1]], -18446744073709551616
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.1, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isinf(long double ld) {
P(isinf, (ld));
return;
}
// CHECK-LABEL: @test_long_double_isnan( // CHECK-LABEL: @test_long_double_isnan(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca x86_fp80, align 16 // CHECK-NEXT: [[LD_ADDR:%.*]] = alloca x86_fp80, align 16
@ -36,7 +54,7 @@ void p(char *str, int x) {
// CHECK-NEXT: [[TMP1:%.*]] = sub i80 604453686435277732577280, [[ABS]] // CHECK-NEXT: [[TMP1:%.*]] = sub i80 604453686435277732577280, [[ABS]]
// CHECK-NEXT: [[ISNAN:%.*]] = lshr i80 [[TMP1]], 79 // CHECK-NEXT: [[ISNAN:%.*]] = lshr i80 [[TMP1]], 79
// CHECK-NEXT: [[RES:%.*]] = trunc i80 [[ISNAN]] to i32 // CHECK-NEXT: [[RES:%.*]] = trunc i80 [[ISNAN]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.1, i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.2, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_long_double_isnan(long double ld) { void test_long_double_isnan(long double ld) {

22
clang/test/CodeGen/aarch64-strictfp-builtins.c
View File

@ -15,7 +15,7 @@ int printf(const char *, ...);
// CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4 // CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4 // CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) // CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) [[ATTR4:#.*]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void p(char *str, int x) { void p(char *str, int x) {
@ -24,6 +24,24 @@ void p(char *str, int x) {
#define P(n,args) p(#n #args, __builtin_##n args) #define P(n,args) p(#n #args, __builtin_##n args)
// CHECK-LABEL: @test_long_double_isinf(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca fp128, align 16
// CHECK-NEXT: store fp128 [[D:%.*]], fp128* [[LD_ADDR]], align 16
// CHECK-NEXT: [[TMP0:%.*]] = load fp128, fp128* [[LD_ADDR]], align 16
// CHECK-NEXT: [[BITCAST:%.*]] = bitcast fp128 [[TMP0]] to i128
// CHECK-NEXT: [[SHL1:%.*]] = shl i128 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[SHL1]], -10384593717069655257060992658440192
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.1, i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isinf(long double ld) {
P(isinf, (ld));
return;
}
// CHECK-LABEL: @test_long_double_isnan( // CHECK-LABEL: @test_long_double_isnan(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca fp128, align 16 // CHECK-NEXT: [[LD_ADDR:%.*]] = alloca fp128, align 16
@ -34,7 +52,7 @@ void p(char *str, int x) {
// CHECK-NEXT: [[TMP1:%.*]] = sub i128 170135991163610696904058773219554885632, [[ABS]] // CHECK-NEXT: [[TMP1:%.*]] = sub i128 170135991163610696904058773219554885632, [[ABS]]
// CHECK-NEXT: [[ISNAN:%.*]] = lshr i128 [[TMP1]], 127 // CHECK-NEXT: [[ISNAN:%.*]] = lshr i128 [[TMP1]], 127
// CHECK-NEXT: [[RES:%.*]] = trunc i128 [[ISNAN]] to i32 // CHECK-NEXT: [[RES:%.*]] = trunc i128 [[ISNAN]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.1, i64 0, i64 0), i32 [[RES]]) // CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.2, i64 0, i64 0), i32 [[RES]])
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_long_double_isnan(long double ld) { void test_long_double_isnan(long double ld) {

15
clang/test/CodeGen/builtin_float_strictfp.c
View File

@ -16,8 +16,19 @@ void test_half(__fp16 *H, __fp16 *H2) {
// CHECK: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict") // CHECK: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float %{{.*}}, metadata !"ogt", metadata !"fpexcept.strict")
// CHECK-NEXT: zext i1 // CHECK-NEXT: zext i1
(void)__builtin_isinf(*H); (void)__builtin_isinf(*H);
// NOFP16: call i1 @llvm.experimental.constrained.fcmp.f32(float %{{.*}}, float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") // NOFP16: [[LDADDR:%.*]] = load i16*, i16** %{{.*}}, align 8
// FP16: call i1 @llvm.experimental.constrained.fcmp.f16(half %{{.*}}, half 0xH7C00, metadata !"oeq", metadata !"fpexcept.strict") // NOFP16-NEXT: [[IHALF:%.*]] = load i16, i16* [[LDADDR]], align 2
// NOFP16-NEXT: [[CONV:%.*]] = call float @llvm.convert.from.fp16.f32(i16 [[IHALF]])
// NOFP16-NEXT: [[IFLOAT:%.*]] = bitcast float [[CONV]] to i32
// NOFP16-NEXT: [[SHL:%.*]] = shl i32 [[IFLOAT]], 1
// NOFP16-NEXT: [[RES1:%.*]] = icmp eq i32 [[SHL]], -16777216
// NOFP16-NEXT: zext i1 [[RES1]] to i32
// FP16: [[LDADDR:%.*]] = load half*, half** %{{.*}}, align 8
// FP16-NEXT: [[HALF:%.*]] = load half, half* [[LDADDR]], align 2
// FP16-NEXT: [[IHALF:%.*]] = bitcast half [[HALF]] to i16
// FP16-NEXT: [[SHL:%.*]] = shl i16 [[IHALF]], 1
// FP16-NEXT: [[RES1:%.*]] = icmp eq i16 [[SHL]], -2048
// FP16-NEXT: zext i1 [[RES1]] to i32
} }
// CHECK-LABEL: @test_mixed // CHECK-LABEL: @test_mixed

65
clang/test/CodeGen/strictfp_builtins.c
View File

@ -1,5 +1,5 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 %s -emit-llvm -ffp-exception-behavior=maytrap -o - -triple x86_64-unknown-unknown | FileCheck %s // RUN: %clang_cc1 %s -emit-llvm -ffp-exception-behavior=maytrap -fallow-half-arguments-and-returns -o - -triple x86_64-unknown-unknown | FileCheck %s
// Test that the constrained intrinsics are picking up the exception // Test that the constrained intrinsics are picking up the exception
// metadata from the AST instead of the global default from the command line. // metadata from the AST instead of the global default from the command line.
@ -55,18 +55,55 @@ void test_fpclassify(double d) {
return; return;
} }
// CHECK-LABEL: @test_isinf( // CHECK-LABEL: @test_fp16_isinf(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[D_ADDR:%.*]] = alloca double, align 8 // CHECK-NEXT: [[LD_ADDR:%.*]] = alloca half, align 2
// CHECK-NEXT: store double [[D:%.*]], double* [[D_ADDR]], align 8 // CHECK-NEXT: store half [[H:%.*]], half* [[LD_ADDR]], align 2
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load half, half* [[LD_ADDR]], align 2
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.fabs.f64(double [[TMP0]]) [[ATTR5]] // CHECK-NEXT: [[BITCAST:%.*]] = bitcast half [[TMP0]] to i16
// CHECK-NEXT: [[CMPINF:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f64(double [[TMP1]], double 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") [[ATTR4]] // CHECK-NEXT: [[SHL1:%.*]] = shl i16 [[BITCAST]], 1
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[CMPINF]] to i32 // CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[SHL1]], -2048
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.2, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]] // CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:2]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_isinf(double d) { void test_fp16_isinf(__fp16 h) {
P(isinf, (h));
return;
}
// CHECK-LABEL: @test_float_isinf(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], float* [[LD_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, float* [[LD_ADDR]], align 4
// CHECK-NEXT: [[BITCAST:%.*]] = bitcast float [[TMP0]] to i32
// CHECK-NEXT: [[SHL1:%.*]] = shl i32 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[SHL1]], -16777216
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_float_isinf(float f) {
P(isinf, (f));
return;
}
// CHECK-LABEL: @test_double_isinf(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[LD_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], double* [[LD_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[LD_ADDR]], align 8
// CHECK-NEXT: [[BITCAST:%.*]] = bitcast double [[TMP0]] to i64
// CHECK-NEXT: [[SHL1:%.*]] = shl i64 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[SHL1]], -9007199254740992
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_double_isinf(double d) {
P(isinf, (d)); P(isinf, (d));
return; return;
@ -83,7 +120,7 @@ void test_isinf(double d) {
// CHECK-NEXT: [[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0 // CHECK-NEXT: [[TMP3:%.*]] = icmp slt i64 [[TMP2]], 0
// CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1 // CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 -1, i32 1
// CHECK-NEXT: [[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0 // CHECK-NEXT: [[TMP5:%.*]] = select i1 [[ISINF]], i32 [[TMP4]], i32 0
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.3, i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]] // CHECK-NEXT: call void @p(i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP5]]) [[ATTR4]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_isinf_sign(double d) { void test_isinf_sign(double d) {
@ -101,7 +138,7 @@ void test_isinf_sign(double d) {
// CHECK-NEXT: [[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFFFFFF]] // CHECK-NEXT: [[ABS:%.*]] = and i32 [[BITCAST]], [[#%u,0x7FFFFFFF]]
// CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[#%u,0x7F800000]], [[ABS]] // CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[#%u,0x7F800000]], [[ABS]]
// CHECK-NEXT: [[ISNAN:%.*]] = lshr i32 [[TMP1]], 31 // CHECK-NEXT: [[ISNAN:%.*]] = lshr i32 [[TMP1]], 31
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.4, i64 0, i64 0), i32 [[ISNAN]]) [[ATTR4]] // CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[ISNAN]]) [[ATTR4]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_float_isnan(float f) { void test_float_isnan(float f) {
@ -120,7 +157,7 @@ void test_float_isnan(float f) {
// CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[#%u,0x7FF0000000000000]], [[ABS]] // CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[#%u,0x7FF0000000000000]], [[ABS]]
// CHECK-NEXT: [[ISNAN:%.*]] = lshr i64 [[TMP1]], 63 // CHECK-NEXT: [[ISNAN:%.*]] = lshr i64 [[TMP1]], 63
// CHECK-NEXT: [[RES:%.*]] = trunc i64 [[ISNAN]] to i32 // CHECK-NEXT: [[RES:%.*]] = trunc i64 [[ISNAN]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.5, i64 0, i64 0), i32 [[RES]]) [[ATTR4]] // CHECK-NEXT: call void @p(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_double_isnan(double d) { void test_double_isnan(double d) {
@ -141,7 +178,7 @@ void test_double_isnan(double d) {
// CHECK-NEXT: [[AND:%.*]] = and i1 [[ISEQ]], [[ISINF]] // CHECK-NEXT: [[AND:%.*]] = and i1 [[ISEQ]], [[ISINF]]
// CHECK-NEXT: [[AND1:%.*]] = and i1 [[AND]], [[ISNORMAL]] // CHECK-NEXT: [[AND1:%.*]] = and i1 [[AND]], [[ISNORMAL]]
// CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[AND1]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[AND1]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.6, i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]] // CHECK-NEXT: call void @p(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[TMP2]]) [[ATTR4]]
// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_isnormal(double d) { void test_isnormal(double d) {