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Revert "ARM: sort register lists by encoding in push/pop instructions." 

This reverts commit 286866. It broke a bot, something to do with exactly which
templates std::sort accepts.

llvm-svn: 286867
This commit is contained in:
Tim Northover 2016-11-14 19:05:28 +00:00
parent e908ea844c
commit 1b66f39cf2
4 changed files with 6 additions and 32 deletions
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15
llvm/lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -893,12 +893,10 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
unsigned MIFlags) const {
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
DebugLoc DL;
typedef std::pair<unsigned, bool> RegAndKill;
SmallVector<RegAndKill, 4> Regs;
SmallVector<std::pair<unsigned,bool>, 4> Regs;
unsigned i = CSI.size();
while (i != 0) {
unsigned LastReg = 0;
@ -929,11 +927,6 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
if (Regs.empty())
continue;
std::sort(Regs.begin(), Regs.end(), [&](RegAndKill &LHS, RegAndKill &RHS) {
return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
});
if (Regs.size() > 1 || StrOpc== 0) {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
@ -967,7 +960,6 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
unsigned NumAlignedDPRCS2Regs) const {
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
DebugLoc DL;
bool isTailCall = false;
@ -1020,11 +1012,6 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
if (Regs.empty())
continue;
std::sort(Regs.begin(), Regs.end(), [&](unsigned &LHS, unsigned &RHS) {
return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
});
if (Regs.size() > 1 || LdrOpc == 0) {
MachineInstrBuilder MIB =
AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)

6
llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -726,12 +726,6 @@ void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
[&](const MCOperand &LHS, const MCOperand &RHS) {
return MRI.getEncodingValue(LHS.getReg()) <
MRI.getEncodingValue(RHS.getReg());
}));
O << "{";
for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
if (i != OpNum)

9
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -1545,15 +1545,8 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op,
else
Binary |= NumRegs * 2;
} else {
const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
assert(std::is_sorted(MI.begin() + Op, MI.end(),
[&](const MCOperand &LHS, const MCOperand &RHS) {
return MRI.getEncodingValue(LHS.getReg()) <
MRI.getEncodingValue(RHS.getReg());
}));
for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
Binary |= 1 << RegNo;
}
}

8
llvm/test/CodeGen/ARM/swifterror.ll
View File

@ -415,7 +415,7 @@ define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
; CHECK-ARMV7-LABEL: _params_in_reg
; Store callee saved registers excluding swifterror.
; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
; Store swiftself (r10) and swifterror (r6).
; CHECK-ARMV7-DAG: str r6, [s[[STK1:.*]]]
; CHECK-ARMV7-DAG: str r10, [s[[STK2:.*]]]
@ -440,7 +440,7 @@ define swiftcc void @swifterror_reg_clobber(%swift_error** nocapture %err) {
; CHECK-ARMV7: mov r2, r5
; CHECK-ARMV7: mov r3, r4
; CHECK-ARMV7: bl _params_in_reg2
; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror %swift_error*, align 8
store %swift_error* null, %swift_error** %error_ptr_ref
@ -451,7 +451,7 @@ define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_err
declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
; CHECK-ARMV7-LABEL: params_and_return_in_reg
; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
; Store swifterror and swiftself
; CHECK-ARMV7: mov r4, r6
; CHECK-ARMV7: str r10, [s[[STK1:.*]]]
@ -502,7 +502,7 @@ declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_e
; CHECK-ARMV7: mov r1, r4
; CHECK-ARMV7: mov r2, r8
; CHECK-ARMV7: mov r3, r11
; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
%error_ptr_ref = alloca swifterror %swift_error*, align 8
store %swift_error* null, %swift_error** %error_ptr_ref