forked from OSchip/llvm-project
[X86] Improved lowering of v4x32 build_vector dag nodes.
This patch improves the lowering of v4f32 and v4i32 build_vector dag nodes that are known to have at least two non-zero elements. With this patch, a build_vector that performs a blend with zero is converted into a shuffle. This is done to let the shuffle legalizer expand the dag node in a optimal way. For example, if we know that a build_vector performs a blend with zero, we can try to lower it as a movq/blend instead of always selecting an insertps. This patch also improves the logic that lowers a build_vector into a insertps with zero masking. See for example the extra test cases added to test sse41.ll. Differential Revision: http://reviews.llvm.org/D6311 llvm-svn: 222375
This commit is contained in:
Andrea Di Biagio
parent
56c0eb2d90
commit
1b657bfcc8
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@ -5740,76 +5740,109 @@ static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
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}
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/// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
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static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
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unsigned NonZeros, unsigned NumNonZero,
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unsigned NumZero, SelectionDAG &DAG,
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static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
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const X86Subtarget *Subtarget,
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const TargetLowering &TLI) {
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// We know there's at least one non-zero element
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unsigned FirstNonZeroIdx = 0;
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SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
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while (FirstNonZero.getOpcode() == ISD::UNDEF ||
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X86::isZeroNode(FirstNonZero)) {
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++FirstNonZeroIdx;
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FirstNonZero = Op->getOperand(FirstNonZeroIdx);
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// Find all zeroable elements.
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bool Zeroable[4];
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for (int i=0; i < 4; ++i) {
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SDValue Elt = Op->getOperand(i);
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Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
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}
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assert(std::count_if(&Zeroable[0], &Zeroable[4],
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[](bool M) { return !M; }) > 1 &&
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"We expect at least two non-zero elements!");
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if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
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!isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
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return SDValue();
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SDValue V = FirstNonZero.getOperand(0);
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MVT VVT = V.getSimpleValueType();
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if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
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return SDValue();
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unsigned FirstNonZeroDst =
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cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
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unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
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unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
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unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
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for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
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SDValue Elem = Op.getOperand(Idx);
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if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
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// We only know how to deal with build_vector nodes where elements are either
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// zeroable or extract_vector_elt with constant index.
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SDValue FirstNonZero;
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for (int i=0; i < 4; ++i) {
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if (Zeroable[i])
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continue;
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// TODO: What else can be here? Deal with it.
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if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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SDValue Elt = Op->getOperand(i);
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if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
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!isa<ConstantSDNode>(Elt.getOperand(1)))
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return SDValue();
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// TODO: Some optimizations are still possible here
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// ex: Getting one element from a vector, and the rest from another.
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if (Elem.getOperand(0) != V)
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return SDValue();
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unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
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if (Dst == Idx)
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++CorrectIdx;
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else if (IncorrectIdx == -1U) {
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IncorrectIdx = Idx;
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IncorrectDst = Dst;
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} else
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// There was already one element with an incorrect index.
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// We can't optimize this case to an insertps.
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// Make sure that this node is extracting from a 128-bit vector.
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MVT VT = Elt.getOperand(0).getSimpleValueType();
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if (!VT.is128BitVector())
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return SDValue();
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if (!FirstNonZero.getNode())
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FirstNonZero = Elt;
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}
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if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
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SDLoc dl(Op);
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EVT VT = Op.getSimpleValueType();
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unsigned ElementMoveMask = 0;
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if (IncorrectIdx == -1U)
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ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
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else
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ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
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assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
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SDValue V1 = FirstNonZero.getOperand(0);
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MVT VT = V1.getSimpleValueType();
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SDValue InsertpsMask =
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DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
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return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
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// See if this build_vector can be lowered as a blend with zero.
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SDValue Elt;
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unsigned EltMaskIdx, EltIdx;
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int Mask[4];
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for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
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if (Zeroable[EltIdx]) {
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// The zero vector will be on the right hand side.
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Mask[EltIdx] = EltIdx+4;
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continue;
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}
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Elt = Op->getOperand(EltIdx);
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// By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
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EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
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if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
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break;
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Mask[EltIdx] = EltIdx;
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}
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return SDValue();
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if (EltIdx == 4) {
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// Let the shuffle legalizer deal with blend operations.
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SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
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if (V1.getSimpleValueType() != VT)
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V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
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return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
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}
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// See if we can lower this build_vector to a INSERTPS.
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if (!Subtarget->hasSSE41())
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return SDValue();
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SDValue V2 = Elt.getOperand(0);
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if (Elt == FirstNonZero)
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V1 = SDValue();
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bool CanFold = true;
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for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
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if (Zeroable[i])
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continue;
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SDValue Current = Op->getOperand(i);
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SDValue SrcVector = Current->getOperand(0);
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if (!V1.getNode())
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V1 = SrcVector;
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CanFold = SrcVector == V1 &&
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cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
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}
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if (!CanFold)
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return SDValue();
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assert(V1.getNode() && "Expected at least two non-zero elements!");
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if (V1.getSimpleValueType() != MVT::v4f32)
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V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
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if (V2.getSimpleValueType() != MVT::v4f32)
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V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
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// Ok, we can emit an INSERTPS instruction.
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unsigned ZMask = 0;
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for (int i = 0; i < 4; ++i)
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if (Zeroable[i])
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ZMask |= 1 << i;
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unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
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assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
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SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
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DAG.getIntPtrConstant(InsertPSMask));
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return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
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}
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/// getVShift - Return a vector logical shift node.
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@ -6997,8 +7030,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
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if (EVTBits == 32 && NumElems == 4) {
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SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
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NumZero, DAG, Subtarget, *this);
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SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
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if (V.getNode())
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return V;
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}
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@ -302,17 +302,8 @@ define <2 x i64> @test_insert_64_zext(<2 x i64> %i) {
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define <4 x i32> @PR19721(<4 x i32> %i) {
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; CHECK-LABEL: PR19721:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
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; CHECK-NEXT: movd %xmm1, %eax
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
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; CHECK-NEXT: movd %xmm1, %ecx
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; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3]
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; CHECK-NEXT: pxor %xmm0, %xmm0
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; CHECK-NEXT: xorps %xmm1, %xmm1
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: movd %ecx, %xmm1
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; CHECK-NEXT: movd %eax, %xmm2
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; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
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; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[0,1]
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; CHECK-NEXT: retl
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%bc = bitcast <4 x i32> %i to i128
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%insert = and i128 %bc, -4294967296
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@ -423,16 +423,18 @@ define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
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ret <4 x i32> %result
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}
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;;;;;; Shuffles optimizable with a single insertps instruction
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;;;;;; Shuffles optimizable with a single insertps or blend instruction
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define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
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; X32-LABEL: shuf_XYZ0:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
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; X32-NEXT: xorps %xmm1, %xmm1
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; X32-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
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; X32-NEXT: retl
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;
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; X64-LABEL: shuf_XYZ0:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
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; X64-NEXT: xorps %xmm1, %xmm1
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; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
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; X64-NEXT: retq
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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@ -447,12 +449,12 @@ define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
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define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
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; X32-LABEL: shuf_XY00:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
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; X32-NEXT: movq %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: shuf_XY00:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
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; X64-NEXT: movq %xmm0, %xmm0
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; X64-NEXT: retq
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%vecext = extractelement <4 x float> %x, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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@ -595,12 +597,14 @@ define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
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define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
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; X32-LABEL: i32_shuf_XYZ0:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
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; X32-NEXT: pxor %xmm1, %xmm1
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; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
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; X32-NEXT: retl
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;
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; X64-LABEL: i32_shuf_XYZ0:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],zero
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; X64-NEXT: pxor %xmm1, %xmm1
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; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
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; X64-NEXT: retq
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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@ -615,12 +619,12 @@ define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
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define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
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; X32-LABEL: i32_shuf_XY00:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
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; X32-NEXT: movq %xmm0, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: i32_shuf_XY00:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],zero,zero
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; X64-NEXT: movq %xmm0, %xmm0
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; X64-NEXT: retq
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%vecext = extractelement <4 x i32> %x, i32 0
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%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
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@ -764,15 +768,15 @@ define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
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define < 4 x float> @test_insertps_no_undef(<4 x float> %x) {
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; X32-LABEL: test_insertps_no_undef:
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; X32: ## BB#0:
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; X32-NEXT: movaps %xmm0, %xmm1
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; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],zero
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; X32-NEXT: xorps %xmm1, %xmm1
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; X32-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3]
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; X32-NEXT: maxps %xmm1, %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: test_insertps_no_undef:
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; X64: ## BB#0:
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; X64-NEXT: movaps %xmm0, %xmm1
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; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],zero
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; X64-NEXT: xorps %xmm1, %xmm1
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; X64-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3]
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; X64-NEXT: maxps %xmm1, %xmm0
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; X64-NEXT: retq
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%vecext = extractelement <4 x float> %x, i32 0
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@ -1022,3 +1026,123 @@ define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
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store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4
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ret void
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}
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define <4 x float> @insertps_4(<4 x float> %A, <4 x float> %B) {
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; X32-LABEL: insertps_4:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_4:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
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; X64-NEXT: retq
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entry:
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%vecext = extractelement <4 x float> %A, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
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%vecext2 = extractelement <4 x float> %B, i32 2
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%vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
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ret <4 x float> %vecinit4
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}
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define <4 x float> @insertps_5(<4 x float> %A, <4 x float> %B) {
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; X32-LABEL: insertps_5:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_5:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
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; X64-NEXT: retq
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entry:
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%vecext = extractelement <4 x float> %A, i32 0
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%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
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%vecext1 = extractelement <4 x float> %B, i32 1
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%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
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%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
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%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
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ret <4 x float> %vecinit4
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}
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define <4 x float> @insertps_6(<4 x float> %A, <4 x float> %B) {
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; X32-LABEL: insertps_6:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_6:
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; X64: ## BB#0:
|
||||
; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%vecext = extractelement <4 x float> %A, i32 1
|
||||
%vecinit = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %vecext, i32 1
|
||||
%vecext1 = extractelement <4 x float> %B, i32 2
|
||||
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 2
|
||||
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 3
|
||||
ret <4 x float> %vecinit3
|
||||
}
|
||||
|
||||
define <4 x float> @insertps_7(<4 x float> %A, <4 x float> %B) {
|
||||
; X32-LABEL: insertps_7:
|
||||
; X32: ## BB#0:
|
||||
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: insertps_7:
|
||||
; X64: ## BB#0:
|
||||
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%vecext = extractelement <4 x float> %A, i32 0
|
||||
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
||||
%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
|
||||
%vecext2 = extractelement <4 x float> %B, i32 1
|
||||
%vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
|
||||
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
|
||||
ret <4 x float> %vecinit4
|
||||
}
|
||||
|
||||
define <4 x float> @insertps_8(<4 x float> %A, <4 x float> %B) {
|
||||
; X32-LABEL: insertps_8:
|
||||
; X32: ## BB#0:
|
||||
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: insertps_8:
|
||||
; X64: ## BB#0:
|
||||
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%vecext = extractelement <4 x float> %A, i32 0
|
||||
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
||||
%vecext1 = extractelement <4 x float> %B, i32 0
|
||||
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
||||
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
|
||||
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
|
||||
ret <4 x float> %vecinit4
|
||||
}
|
||||
|
||||
define <4 x float> @insertps_9(<4 x float> %A, <4 x float> %B) {
|
||||
; X32-LABEL: insertps_9:
|
||||
; X32: ## BB#0:
|
||||
; X32-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
|
||||
; X32-NEXT: movaps %xmm1, %xmm0
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: insertps_9:
|
||||
; X64: ## BB#0:
|
||||
; X64-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
|
||||
; X64-NEXT: movaps %xmm1, %xmm0
|
||||
; X64-NEXT: retq
|
||||
entry:
|
||||
%vecext = extractelement <4 x float> %A, i32 0
|
||||
%vecinit = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %vecext, i32 1
|
||||
%vecext1 = extractelement <4 x float> %B, i32 2
|
||||
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 2
|
||||
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 3
|
||||
ret <4 x float> %vecinit3
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue