forked from OSchip/llvm-project
Masked gather and scatter intrinsics - enabled codegen for KNL.
llvm-svn: 236394
This commit is contained in:
Elena Demikhovsky
parent
a63b7cee66
commit
1b60ed7069
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@ -625,6 +625,7 @@ private:
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void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_MLOAD(MaskedLoadSDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_MGATHER(MaskedGatherSDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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@ -643,6 +644,8 @@ private:
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SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N);
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SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
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SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
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SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
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SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
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SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
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SDValue SplitVecOp_VSETCC(SDNode *N);
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SDValue SplitVecOp_FP_ROUND(SDNode *N);
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@ -196,6 +196,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
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bool HasVectorValue = false;
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if (Op.getOpcode() == ISD::LOAD) {
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LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
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ISD::LoadExtType ExtType = LD->getExtensionType();
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@ -243,9 +244,9 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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Changed = true;
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return LegalizeOp(ExpandStore(Op));
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}
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}
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} else if (Op.getOpcode() == ISD::MSCATTER)
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HasVectorValue = true;
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bool HasVectorValue = false;
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for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
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J != E;
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++J)
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@ -330,6 +331,9 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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case ISD::UINT_TO_FP:
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QueryType = Node->getOperand(0).getValueType();
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break;
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case ISD::MSCATTER:
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QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
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break;
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}
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switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
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@ -600,6 +600,9 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::MLOAD:
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SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
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break;
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case ISD::MGATHER:
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SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
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break;
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case ISD::SETCC:
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SplitVecRes_SETCC(N, Lo, Hi);
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break;
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@ -1045,6 +1048,54 @@ void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
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}
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void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
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SDValue &Lo, SDValue &Hi) {
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EVT LoVT, HiVT;
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SDLoc dl(MGT);
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std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
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SDValue Ch = MGT->getChain();
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SDValue Ptr = MGT->getBasePtr();
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SDValue Mask = MGT->getMask();
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unsigned Alignment = MGT->getOriginalAlignment();
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SDValue MaskLo, MaskHi;
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std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
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EVT MemoryVT = MGT->getMemoryVT();
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EVT LoMemVT, HiMemVT;
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std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
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SDValue Src0Lo, Src0Hi;
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std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
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SDValue IndexHi, IndexLo;
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std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
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MachineMemOperand *MMO = DAG.getMachineFunction().
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getMachineMemOperand(MGT->getPointerInfo(),
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MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
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Alignment, MGT->getAAInfo(), MGT->getRanges());
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SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
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Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
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MMO);
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SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
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Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
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MMO);
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// Build a factor node to remember that this load is independent of the
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// other one.
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Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDValue(MGT, 1), Ch);
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}
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void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
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assert(N->getValueType(0).isVector() &&
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N->getOperand(0).getValueType().isVector() &&
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@ -1306,6 +1357,12 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
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case ISD::MSTORE:
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Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
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break;
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case ISD::MSCATTER:
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Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
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break;
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case ISD::MGATHER:
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Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
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break;
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case ISD::VSELECT:
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Res = SplitVecOp_VSELECT(N, OpNo);
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break;
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@ -1478,6 +1535,68 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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MachinePointerInfo(), EltVT, false, false, false, 0);
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}
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SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
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unsigned OpNo) {
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EVT LoVT, HiVT;
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SDLoc dl(MGT);
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std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
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SDValue Ch = MGT->getChain();
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SDValue Ptr = MGT->getBasePtr();
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SDValue Index = MGT->getIndex();
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SDValue Mask = MGT->getMask();
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unsigned Alignment = MGT->getOriginalAlignment();
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SDValue MaskLo, MaskHi;
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std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
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EVT MemoryVT = MGT->getMemoryVT();
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EVT LoMemVT, HiMemVT;
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std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
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SDValue Src0Lo, Src0Hi;
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std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
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SDValue IndexHi, IndexLo;
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if (Index.getNode())
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std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
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else
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IndexLo = IndexHi = Index;
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MachineMemOperand *MMO = DAG.getMachineFunction().
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getMachineMemOperand(MGT->getPointerInfo(),
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MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
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Alignment, MGT->getAAInfo(), MGT->getRanges());
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SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
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SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
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OpsLo, MMO);
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MMO = DAG.getMachineFunction().
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getMachineMemOperand(MGT->getPointerInfo(),
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MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
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Alignment, MGT->getAAInfo(),
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MGT->getRanges());
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SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
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SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
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OpsHi, MMO);
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// Build a factor node to remember that this load is independent of the
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// other one.
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Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDValue(MGT, 1), Ch);
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SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
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Hi);
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ReplaceValueWith(SDValue(MGT, 0), Res);
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return SDValue();
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}
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SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
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unsigned OpNo) {
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SDValue Ch = N->getChain();
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@ -1523,11 +1642,64 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
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Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
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N->isTruncatingStore());
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// Build a factor node to remember that this store is independent of the
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// other one.
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
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}
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SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
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unsigned OpNo) {
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SDValue Ch = N->getChain();
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SDValue Ptr = N->getBasePtr();
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SDValue Mask = N->getMask();
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SDValue Index = N->getIndex();
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SDValue Data = N->getValue();
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EVT MemoryVT = N->getMemoryVT();
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unsigned Alignment = N->getOriginalAlignment();
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SDLoc DL(N);
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EVT LoMemVT, HiMemVT;
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std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
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SDValue DataLo, DataHi;
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GetSplitVector(Data, DataLo, DataHi);
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SDValue MaskLo, MaskHi;
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GetSplitVector(Mask, MaskLo, MaskHi);
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SDValue PtrLo, PtrHi;
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if (Ptr.getValueType().isVector()) // gather form vector of pointers
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std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
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else
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PtrLo = PtrHi = Ptr;
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SDValue IndexHi, IndexLo;
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if (Index.getNode())
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std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
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else
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IndexLo = IndexHi = Index;
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SDValue Lo, Hi;
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MachineMemOperand *MMO = DAG.getMachineFunction().
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getMachineMemOperand(N->getPointerInfo(),
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MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
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Alignment, N->getAAInfo(), N->getRanges());
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SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
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Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
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DL, OpsLo, MMO);
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MMO = DAG.getMachineFunction().
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getMachineMemOperand(N->getPointerInfo(),
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MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
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Alignment, N->getAAInfo(), N->getRanges());
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SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
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Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
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DL, OpsHi, MMO);
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// Build a factor node to remember that this store is independent of the
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// other one.
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return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
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}
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SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
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@ -1389,6 +1389,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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// Custom lower several nodes.
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for (MVT VT : MVT::vector_valuetypes()) {
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unsigned EltSize = VT.getVectorElementType().getSizeInBits();
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if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
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setOperationAction(ISD::MGATHER, VT, Custom);
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setOperationAction(ISD::MSCATTER, VT, Custom);
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}
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// Extract subvector is special because the value type
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// (result) is 256/128-bit but the source is 512-bit wide.
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if (VT.is128BitVector() || VT.is256BitVector()) {
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@ -17360,6 +17364,56 @@ static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
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return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
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}
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static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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assert(Subtarget->hasAVX512() &&
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"MGATHER/MSCATTER are supported on AVX-512 arch only");
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MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
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EVT VT = N->getValue().getValueType();
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assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
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SDLoc dl(Op);
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// X86 scatter kills mask register, so its type should be added to
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// the list of return values
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if (N->getNumValues() == 1) {
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SDValue Index = N->getIndex();
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if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
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!Index.getValueType().is512BitVector())
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Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
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SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
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N->getOperand(3), Index };
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SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
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DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
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return SDValue(NewScatter.getNode(), 0);
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}
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return Op;
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}
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static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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assert(Subtarget->hasAVX512() &&
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"MGATHER/MSCATTER are supported on AVX-512 arch only");
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MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
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EVT VT = Op.getValueType();
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assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
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SDLoc dl(Op);
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SDValue Index = N->getIndex();
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if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
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!Index.getValueType().is512BitVector()) {
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Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
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N->getOperand(3), Index };
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DAG.UpdateNodeOperands(N, Ops);
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}
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return Op;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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@ -17447,6 +17501,8 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ADD: return LowerADD(Op, DAG);
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case ISD::SUB: return LowerSUB(Op, DAG);
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case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
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case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
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case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
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}
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}
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@ -0,0 +1,142 @@
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; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=knl < %s | FileCheck %s -check-prefix=KNL
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; KNL-LABEL: test1
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; KNL: kxnorw %k1, %k1, %k1
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; KNL: vgatherdps (%rdi,%zmm0,4), %zmm1 {%k1}
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define <16 x float> @test1(float* %base, <16 x i32> %ind) {
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%broadcast.splatinsert = insertelement <16 x float*> undef, float* %base, i32 0
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%broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
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%sext_ind = sext <16 x i32> %ind to <16 x i64>
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%gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
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%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
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ret <16 x float>%res
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}
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declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>)
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declare <16 x float> @llvm.masked.gather.v16f32(<16 x float*>, i32, <16 x i1>, <16 x float>)
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declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> , i32, <8 x i1> , <8 x i32> )
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; KNL-LABEL: test2
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; KNL: kmovw %esi, %k1
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; KNL: vgatherdps (%rdi,%zmm0,4), %zmm1 {%k1}
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define <16 x float> @test2(float* %base, <16 x i32> %ind, i16 %mask) {
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%broadcast.splatinsert = insertelement <16 x float*> undef, float* %base, i32 0
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%broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
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%sext_ind = sext <16 x i32> %ind to <16 x i64>
|
||||
%gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
|
||||
%imask = bitcast i16 %mask to <16 x i1>
|
||||
%res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> %imask, <16 x float>undef)
|
||||
ret <16 x float> %res
|
||||
}
|
||||
|
||||
; KNL-LABEL: test3
|
||||
; KNL: kmovw %esi, %k1
|
||||
; KNL: vpgatherdd (%rdi,%zmm0,4), %zmm1 {%k1}
|
||||
define <16 x i32> @test3(i32* %base, <16 x i32> %ind, i16 %mask) {
|
||||
|
||||
%broadcast.splatinsert = insertelement <16 x i32*> undef, i32* %base, i32 0
|
||||
%broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
|
||||
|
||||
%sext_ind = sext <16 x i32> %ind to <16 x i64>
|
||||
%gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i64> %sext_ind
|
||||
%imask = bitcast i16 %mask to <16 x i1>
|
||||
%res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
; KNL-LABEL: test4
|
||||
; KNL: kmovw %esi, %k1
|
||||
; KNL: kmovw
|
||||
; KNL: vpgatherdd
|
||||
; KNL: vpgatherdd
|
||||
|
||||
define <16 x i32> @test4(i32* %base, <16 x i32> %ind, i16 %mask) {
|
||||
|
||||
%broadcast.splatinsert = insertelement <16 x i32*> undef, i32* %base, i32 0
|
||||
%broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
|
||||
|
||||
%gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
|
||||
%imask = bitcast i16 %mask to <16 x i1>
|
||||
%gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
|
||||
%gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
|
||||
%res = add <16 x i32> %gt1, %gt2
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
||||
; KNL-LABEL: test5
|
||||
; KNL: kmovw %k1, %k2
|
||||
; KNL: vpscatterdd {{.*}}%k2
|
||||
; KNL: vpscatterdd {{.*}}%k1
|
||||
|
||||
define void @test5(i32* %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) {
|
||||
|
||||
%broadcast.splatinsert = insertelement <16 x i32*> undef, i32* %base, i32 0
|
||||
%broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
|
||||
|
||||
%gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
|
||||
%imask = bitcast i16 %mask to <16 x i1>
|
||||
call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
|
||||
call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.masked.scatter.v8i32(<8 x i32> , <8 x i32*> , i32 , <8 x i1> )
|
||||
declare void @llvm.masked.scatter.v16i32(<16 x i32> , <16 x i32*> , i32 , <16 x i1> )
|
||||
|
||||
; KNL-LABEL: test6
|
||||
; KNL: kxnorw %k1, %k1, %k1
|
||||
; KNL: kxnorw %k2, %k2, %k2
|
||||
; KNL: vpgatherqd (,%zmm{{.*}}), %ymm{{.*}} {%k2}
|
||||
; KNL: vpscatterqd %ymm{{.*}}, (,%zmm{{.*}}) {%k1}
|
||||
define <8 x i32> @test6(<8 x i32>%a1, <8 x i32*> %ptr) {
|
||||
|
||||
%a = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef)
|
||||
|
||||
call void @llvm.masked.scatter.v8i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
|
||||
ret <8 x i32>%a
|
||||
}
|
||||
|
||||
; In this case the index should be promoted to <8 x i64> for KNL
|
||||
; KNL-LABEL: test7
|
||||
; KNL: vpmovsxdq %ymm0, %zmm0
|
||||
; KNL: kmovw %k1, %k2
|
||||
; KNL: vpgatherqd {{.*}} {%k2}
|
||||
; KNL: vpgatherqd {{.*}} {%k1}
|
||||
define <8 x i32> @test7(i32* %base, <8 x i32> %ind, i8 %mask) {
|
||||
|
||||
%broadcast.splatinsert = insertelement <8 x i32*> undef, i32* %base, i32 0
|
||||
%broadcast.splat = shufflevector <8 x i32*> %broadcast.splatinsert, <8 x i32*> undef, <8 x i32> zeroinitializer
|
||||
|
||||
%gep.random = getelementptr i32, <8 x i32*> %broadcast.splat, <8 x i32> %ind
|
||||
%imask = bitcast i8 %mask to <8 x i1>
|
||||
%gt1 = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.random, i32 4, <8 x i1> %imask, <8 x i32>undef)
|
||||
%gt2 = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.random, i32 4, <8 x i1> %imask, <8 x i32>%gt1)
|
||||
%res = add <8 x i32> %gt1, %gt2
|
||||
ret <8 x i32> %res
|
||||
}
|
||||
|
||||
; No uniform base in this case, index <8 x i64> contains addresses,
|
||||
; each gather call will be split into two
|
||||
; KNL-LABEL: test8
|
||||
; KNL: kshiftrw $8, %k1, %k2
|
||||
; KNL: vpgatherqd
|
||||
; KNL: vpgatherqd
|
||||
; KNL: vinserti64x4
|
||||
; KNL: vpgatherqd
|
||||
; KNL: vpgatherqd
|
||||
; KNL: vinserti64x4
|
||||
define <16 x i32> @test8(<16 x i32*> %ptr.random, <16 x i32> %ind, i16 %mask) {
|
||||
%imask = bitcast i16 %mask to <16 x i1>
|
||||
%gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
|
||||
%gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %ptr.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
|
||||
%res = add <16 x i32> %gt1, %gt2
|
||||
ret <16 x i32> %res
|
||||
}
|
||||
|
|
@ -7,8 +7,8 @@
|
|||
; AVX512: vmovdqu32 (%rdi), %zmm0 {%k1} {z}
|
||||
|
||||
; AVX2-LABEL: test1
|
||||
; AVX2: vpmaskmovd 32(%rdi)
|
||||
; AVX2: vpmaskmovd (%rdi)
|
||||
; AVX2: vpmaskmovd {{.*}}(%rdi)
|
||||
; AVX2: vpmaskmovd {{.*}}(%rdi)
|
||||
; AVX2-NOT: blend
|
||||
|
||||
; AVX_SCALAR-LABEL: test1
|
||||
|
|
|
|||
Loading…
Reference in New Issue