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[AArch64] add select tests with partial vector undefs; NFC

This commit is contained in:
Sanjay Patel 2021-03-02 13:07:16 -05:00
parent 068aa12f96
commit 1b5ab13541
1 changed files with 63 additions and 0 deletions
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63
llvm/test/CodeGen/AArch64/select-with-and-or.ll
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@ -116,3 +116,66 @@ define <4 x i1> @or_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32>
%s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 1, i1 1, i1 1>
ret <4 x i1> %s
}
define <4 x i1> @and_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
; CHECK-LABEL: and_vec_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmgt v1.4s, v2.4s, v3.4s
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%a = icmp eq <4 x i32> %x, %y
%b = icmp sgt <4 x i32> %z, %w
%s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 0, i1 undef, i1 0, i1 undef>
ret <4 x i1> %s
}
define <4 x i1> @or_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
; CHECK-LABEL: or_vec_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmgt v1.4s, v2.4s, v3.4s
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: xtn v1.4h, v1.4s
; CHECK-NEXT: movi v2.4h, #1
; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b
; CHECK-NEXT: ret
%a = icmp eq <4 x i32> %x, %y
%b = icmp sgt <4 x i32> %z, %w
%s = select <4 x i1> %a, <4 x i1> <i1 undef, i1 1, i1 1, i1 undef>, <4 x i1> %b
ret <4 x i1> %s
}
define <4 x i1> @and_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
; CHECK-LABEL: and_not_vec_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmgt v1.4s, v2.4s, v3.4s
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: xtn v1.4h, v1.4s
; CHECK-NEXT: bic v0.8b, v1.8b, v0.8b
; CHECK-NEXT: ret
%a = icmp eq <4 x i32> %x, %y
%b = icmp sgt <4 x i32> %z, %w
%s = select <4 x i1> %a, <4 x i1> <i1 0, i1 0, i1 undef, i1 0>, <4 x i1> %b
ret <4 x i1> %s
}
define <4 x i1> @or_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {
; CHECK-LABEL: or_not_vec_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmgt v1.4s, v2.4s, v3.4s
; CHECK-NEXT: movi v2.4h, #1
; CHECK-NEXT: xtn v3.4h, v0.4s
; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: bic v1.8b, v2.8b, v3.8b
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%a = icmp eq <4 x i32> %x, %y
%b = icmp sgt <4 x i32> %z, %w
%s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 undef, i1 1, i1 1>
ret <4 x i1> %s
}