forked from OSchip/llvm-project
[RISCV] Enable cross basic block aware vsetvli insertion
This patch extends D102737 to allow VL/VTYPE changes to be taken into account before adding an explicit vsetvli. We do this by using a data flow analysis to propagate VL/VTYPE information from predecessors until we've determined a value for every value in the function. We use this information to determine if a vsetvli needs to be inserted before the first vector instruction the block. Differential Revision: https://reviews.llvm.org/D102739
This commit is contained in:
Craig Topper
parent
ea91a8cbab
commit
1b47a3de48
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@ -9,13 +9,17 @@
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// This file implements a function pass that inserts VSETVLI instructions where
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// needed.
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//
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// The pass consists of a single pass over each basic block looking for changes
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// in VL/VTYPE usage that requires a vsetvli to be inserted. We assume the
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// VL/VTYPE values are unknown from predecessors so the first vector instruction
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// will always require a new VSETVLI.
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// This pass consists of 3 phases:
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//
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// TODO: Future enhancements to this pass will take into account VL/VTYPE from
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// predecessors.
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// Phase 1 collects how each basic block affects VL/VTYPE.
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//
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// Phase 2 uses the information from phase 1 to do a data flow analysis to
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// propagate the VL/VTYPE changes through the function. This gives us the
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// VL/VTYPE at the start of each basic block.
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//
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// Phase 3 inserts VSETVLI instructions in each basic block. Information from
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// phase 2 is used to prevent inserting a VSETVLI before the first vector
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// instruction in the block if possible.
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//
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//===----------------------------------------------------------------------===//
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@ -23,6 +27,7 @@
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include <queue>
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using namespace llvm;
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#define DEBUG_TYPE "riscv-insert-vsetvli"
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@ -52,6 +57,12 @@ class VSETVLIInfo {
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public:
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VSETVLIInfo() : AVLImm(0) {}
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static VSETVLIInfo getUnknown() {
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VSETVLIInfo Info;
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Info.setUnknown();
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return Info;
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}
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bool isValid() const { return State != Uninitialized; }
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void setUnknown() { State = Unknown; }
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bool isUnknown() const { return State == Unknown; }
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@ -148,12 +159,89 @@ public:
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return getAVLReg() == Other.getAVLReg();
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}
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bool operator==(const VSETVLIInfo &Other) const {
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// Uninitialized is only equal to another Uninitialized.
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if (!isValid())
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return !Other.isValid();
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if (!Other.isValid())
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return !isValid();
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// Unknown is only equal to another Unknown.
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if (isUnknown())
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return Other.isUnknown();
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if (Other.isUnknown())
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return isUnknown();
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// Otherwise compare the VTYPE and AVL.
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return hasSameVTYPE(Other) && hasSameAVL(Other);
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}
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bool operator!=(const VSETVLIInfo &Other) const { return !(*this == Other); }
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// Calculate the VSETVLIInfo visible to a block assuming this and Other are
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// both predecessors.
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VSETVLIInfo intersect(const VSETVLIInfo &Other) const {
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// If the new value isn't valid, ignore it.
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if (!Other.isValid())
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return *this;
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// If this value isn't valid, this must be the first predecessor, use it.
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if (!isValid())
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return Other;
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if (*this == Other)
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return *this;
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// If the configurations don't match, assume unknown.
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return VSETVLIInfo::getUnknown();
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}
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// Calculate the VSETVLIInfo visible at the end of the block assuming this
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// is the predecessor value, and Other is change for this block.
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VSETVLIInfo merge(const VSETVLIInfo &Other) const {
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assert(isValid() && "Can only merge with a valid VSETVLInfo");
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// Nothing changed from the predecessor, keep it.
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if (!Other.isValid())
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return *this;
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// If the change is compatible with the input, we won't create a VSETVLI
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// and should keep the predecessor.
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if (isCompatible(Other))
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return *this;
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// Otherwise just use whatever is in this block.
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return Other;
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}
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};
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struct BlockData {
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// The VSETVLIInfo that represents the net changes to the VL/VTYPE registers
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// made by this block. Calculated in Phase 1.
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VSETVLIInfo Change;
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// The VSETVLIInfo that represents the VL/VTYPE settings on exit from this
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// block. Calculated in Phase 2.
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VSETVLIInfo Exit;
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// The VSETVLIInfo that represents the VL/VTYPE settings from all predecessor
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// blocks. Calculated in Phase 2, and used by Phase 3.
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VSETVLIInfo Pred;
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// Keeps track of whether the block is already in the queue.
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bool InQueue = false;
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BlockData() {}
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};
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class RISCVInsertVSETVLI : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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std::vector<BlockData> BlockInfo;
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std::queue<const MachineBasicBlock *> WorkList;
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public:
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static char ID;
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@ -170,10 +258,13 @@ public:
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StringRef getPassName() const override { return RISCV_INSERT_VSETVLI_NAME; }
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private:
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bool needVSETVLI(const VSETVLIInfo &Require, const VSETVLIInfo &CurInfo);
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void insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
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const VSETVLIInfo &Info);
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bool emitVSETVLIs(MachineBasicBlock &MBB);
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bool computeVLVTYPEChanges(const MachineBasicBlock &MBB);
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void computeIncomingVLVTYPE(const MachineBasicBlock &MBB);
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void emitVSETVLIs(MachineBasicBlock &MBB);
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};
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} // end anonymous namespace
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@ -276,7 +367,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
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// Return a VSETVLIInfo representing the changes made by this VSETVLI or
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// VSETIVLI instruction.
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VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
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static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
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VSETVLIInfo NewInfo;
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if (MI.getOpcode() == RISCV::PseudoVSETVLI) {
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Register AVLReg = MI.getOperand(1).getReg();
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@ -292,12 +383,111 @@ VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
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return NewInfo;
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}
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bool RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
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bool MadeChange = false;
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bool RISCVInsertVSETVLI::needVSETVLI(const VSETVLIInfo &Require,
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const VSETVLIInfo &CurInfo) {
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if (CurInfo.isCompatible(Require))
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return false;
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// Assume predecessor state is unknown.
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// We didn't find a compatible value. If our AVL is a virtual register,
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// it might be defined by a VSET(I)VLI. If it has the same VTYPE we need
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// and the last VL/VTYPE we observed is the same, we don't need a
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// VSETVLI here.
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if (!CurInfo.isUnknown() && Require.hasAVLReg() &&
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Require.getAVLReg().isVirtual() && Require.hasSameVTYPE(CurInfo)) {
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if (MachineInstr *DefMI = MRI->getVRegDef(Require.getAVLReg())) {
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if (DefMI->getOpcode() == RISCV::PseudoVSETVLI ||
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DefMI->getOpcode() == RISCV::PseudoVSETIVLI) {
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VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
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if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo))
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return false;
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}
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}
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}
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return true;
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}
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bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB) {
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bool HadVectorOp = false;
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BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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for (const MachineInstr &MI : MBB) {
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// If this is an explicit VSETVLI or VSETIVLI, update our state.
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if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
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MI.getOpcode() == RISCV::PseudoVSETIVLI) {
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HadVectorOp = true;
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BBInfo.Change = getInfoForVSETVLI(MI);
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continue;
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}
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uint64_t TSFlags = MI.getDesc().TSFlags;
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if (RISCVII::hasSEWOp(TSFlags)) {
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HadVectorOp = true;
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VSETVLIInfo NewInfo = computeInfoForInstr(MI, TSFlags, MRI);
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if (!BBInfo.Change.isValid()) {
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BBInfo.Change = NewInfo;
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} else {
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// If this instruction isn't compatible with the previous VL/VTYPE
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// we need to insert a VSETVLI.
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if (needVSETVLI(NewInfo, BBInfo.Change))
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BBInfo.Change = NewInfo;
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}
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}
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// If this is something that updates VL/VTYPE that we don't know about, set
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// the state to unknown.
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if (MI.isCall() || MI.modifiesRegister(RISCV::VL) ||
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MI.modifiesRegister(RISCV::VTYPE)) {
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BBInfo.Change = VSETVLIInfo::getUnknown();
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}
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}
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// Initial exit state is whatever change we found in the block.
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BBInfo.Exit = BBInfo.Change;
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return HadVectorOp;
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}
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void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
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BlockData &BBInfo = BlockInfo[MBB.getNumber()];
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BBInfo.InQueue = false;
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VSETVLIInfo InInfo;
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if (MBB.pred_empty()) {
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// There are no predecessors, so use the default starting status.
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InInfo.setUnknown();
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} else {
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for (MachineBasicBlock *P : MBB.predecessors())
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InInfo = InInfo.intersect(BlockInfo[P->getNumber()].Exit);
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}
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// If we don't have any valid predecessor value, wait until we do.
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if (!InInfo.isValid())
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return;
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BBInfo.Pred = InInfo;
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VSETVLIInfo TmpStatus = BBInfo.Pred.merge(BBInfo.Change);
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// If the new exit value matches the old exit value, we don't need to revisit
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// any blocks.
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if (BBInfo.Exit == TmpStatus)
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return;
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BBInfo.Exit = TmpStatus;
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// Add the successors to the work list so we can propagate the changed exit
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// status.
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for (MachineBasicBlock *S : MBB.successors())
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if (!BlockInfo[S->getNumber()].InQueue)
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WorkList.push(S);
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}
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void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
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VSETVLIInfo CurInfo;
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CurInfo.setUnknown();
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for (MachineInstr &MI : MBB) {
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// If this is an explicit VSETVLI or VSETIVLI, update our state.
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@ -309,7 +499,6 @@ bool RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
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"Unexpected operands where VL and VTYPE should be");
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MI.getOperand(3).setIsDead(false);
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MI.getOperand(4).setIsDead(false);
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MadeChange = true;
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CurInfo = getInfoForVSETVLI(MI);
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continue;
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}
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@ -330,47 +519,32 @@ bool RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
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MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false,
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/*isImp*/ true));
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bool NeedVSETVLI = true;
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if (CurInfo.isValid() && CurInfo.isCompatible(NewInfo))
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NeedVSETVLI = false;
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// We didn't find a compatible value. If our AVL is a virtual register,
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// it might be defined by a VSET(I)VLI. If it has the same VTYPE we need
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// and the last VL/VTYPE we observed is the same, we don't need a
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// VSETVLI here.
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if (NeedVSETVLI && !CurInfo.isUnknown() && NewInfo.hasAVLReg() &&
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NewInfo.getAVLReg().isVirtual() && NewInfo.hasSameVTYPE(CurInfo)) {
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if (MachineInstr *DefMI = MRI->getVRegDef(NewInfo.getAVLReg())) {
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if (DefMI->getOpcode() == RISCV::PseudoVSETVLI ||
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DefMI->getOpcode() == RISCV::PseudoVSETIVLI) {
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VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
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if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVTYPE(CurInfo))
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NeedVSETVLI = false;
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}
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if (!CurInfo.isValid()) {
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// We haven't found any vector instructions or VL/VTYPE changes yet,
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// use the predecessor information.
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assert(BlockInfo[MBB.getNumber()].Pred.isValid() &&
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"Expected a valid predecessor state.");
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if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred)) {
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insertVSETVLI(MBB, MI, NewInfo);
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CurInfo = NewInfo;
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}
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} else {
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// If this instruction isn't compatible with the previous VL/VTYPE
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// we need to insert a VSETVLI.
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if (needVSETVLI(NewInfo, CurInfo)) {
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insertVSETVLI(MBB, MI, NewInfo);
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CurInfo = NewInfo;
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}
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}
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// If this instruction isn't compatible with the previous VL/VTYPE
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// we need to insert a VSETVLI.
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if (NeedVSETVLI) {
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insertVSETVLI(MBB, MI, NewInfo);
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CurInfo = NewInfo;
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}
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// If we find an instruction we at least changed the operands.
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MadeChange = true;
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}
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// If this is something updates VL/VTYPE that we don't know about, set
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// the state to unknown.
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if (MI.isCall() || MI.modifiesRegister(RISCV::VL) ||
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MI.modifiesRegister(RISCV::VTYPE)) {
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VSETVLIInfo NewInfo;
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NewInfo.setUnknown();
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CurInfo = NewInfo;
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CurInfo = VSETVLIInfo::getUnknown();
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}
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}
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return MadeChange;
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}
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bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
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@ -382,12 +556,41 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
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TII = ST.getInstrInfo();
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MRI = &MF.getRegInfo();
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bool Changed = false;
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assert(BlockInfo.empty() && "Expect empty block infos");
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BlockInfo.resize(MF.getNumBlockIDs());
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for (MachineBasicBlock &MBB : MF)
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Changed |= emitVSETVLIs(MBB);
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bool HaveVectorOp = false;
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return Changed;
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// Phase 1 - determine how VL/VTYPE are affected by the each block.
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for (const MachineBasicBlock &MBB : MF)
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HaveVectorOp |= computeVLVTYPEChanges(MBB);
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// If we didn't find any instructions that need VSETVLI, we're done.
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if (HaveVectorOp) {
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// Phase 2 - determine the exit VL/VTYPE from each block. We add all
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// blocks to the list here, but will also add any that need to be revisited
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// during Phase 2 processing.
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for (const MachineBasicBlock &MBB : MF) {
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WorkList.push(&MBB);
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BlockInfo[MBB.getNumber()].InQueue = true;
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}
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while (!WorkList.empty()) {
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const MachineBasicBlock &MBB = *WorkList.front();
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WorkList.pop();
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computeIncomingVLVTYPE(MBB);
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}
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// Phase 3 - add any vsetvli instructions needed in the block. Use the
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// Phase 2 information to avoid adding vsetvlis before the first vector
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// instruction in the block if the VL/VTYPE is satisfied by its
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// predecessors.
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for (MachineBasicBlock &MBB : MF)
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emitVSETVLIs(MBB);
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}
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BlockInfo.clear();
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return HaveVectorOp;
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}
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/// Returns an instance of the Insert VSETVLI pass.
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@ -3667,11 +3667,10 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
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; LMULMAX2-RV32-NEXT: addi a3, a1, 819
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; LMULMAX2-RV32-NEXT: lui a1, 61681
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; LMULMAX2-RV32-NEXT: addi a7, a1, -241
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; LMULMAX2-RV32-NEXT: lui a2, 4112
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; LMULMAX2-RV32-NEXT: addi a2, a2, 257
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; LMULMAX2-RV32-NEXT: lui a1, 4112
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; LMULMAX2-RV32-NEXT: addi a2, a1, 257
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; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_2
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; LMULMAX2-RV32-NEXT: # %bb.1:
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; LMULMAX2-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
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; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
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; LMULMAX2-RV32-NEXT: srli a5, a1, 1
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; LMULMAX2-RV32-NEXT: or a1, a1, a5
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@ -3723,14 +3722,12 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
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; LMULMAX2-RV32-NEXT: mul a1, a1, a2
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; LMULMAX2-RV32-NEXT: srli a5, a1, 24
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; LMULMAX2-RV32-NEXT: .LBB3_3:
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; LMULMAX2-RV32-NEXT: sw a5, 0(sp)
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; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
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; LMULMAX2-RV32-NEXT: vslidedown.vi v25, v25, 1
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; LMULMAX2-RV32-NEXT: vsrl.vx v26, v25, a6
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; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
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; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_5
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; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
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; LMULMAX2-RV32-NEXT: sw a5, 0(sp)
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; LMULMAX2-RV32-NEXT: bnez a1, .LBB3_5
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; LMULMAX2-RV32-NEXT: # %bb.4:
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; LMULMAX2-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -3758,8 +3755,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX2-RV32-NEXT: j .LBB3_6
|
||||
; LMULMAX2-RV32-NEXT: .LBB3_5:
|
||||
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a5, a1
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 4
|
||||
|
|
@ -3902,11 +3899,10 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a3, a1, 819
|
||||
; LMULMAX1-RV32-NEXT: lui a1, 61681
|
||||
; LMULMAX1-RV32-NEXT: addi a7, a1, -241
|
||||
; LMULMAX1-RV32-NEXT: lui a2, 4112
|
||||
; LMULMAX1-RV32-NEXT: addi a2, a2, 257
|
||||
; LMULMAX1-RV32-NEXT: lui a1, 4112
|
||||
; LMULMAX1-RV32-NEXT: addi a2, a1, 257
|
||||
; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_2
|
||||
; LMULMAX1-RV32-NEXT: # %bb.1:
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -3958,14 +3954,12 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: mul a1, a1, a2
|
||||
; LMULMAX1-RV32-NEXT: srli a5, a1, 24
|
||||
; LMULMAX1-RV32-NEXT: .LBB3_3:
|
||||
; LMULMAX1-RV32-NEXT: sw a5, 0(sp)
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a5, v26
|
||||
; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_5
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: sw a5, 0(sp)
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB3_5
|
||||
; LMULMAX1-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -3993,8 +3987,8 @@ define void @ctlz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX1-RV32-NEXT: j .LBB3_6
|
||||
; LMULMAX1-RV32-NEXT: .LBB3_5:
|
||||
; LMULMAX1-RV32-NEXT: srli a1, a5, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a5, a1
|
||||
; LMULMAX1-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX1-RV32-NEXT: srli a5, a1, 2
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX1-RV32-NEXT: srli a5, a1, 4
|
||||
|
|
@ -11124,11 +11118,10 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a3, a1, 819
|
||||
; LMULMAX2-RV32-NEXT: lui a1, 61681
|
||||
; LMULMAX2-RV32-NEXT: addi a7, a1, -241
|
||||
; LMULMAX2-RV32-NEXT: lui a2, 4112
|
||||
; LMULMAX2-RV32-NEXT: addi a2, a2, 257
|
||||
; LMULMAX2-RV32-NEXT: lui a1, 4112
|
||||
; LMULMAX2-RV32-NEXT: addi a2, a1, 257
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_2
|
||||
; LMULMAX2-RV32-NEXT: # %bb.1:
|
||||
; LMULMAX2-RV32-NEXT: vsetvli zero, zero, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -11180,14 +11173,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_3:
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 0(sp)
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 3
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v30, v28, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v30
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_5
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v30
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 0(sp)
|
||||
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_5
|
||||
; LMULMAX2-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX2-RV32-NEXT: vsetvli zero, zero, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -11215,8 +11206,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a5, a1, 32
|
||||
; LMULMAX2-RV32-NEXT: j .LBB7_6
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_5:
|
||||
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a5, a1
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 4
|
||||
|
|
@ -11239,14 +11230,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_6:
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 24(sp)
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v30, v28, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v30
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_8
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v30
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 24(sp)
|
||||
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_8
|
||||
; LMULMAX2-RV32-NEXT: # %bb.7:
|
||||
; LMULMAX2-RV32-NEXT: vsetvli zero, zero, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -11274,8 +11263,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a5, a1, 32
|
||||
; LMULMAX2-RV32-NEXT: j .LBB7_9
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_8:
|
||||
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a5, a1
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 4
|
||||
|
|
@ -11298,14 +11287,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_9:
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v28, v26, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_11
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
|
||||
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_11
|
||||
; LMULMAX2-RV32-NEXT: # %bb.10:
|
||||
; LMULMAX2-RV32-NEXT: vsetvli zero, zero, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
|
|
@ -11333,8 +11320,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX2-RV32-NEXT: j .LBB7_12
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_11:
|
||||
; LMULMAX2-RV32-NEXT: srli a1, a5, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a5, a1
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 2
|
||||
; LMULMAX2-RV32-NEXT: or a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 4
|
||||
|
|
@ -11552,11 +11539,10 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a4, a2, 819
|
||||
; LMULMAX1-RV32-NEXT: lui a2, 61681
|
||||
; LMULMAX1-RV32-NEXT: addi t0, a2, -241
|
||||
; LMULMAX1-RV32-NEXT: lui a3, 4112
|
||||
; LMULMAX1-RV32-NEXT: addi a3, a3, 257
|
||||
; LMULMAX1-RV32-NEXT: lui a2, 4112
|
||||
; LMULMAX1-RV32-NEXT: addi a3, a2, 257
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_2
|
||||
; LMULMAX1-RV32-NEXT: # %bb.1:
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
|
|
@ -11608,14 +11594,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: mul a1, a1, a3
|
||||
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
|
||||
; LMULMAX1-RV32-NEXT: .LBB7_3:
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vslidedown.vi v26, v26, 1
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v27, v26, a7
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v27
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_5
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a2, v27
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 16(sp)
|
||||
; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_5
|
||||
; LMULMAX1-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
|
|
@ -11643,8 +11627,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX1-RV32-NEXT: j .LBB7_6
|
||||
; LMULMAX1-RV32-NEXT: .LBB7_5:
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
; LMULMAX1-RV32-NEXT: srli a1, a2, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a2, a1
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 4
|
||||
|
|
@ -11669,13 +11653,11 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: .LBB7_6:
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
|
||||
; LMULMAX1-RV32-NEXT: sw zero, 12(sp)
|
||||
; LMULMAX1-RV32-NEXT: sw zero, 4(sp)
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a7
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: sw zero, 4(sp)
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_8
|
||||
; LMULMAX1-RV32-NEXT: # %bb.7:
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
|
|
@ -11727,14 +11709,12 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: mul a1, a1, a3
|
||||
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
|
||||
; LMULMAX1-RV32-NEXT: .LBB7_9:
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 0(sp)
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a7
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_11
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a2, v26
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 0(sp)
|
||||
; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_11
|
||||
; LMULMAX1-RV32-NEXT: # %bb.10:
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
|
|
@ -11762,8 +11742,8 @@ define void @ctlz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX1-RV32-NEXT: j .LBB7_12
|
||||
; LMULMAX1-RV32-NEXT: .LBB7_11:
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
; LMULMAX1-RV32-NEXT: srli a1, a2, 1
|
||||
; LMULMAX1-RV32-NEXT: or a1, a2, a1
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 2
|
||||
; LMULMAX1-RV32-NEXT: or a1, a1, a2
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 4
|
||||
|
|
|
|||
|
|
@ -2592,7 +2592,6 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v25
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB3_5
|
||||
; LMULMAX2-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v25, v25, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
|
||||
|
|
@ -2774,7 +2773,6 @@ define void @cttz_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: vmv.x.s a5, v25
|
||||
; LMULMAX1-RV32-NEXT: bnez a5, .LBB3_5
|
||||
; LMULMAX1-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a6
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: addi a5, a1, -1
|
||||
|
|
@ -7655,9 +7653,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a3, a1, 819
|
||||
; LMULMAX2-RV32-NEXT: lui a1, 61681
|
||||
; LMULMAX2-RV32-NEXT: addi a7, a1, -241
|
||||
; LMULMAX2-RV32-NEXT: lui a2, 4112
|
||||
; LMULMAX2-RV32-NEXT: lui a1, 4112
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
|
||||
; LMULMAX2-RV32-NEXT: addi a2, a2, 257
|
||||
; LMULMAX2-RV32-NEXT: addi a2, a1, 257
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_2
|
||||
; LMULMAX2-RV32-NEXT: # %bb.1:
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
|
|
@ -7703,7 +7701,6 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_5
|
||||
; LMULMAX2-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v28, v28, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
|
||||
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
|
||||
|
|
@ -7740,13 +7737,11 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_6:
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 24(sp)
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vslidedown.vi v28, v26, 2
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v28
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_8
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 24(sp)
|
||||
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_8
|
||||
; LMULMAX2-RV32-NEXT: # %bb.7:
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v28, v28, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v28
|
||||
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
|
||||
|
|
@ -7767,9 +7762,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a5, a1, 32
|
||||
; LMULMAX2-RV32-NEXT: j .LBB7_9
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_8:
|
||||
; LMULMAX2-RV32-NEXT: addi a1, a5, -1
|
||||
; LMULMAX2-RV32-NEXT: not a5, a5
|
||||
; LMULMAX2-RV32-NEXT: and a1, a5, a1
|
||||
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
|
||||
; LMULMAX2-RV32-NEXT: not a1, a1
|
||||
; LMULMAX2-RV32-NEXT: and a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: and a5, a5, a4
|
||||
; LMULMAX2-RV32-NEXT: sub a1, a1, a5
|
||||
|
|
@ -7783,13 +7778,11 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: mul a1, a1, a2
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 24
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_9:
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vslidedown.vi v26, v26, 1
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a5, v26
|
||||
; LMULMAX2-RV32-NEXT: bnez a5, .LBB7_11
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX2-RV32-NEXT: sw a5, 16(sp)
|
||||
; LMULMAX2-RV32-NEXT: bnez a1, .LBB7_11
|
||||
; LMULMAX2-RV32-NEXT: # %bb.10:
|
||||
; LMULMAX2-RV32-NEXT: vsetivli a1, 1, e64,m2,ta,mu
|
||||
; LMULMAX2-RV32-NEXT: vsrl.vx v26, v26, a6
|
||||
; LMULMAX2-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
|
||||
|
|
@ -7810,9 +7803,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX2-RV32-NEXT: j .LBB7_12
|
||||
; LMULMAX2-RV32-NEXT: .LBB7_11:
|
||||
; LMULMAX2-RV32-NEXT: addi a1, a5, -1
|
||||
; LMULMAX2-RV32-NEXT: not a5, a5
|
||||
; LMULMAX2-RV32-NEXT: and a1, a5, a1
|
||||
; LMULMAX2-RV32-NEXT: addi a5, a1, -1
|
||||
; LMULMAX2-RV32-NEXT: not a1, a1
|
||||
; LMULMAX2-RV32-NEXT: and a1, a1, a5
|
||||
; LMULMAX2-RV32-NEXT: srli a5, a1, 1
|
||||
; LMULMAX2-RV32-NEXT: and a4, a5, a4
|
||||
; LMULMAX2-RV32-NEXT: sub a1, a1, a4
|
||||
|
|
@ -7978,9 +7971,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a4, a1, 819
|
||||
; LMULMAX1-RV32-NEXT: lui a1, 61681
|
||||
; LMULMAX1-RV32-NEXT: addi t0, a1, -241
|
||||
; LMULMAX1-RV32-NEXT: lui a3, 4112
|
||||
; LMULMAX1-RV32-NEXT: lui a2, 4112
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: addi a3, a3, 257
|
||||
; LMULMAX1-RV32-NEXT: addi a3, a2, 257
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_2
|
||||
; LMULMAX1-RV32-NEXT: # %bb.1:
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
|
|
@ -8026,7 +8019,6 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_5
|
||||
; LMULMAX1-RV32-NEXT: # %bb.4:
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v26, v26, a6
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
|
||||
|
|
@ -8065,12 +8057,10 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: .LBB7_6:
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 24(sp)
|
||||
; LMULMAX1-RV32-NEXT: sw zero, 12(sp)
|
||||
; LMULMAX1-RV32-NEXT: sw zero, 4(sp)
|
||||
; LMULMAX1-RV32-NEXT: vsetvli zero, zero, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: sw zero, 4(sp)
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_8
|
||||
; LMULMAX1-RV32-NEXT: # %bb.7:
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v26, v25, a6
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v26
|
||||
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
|
||||
|
|
@ -8107,13 +8097,11 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: mul a1, a1, a3
|
||||
; LMULMAX1-RV32-NEXT: srli a1, a1, 24
|
||||
; LMULMAX1-RV32-NEXT: .LBB7_9:
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 0(sp)
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vslidedown.vi v25, v25, 1
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: bnez a1, .LBB7_11
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a2, v25
|
||||
; LMULMAX1-RV32-NEXT: sw a1, 0(sp)
|
||||
; LMULMAX1-RV32-NEXT: bnez a2, .LBB7_11
|
||||
; LMULMAX1-RV32-NEXT: # %bb.10:
|
||||
; LMULMAX1-RV32-NEXT: vsetivli a1, 1, e64,m1,ta,mu
|
||||
; LMULMAX1-RV32-NEXT: vsrl.vx v25, v25, a6
|
||||
; LMULMAX1-RV32-NEXT: vmv.x.s a1, v25
|
||||
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
|
||||
|
|
@ -8134,9 +8122,9 @@ define void @cttz_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-RV32-NEXT: addi a1, a1, 32
|
||||
; LMULMAX1-RV32-NEXT: j .LBB7_12
|
||||
; LMULMAX1-RV32-NEXT: .LBB7_11:
|
||||
; LMULMAX1-RV32-NEXT: addi a2, a1, -1
|
||||
; LMULMAX1-RV32-NEXT: not a1, a1
|
||||
; LMULMAX1-RV32-NEXT: and a1, a1, a2
|
||||
; LMULMAX1-RV32-NEXT: addi a1, a2, -1
|
||||
; LMULMAX1-RV32-NEXT: not a2, a2
|
||||
; LMULMAX1-RV32-NEXT: and a1, a2, a1
|
||||
; LMULMAX1-RV32-NEXT: srli a2, a1, 1
|
||||
; LMULMAX1-RV32-NEXT: and a2, a2, a5
|
||||
; LMULMAX1-RV32-NEXT: sub a1, a1, a2
|
||||
|
|
|
|||
|
|
@ -3959,7 +3959,6 @@ define void @extract_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX2-NEXT: vsetivli a2, 4, e64,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vle64.v v26, (a0)
|
||||
; LMULMAX2-NEXT: vle64.v v28, (a1)
|
||||
; LMULMAX2-NEXT: vsetivli a1, 4, e64,m2,ta,mu
|
||||
; LMULMAX2-NEXT: vadd.vv v26, v26, v28
|
||||
; LMULMAX2-NEXT: vse64.v v26, (a0)
|
||||
; LMULMAX2-NEXT: ret
|
||||
|
|
@ -3973,7 +3972,6 @@ define void @extract_v4i64(<4 x i64>* %x, <4 x i64>* %y) {
|
|||
; LMULMAX1-NEXT: vle64.v v27, (a1)
|
||||
; LMULMAX1-NEXT: addi a1, a1, 16
|
||||
; LMULMAX1-NEXT: vle64.v v28, (a1)
|
||||
; LMULMAX1-NEXT: vsetivli a1, 2, e64,m1,ta,mu
|
||||
; LMULMAX1-NEXT: vadd.vv v26, v26, v28
|
||||
; LMULMAX1-NEXT: vadd.vv v25, v25, v27
|
||||
; LMULMAX1-NEXT: vse64.v v25, (a0)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,447 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \
|
||||
; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
|
||||
|
||||
; The following tests check whether inserting VSETVLI avoids inserting
|
||||
; unneeded vsetvlis across basic blocks.
|
||||
|
||||
declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64)
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i64)
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64)
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64)
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double, i64)
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float, i64)
|
||||
|
||||
declare void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>* nocapture, i64)
|
||||
declare void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>* nocapture, i64)
|
||||
|
||||
define <vscale x 1 x double> @test1(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: beqz a1, .LBB0_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.then
|
||||
; CHECK-NEXT: vfadd.vv v8, v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .LBB0_2: # %if.else
|
||||
; CHECK-NEXT: vfsub.vv v8, v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
|
||||
ret <vscale x 1 x double> %c.0
|
||||
}
|
||||
|
||||
@scratch = global i8 0, align 16
|
||||
|
||||
define <vscale x 1 x double> @test2(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: beqz a1, .LBB1_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.then
|
||||
; CHECK-NEXT: vfadd.vv v25, v8, v9
|
||||
; CHECK-NEXT: vfmul.vv v8, v25, v8
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .LBB1_2: # %if.else
|
||||
; CHECK-NEXT: vfsub.vv v25, v8, v9
|
||||
; CHECK-NEXT: vfmul.vv v8, v25, v8
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
|
||||
%3 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %c.0, <vscale x 1 x double> %a, i64 %0)
|
||||
ret <vscale x 1 x double> %3
|
||||
}
|
||||
|
||||
; FIXME: The last vsetvli is redundant, but we need to look through a phi to
|
||||
; prove it.
|
||||
define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: beqz a1, .LBB2_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.then
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vfadd.vv v25, v8, v9
|
||||
; CHECK-NEXT: j .LBB2_3
|
||||
; CHECK-NEXT: .LBB2_2: # %if.else
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vfsub.vv v25, v8, v9
|
||||
; CHECK-NEXT: .LBB2_3: # %if.end
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vfmul.vv v8, v25, v8
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%2 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%3 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%vl.0 = phi i64 [ %0, %if.then], [ %2, %if.else ]
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %3, %if.else ]
|
||||
%4 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %c.0, <vscale x 1 x double> %a, i64 %vl.0)
|
||||
ret <vscale x 1 x double> %4
|
||||
}
|
||||
|
||||
define <vscale x 1 x double> @test4(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %l, <vscale x 1 x double> %r) nounwind {
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: beqz a1, .LBB3_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.then
|
||||
; CHECK-NEXT: lui a1, %hi(.LCPI3_0)
|
||||
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_0)
|
||||
; CHECK-NEXT: vsetvli a2, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vlse64.v v25, (a1), zero
|
||||
; CHECK-NEXT: lui a1, %hi(.LCPI3_1)
|
||||
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_1)
|
||||
; CHECK-NEXT: vlse64.v v26, (a1), zero
|
||||
; CHECK-NEXT: vfadd.vv v25, v25, v26
|
||||
; CHECK-NEXT: lui a1, %hi(scratch)
|
||||
; CHECK-NEXT: addi a1, a1, %lo(scratch)
|
||||
; CHECK-NEXT: vse64.v v25, (a1)
|
||||
; CHECK-NEXT: j .LBB3_3
|
||||
; CHECK-NEXT: .LBB3_2: # %if.else
|
||||
; CHECK-NEXT: lui a1, %hi(.LCPI3_2)
|
||||
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_2)
|
||||
; CHECK-NEXT: vsetvli a2, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vlse32.v v25, (a1), zero
|
||||
; CHECK-NEXT: lui a1, %hi(.LCPI3_3)
|
||||
; CHECK-NEXT: addi a1, a1, %lo(.LCPI3_3)
|
||||
; CHECK-NEXT: vlse32.v v26, (a1), zero
|
||||
; CHECK-NEXT: vfadd.vv v25, v25, v26
|
||||
; CHECK-NEXT: lui a1, %hi(scratch)
|
||||
; CHECK-NEXT: addi a1, a1, %lo(scratch)
|
||||
; CHECK-NEXT: vse32.v v25, (a1)
|
||||
; CHECK-NEXT: .LBB3_3: # %if.end
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vfmul.vv v8, v8, v9
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%0 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 1.000000e+00, i64 %avl)
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 2.000000e+00, i64 %avl)
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %avl)
|
||||
%3 = bitcast i8* @scratch to <vscale x 1 x double>*
|
||||
tail call void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double> %2, <vscale x 1 x double>* %3, i64 %avl)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%4 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 1.000000e+00, i64 %avl)
|
||||
%5 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 2.000000e+00, i64 %avl)
|
||||
%6 = tail call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> %4, <vscale x 2 x float> %5, i64 %avl)
|
||||
%7 = bitcast i8* @scratch to <vscale x 2 x float>*
|
||||
tail call void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float> %6, <vscale x 2 x float>* %7, i64 %avl)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%8 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %l, <vscale x 1 x double> %r, i64 %avl)
|
||||
ret <vscale x 1 x double> %8
|
||||
}
|
||||
|
||||
define <vscale x 1 x double> @test5(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test5:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: andi a2, a1, 1
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: bnez a2, .LBB4_3
|
||||
; CHECK-NEXT: # %bb.1: # %if.else
|
||||
; CHECK-NEXT: vfsub.vv v25, v8, v9
|
||||
; CHECK-NEXT: andi a0, a1, 2
|
||||
; CHECK-NEXT: beqz a0, .LBB4_4
|
||||
; CHECK-NEXT: .LBB4_2: # %if.then4
|
||||
; CHECK-NEXT: vfmul.vv v8, v25, v8
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .LBB4_3: # %if.then
|
||||
; CHECK-NEXT: vfadd.vv v25, v8, v9
|
||||
; CHECK-NEXT: andi a0, a1, 2
|
||||
; CHECK-NEXT: bnez a0, .LBB4_2
|
||||
; CHECK-NEXT: .LBB4_4: # %if.else5
|
||||
; CHECK-NEXT: vfmul.vv v8, v8, v25
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%conv = zext i8 %cond to i32
|
||||
%and = and i32 %conv, 1
|
||||
%tobool = icmp eq i32 %and, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
|
||||
%and2 = and i32 %conv, 2
|
||||
%tobool3 = icmp eq i32 %and2, 0
|
||||
br i1 %tobool3, label %if.else5, label %if.then4
|
||||
|
||||
if.then4: ; preds = %if.end
|
||||
%3 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %c.0, <vscale x 1 x double> %a, i64 %0)
|
||||
br label %if.end6
|
||||
|
||||
if.else5: ; preds = %if.end
|
||||
%4 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %c.0, i64 %0)
|
||||
br label %if.end6
|
||||
|
||||
if.end6: ; preds = %if.else5, %if.then4
|
||||
%c.1 = phi <vscale x 1 x double> [ %3, %if.then4 ], [ %4, %if.else5 ]
|
||||
ret <vscale x 1 x double> %c.1
|
||||
}
|
||||
|
||||
; FIXME: The explicit vsetvli in if.then4 could be removed as it is redundant
|
||||
; with the one in the entry, but we lack the ability to remove explicit
|
||||
; vsetvli instructions.
|
||||
define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: andi a3, a1, 1
|
||||
; CHECK-NEXT: vsetvli a2, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: bnez a3, .LBB5_3
|
||||
; CHECK-NEXT: # %bb.1: # %if.else
|
||||
; CHECK-NEXT: vfsub.vv v25, v8, v9
|
||||
; CHECK-NEXT: andi a1, a1, 2
|
||||
; CHECK-NEXT: beqz a1, .LBB5_4
|
||||
; CHECK-NEXT: .LBB5_2: # %if.then4
|
||||
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
|
||||
; CHECK-NEXT: vlse64.v v26, (a0), zero
|
||||
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1)
|
||||
; CHECK-NEXT: vlse64.v v27, (a0), zero
|
||||
; CHECK-NEXT: vfadd.vv v26, v26, v27
|
||||
; CHECK-NEXT: lui a0, %hi(scratch)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(scratch)
|
||||
; CHECK-NEXT: vse64.v v26, (a0)
|
||||
; CHECK-NEXT: j .LBB5_5
|
||||
; CHECK-NEXT: .LBB5_3: # %if.then
|
||||
; CHECK-NEXT: vfadd.vv v25, v8, v9
|
||||
; CHECK-NEXT: andi a1, a1, 2
|
||||
; CHECK-NEXT: bnez a1, .LBB5_2
|
||||
; CHECK-NEXT: .LBB5_4: # %if.else5
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: lui a0, %hi(.LCPI5_2)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_2)
|
||||
; CHECK-NEXT: vlse32.v v26, (a0), zero
|
||||
; CHECK-NEXT: lui a0, %hi(.LCPI5_3)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_3)
|
||||
; CHECK-NEXT: vlse32.v v27, (a0), zero
|
||||
; CHECK-NEXT: vfadd.vv v26, v26, v27
|
||||
; CHECK-NEXT: lui a0, %hi(scratch)
|
||||
; CHECK-NEXT: addi a0, a0, %lo(scratch)
|
||||
; CHECK-NEXT: vse32.v v26, (a0)
|
||||
; CHECK-NEXT: .LBB5_5: # %if.end10
|
||||
; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vfmul.vv v8, v25, v25
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%conv = zext i8 %cond to i32
|
||||
%and = and i32 %conv, 1
|
||||
%tobool = icmp eq i32 %and, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
|
||||
%and2 = and i32 %conv, 2
|
||||
%tobool3 = icmp eq i32 %and2, 0
|
||||
br i1 %tobool3, label %if.else5, label %if.then4
|
||||
|
||||
if.then4: ; preds = %if.end
|
||||
%3 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%4 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 1.000000e+00, i64 %3)
|
||||
%5 = tail call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(double 2.000000e+00, i64 %3)
|
||||
%6 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %4, <vscale x 1 x double> %5, i64 %3)
|
||||
%7 = bitcast i8* @scratch to <vscale x 1 x double>*
|
||||
tail call void @llvm.riscv.vse.nxv1f64(<vscale x 1 x double> %6, <vscale x 1 x double>* %7, i64 %3)
|
||||
br label %if.end10
|
||||
|
||||
if.else5: ; preds = %if.end
|
||||
%8 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)
|
||||
%9 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 1.000000e+00, i64 %8)
|
||||
%10 = tail call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(float 2.000000e+00, i64 %8)
|
||||
%11 = tail call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(<vscale x 2 x float> %9, <vscale x 2 x float> %10, i64 %8)
|
||||
%12 = bitcast i8* @scratch to <vscale x 2 x float>*
|
||||
tail call void @llvm.riscv.vse.nxv2f32(<vscale x 2 x float> %11, <vscale x 2 x float>* %12, i64 %8)
|
||||
br label %if.end10
|
||||
|
||||
if.end10: ; preds = %if.else5, %if.then4
|
||||
%13 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %c.0, <vscale x 1 x double> %c.0, i64 %0)
|
||||
ret <vscale x 1 x double> %13
|
||||
}
|
||||
|
||||
declare void @foo()
|
||||
|
||||
; Similar to test1, but contains a call to @foo to act as barrier to analyzing
|
||||
; VL/VTYPE.
|
||||
define <vscale x 1 x double> @test8(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test8:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addi sp, sp, -32
|
||||
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
|
||||
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
|
||||
; CHECK-NEXT: csrr a2, vlenb
|
||||
; CHECK-NEXT: slli a2, a2, 1
|
||||
; CHECK-NEXT: sub sp, sp, a2
|
||||
; CHECK-NEXT: vsetvli s0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: beqz a1, .LBB6_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.then
|
||||
; CHECK-NEXT: vfadd.vv v8, v8, v9
|
||||
; CHECK-NEXT: j .LBB6_3
|
||||
; CHECK-NEXT: .LBB6_2: # %if.else
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: add a0, a0, sp
|
||||
; CHECK-NEXT: addi a0, a0, 16
|
||||
; CHECK-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
|
||||
; CHECK-NEXT: addi a0, sp, 16
|
||||
; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
|
||||
; CHECK-NEXT: call foo@plt
|
||||
; CHECK-NEXT: vsetvli a0, s0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: add a0, a0, sp
|
||||
; CHECK-NEXT: addi a0, a0, 16
|
||||
; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
|
||||
; CHECK-NEXT: addi a0, sp, 16
|
||||
; CHECK-NEXT: vl1r.v v26, (a0) # Unknown-size Folded Reload
|
||||
; CHECK-NEXT: vfsub.vv v8, v26, v25
|
||||
; CHECK-NEXT: .LBB6_3: # %if.then
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: slli a0, a0, 1
|
||||
; CHECK-NEXT: add sp, sp, a0
|
||||
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
|
||||
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
|
||||
; CHECK-NEXT: addi sp, sp, 32
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
call void @foo()
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
|
||||
ret <vscale x 1 x double> %c.0
|
||||
}
|
||||
|
||||
; Similar to test2, but contains a call to @foo to act as barrier to analyzing
|
||||
; VL/VTYPE.
|
||||
define <vscale x 1 x double> @test9(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
|
||||
; CHECK-LABEL: test9:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: addi sp, sp, -32
|
||||
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
|
||||
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
|
||||
; CHECK-NEXT: csrr a2, vlenb
|
||||
; CHECK-NEXT: slli a2, a2, 1
|
||||
; CHECK-NEXT: sub sp, sp, a2
|
||||
; CHECK-NEXT: vsetvli s0, a0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: beqz a1, .LBB7_2
|
||||
; CHECK-NEXT: # %bb.1: # %if.then
|
||||
; CHECK-NEXT: vfadd.vv v25, v8, v9
|
||||
; CHECK-NEXT: addi a0, sp, 16
|
||||
; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: add a0, a0, sp
|
||||
; CHECK-NEXT: addi a0, a0, 16
|
||||
; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
|
||||
; CHECK-NEXT: call foo@plt
|
||||
; CHECK-NEXT: addi a0, sp, 16
|
||||
; CHECK-NEXT: vl1r.v v25, (a0) # Unknown-size Folded Reload
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: add a0, a0, sp
|
||||
; CHECK-NEXT: addi a0, a0, 16
|
||||
; CHECK-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
|
||||
; CHECK-NEXT: j .LBB7_3
|
||||
; CHECK-NEXT: .LBB7_2: # %if.else
|
||||
; CHECK-NEXT: vfsub.vv v25, v8, v9
|
||||
; CHECK-NEXT: .LBB7_3: # %if.end
|
||||
; CHECK-NEXT: vsetvli a0, s0, e64,m1,ta,mu
|
||||
; CHECK-NEXT: vfmul.vv v8, v25, v8
|
||||
; CHECK-NEXT: csrr a0, vlenb
|
||||
; CHECK-NEXT: slli a0, a0, 1
|
||||
; CHECK-NEXT: add sp, sp, a0
|
||||
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
|
||||
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
|
||||
; CHECK-NEXT: addi sp, sp, 32
|
||||
; CHECK-NEXT: ret
|
||||
entry:
|
||||
%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
call void @foo()
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%2 = tail call <vscale x 1 x double> @llvm.riscv.vfsub.nxv1f64.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, i64 %0)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c.0 = phi <vscale x 1 x double> [ %1, %if.then ], [ %2, %if.else ]
|
||||
%3 = tail call <vscale x 1 x double> @llvm.riscv.vfmul.nxv1f64.nxv1f64(<vscale x 1 x double> %c.0, <vscale x 1 x double> %a, i64 %0)
|
||||
ret <vscale x 1 x double> %3
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,415 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc %s -o - -mtriple=riscv64 -mattr=experimental-v \
|
||||
# RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s
|
||||
|
||||
--- |
|
||||
; ModuleID = 'vsetvli-insert.ll'
|
||||
source_filename = "vsetvli-insert.ll"
|
||||
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
|
||||
target triple = "riscv64"
|
||||
|
||||
define <vscale x 1 x i64> @load_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64>* %0, <vscale x 1 x i64> %1, i64 %2) #0 {
|
||||
entry:
|
||||
%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* %0, i64 %2)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
|
||||
ret <vscale x 1 x i64> %d
|
||||
}
|
||||
|
||||
define void @load_zext_or_sext(i8 zeroext %cond, <vscale x 1 x i32>* %0, <vscale x 1 x i64>* %1, i64 %2) #0 {
|
||||
entry:
|
||||
%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* %0, i64 %2)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%c = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32> %a, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
|
||||
call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> %d, <vscale x 1 x i64>* %1, i64 %2)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
|
||||
|
||||
define i64 @vmv_x_s(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
|
||||
entry:
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%b = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %1, <vscale x 1 x i64> %1, i64 %2)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%c = phi <vscale x 1 x i64> [ %a, %if.then ], [ %b, %if.else ]
|
||||
%d = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %c)
|
||||
ret i64 %d
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind
|
||||
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #2
|
||||
|
||||
define <vscale x 1 x i64> @vsetvli_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
|
||||
entry:
|
||||
%vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)
|
||||
%tobool = icmp eq i8 %cond, 0
|
||||
br i1 %tobool, label %if.else, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
|
||||
ret <vscale x 1 x i64> %d
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
|
||||
|
||||
; Function Attrs: nounwind readonly
|
||||
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>* nocapture, i64) #3
|
||||
|
||||
; Function Attrs: nounwind readonly
|
||||
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>* nocapture, i64) #3
|
||||
|
||||
; Function Attrs: nounwind writeonly
|
||||
declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i32>, i64) #1
|
||||
|
||||
attributes #0 = { "target-features"="+experimental-v" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
attributes #2 = { nounwind }
|
||||
attributes #3 = { nounwind readonly }
|
||||
attributes #4 = { nounwind writeonly }
|
||||
|
||||
...
|
||||
---
|
||||
name: load_add_or_sub
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vr }
|
||||
- { id: 1, class: vr }
|
||||
- { id: 2, class: vr }
|
||||
- { id: 3, class: vr }
|
||||
- { id: 4, class: gpr }
|
||||
- { id: 5, class: gpr }
|
||||
- { id: 6, class: vr }
|
||||
- { id: 7, class: gpr }
|
||||
- { id: 8, class: gpr }
|
||||
liveins:
|
||||
- { reg: '$x10', virtual-reg: '%4' }
|
||||
- { reg: '$x11', virtual-reg: '%5' }
|
||||
- { reg: '$v8', virtual-reg: '%6' }
|
||||
- { reg: '$x12', virtual-reg: '%7' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: load_add_or_sub
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; CHECK: liveins: $x10, $x11, $v8, $x12
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x12
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vr = COPY $v8
|
||||
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $x11
|
||||
; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY $x10
|
||||
; CHECK: dead %9:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 [[COPY2]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: [[COPY4:%[0-9]+]]:gpr = COPY $x0
|
||||
; CHECK: BEQ [[COPY3]], [[COPY4]], %bb.2
|
||||
; CHECK: PseudoBR %bb.1
|
||||
; CHECK: bb.1.if.then:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: PseudoBR %bb.3
|
||||
; CHECK: bb.2.if.else:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: bb.3.if.end:
|
||||
; CHECK: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
|
||||
; CHECK: $v8 = COPY [[PHI]]
|
||||
; CHECK: PseudoRET implicit $v8
|
||||
bb.0.entry:
|
||||
successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
liveins: $x10, $x11, $v8, $x12
|
||||
|
||||
%7:gpr = COPY $x12
|
||||
%6:vr = COPY $v8
|
||||
%5:gpr = COPY $x11
|
||||
%4:gpr = COPY $x10
|
||||
%0:vr = PseudoVLE64_V_M1 %5, %7, 6
|
||||
%8:gpr = COPY $x0
|
||||
BEQ %4, %8, %bb.2
|
||||
PseudoBR %bb.1
|
||||
|
||||
bb.1.if.then:
|
||||
%1:vr = PseudoVADD_VV_M1 %0, %6, %7, 6
|
||||
PseudoBR %bb.3
|
||||
|
||||
bb.2.if.else:
|
||||
%2:vr = PseudoVSUB_VV_M1 %0, %6, %7, 6
|
||||
|
||||
bb.3.if.end:
|
||||
%3:vr = PHI %1, %bb.1, %2, %bb.2
|
||||
$v8 = COPY %3
|
||||
PseudoRET implicit $v8
|
||||
|
||||
...
|
||||
---
|
||||
name: load_zext_or_sext
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vr }
|
||||
- { id: 1, class: vr }
|
||||
- { id: 2, class: vr }
|
||||
- { id: 3, class: vr }
|
||||
- { id: 4, class: gpr }
|
||||
- { id: 5, class: gpr }
|
||||
- { id: 6, class: gpr }
|
||||
- { id: 7, class: gpr }
|
||||
- { id: 8, class: gpr }
|
||||
liveins:
|
||||
- { reg: '$x10', virtual-reg: '%4' }
|
||||
- { reg: '$x11', virtual-reg: '%5' }
|
||||
- { reg: '$x12', virtual-reg: '%6' }
|
||||
- { reg: '$x13', virtual-reg: '%7' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: load_zext_or_sext
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; CHECK: liveins: $x10, $x11, $x12, $x13
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x13
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $x12
|
||||
; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $x11
|
||||
; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY $x10
|
||||
; CHECK: dead %9:gpr = PseudoVSETVLI [[COPY]], 87, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 [[COPY2]], $noreg, 5, implicit $vl, implicit $vtype
|
||||
; CHECK: [[COPY4:%[0-9]+]]:gpr = COPY $x0
|
||||
; CHECK: BEQ [[COPY3]], [[COPY4]], %bb.2
|
||||
; CHECK: PseudoBR %bb.1
|
||||
; CHECK: bb.1.if.then:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: dead %10:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[PseudoVLE32_V_MF2_]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: PseudoBR %bb.3
|
||||
; CHECK: bb.2.if.else:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: dead %11:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: early-clobber %2:vr = PseudoVSEXT_VF2_M1 [[PseudoVLE32_V_MF2_]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: bb.3.if.end:
|
||||
; CHECK: [[PHI:%[0-9]+]]:vr = PHI %1, %bb.1, %2, %bb.2
|
||||
; CHECK: PseudoVSE64_V_M1 [[PHI]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: PseudoRET
|
||||
bb.0.entry:
|
||||
successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
liveins: $x10, $x11, $x12, $x13
|
||||
|
||||
%7:gpr = COPY $x13
|
||||
%6:gpr = COPY $x12
|
||||
%5:gpr = COPY $x11
|
||||
%4:gpr = COPY $x10
|
||||
%0:vr = PseudoVLE32_V_MF2 %5, %7, 5
|
||||
%8:gpr = COPY $x0
|
||||
BEQ %4, %8, %bb.2
|
||||
PseudoBR %bb.1
|
||||
|
||||
bb.1.if.then:
|
||||
early-clobber %1:vr = PseudoVZEXT_VF2_M1 %0, %7, 6
|
||||
PseudoBR %bb.3
|
||||
|
||||
bb.2.if.else:
|
||||
early-clobber %2:vr = PseudoVSEXT_VF2_M1 %0, %7, 6
|
||||
|
||||
bb.3.if.end:
|
||||
%3:vr = PHI %1, %bb.1, %2, %bb.2
|
||||
PseudoVSE64_V_M1 %3, %6, %7, 6
|
||||
PseudoRET
|
||||
|
||||
...
|
||||
---
|
||||
name: vmv_x_s
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vr }
|
||||
- { id: 1, class: vr }
|
||||
- { id: 2, class: vr }
|
||||
- { id: 3, class: gpr }
|
||||
- { id: 4, class: vr }
|
||||
- { id: 5, class: vr }
|
||||
- { id: 6, class: gpr }
|
||||
- { id: 7, class: gpr }
|
||||
- { id: 8, class: gpr }
|
||||
liveins:
|
||||
- { reg: '$x10', virtual-reg: '%3' }
|
||||
- { reg: '$v8', virtual-reg: '%4' }
|
||||
- { reg: '$v9', virtual-reg: '%5' }
|
||||
- { reg: '$x11', virtual-reg: '%6' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: vmv_x_s
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; CHECK: liveins: $x10, $v8, $v9, $x11
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x11
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vr = COPY $v9
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vr = COPY $v8
|
||||
; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY $x10
|
||||
; CHECK: [[COPY4:%[0-9]+]]:gpr = COPY $x0
|
||||
; CHECK: BEQ [[COPY3]], [[COPY4]], %bb.2
|
||||
; CHECK: PseudoBR %bb.1
|
||||
; CHECK: bb.1.if.then:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: dead %9:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: PseudoBR %bb.3
|
||||
; CHECK: bb.2.if.else:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: dead %10:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY1]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: bb.3.if.end:
|
||||
; CHECK: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
|
||||
; CHECK: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[PHI]], 6, implicit $vtype
|
||||
; CHECK: $x10 = COPY [[PseudoVMV_X_S_M1_]]
|
||||
; CHECK: PseudoRET implicit $x10
|
||||
bb.0.entry:
|
||||
successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
liveins: $x10, $v8, $v9, $x11
|
||||
|
||||
%6:gpr = COPY $x11
|
||||
%5:vr = COPY $v9
|
||||
%4:vr = COPY $v8
|
||||
%3:gpr = COPY $x10
|
||||
%7:gpr = COPY $x0
|
||||
BEQ %3, %7, %bb.2
|
||||
PseudoBR %bb.1
|
||||
|
||||
bb.1.if.then:
|
||||
%0:vr = PseudoVADD_VV_M1 %4, %5, %6, 6
|
||||
PseudoBR %bb.3
|
||||
|
||||
bb.2.if.else:
|
||||
%1:vr = PseudoVSUB_VV_M1 %5, %5, %6, 6
|
||||
|
||||
bb.3.if.end:
|
||||
%2:vr = PHI %0, %bb.1, %1, %bb.2
|
||||
%8:gpr = PseudoVMV_X_S_M1 %2, 6
|
||||
$x10 = COPY %8
|
||||
PseudoRET implicit $x10
|
||||
|
||||
...
|
||||
---
|
||||
name: vsetvli_add_or_sub
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: vr }
|
||||
- { id: 2, class: vr }
|
||||
- { id: 3, class: vr }
|
||||
- { id: 4, class: gpr }
|
||||
- { id: 5, class: vr }
|
||||
- { id: 6, class: vr }
|
||||
- { id: 7, class: gpr }
|
||||
- { id: 8, class: gpr }
|
||||
liveins:
|
||||
- { reg: '$x10', virtual-reg: '%4' }
|
||||
- { reg: '$v8', virtual-reg: '%5' }
|
||||
- { reg: '$v9', virtual-reg: '%6' }
|
||||
- { reg: '$x11', virtual-reg: '%7' }
|
||||
frameInfo:
|
||||
maxAlignment: 1
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: vsetvli_add_or_sub
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
; CHECK: liveins: $x10, $v8, $v9, $x11
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $x11
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vr = COPY $v9
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vr = COPY $v8
|
||||
; CHECK: [[COPY3:%[0-9]+]]:gpr = COPY $x10
|
||||
; CHECK: [[PseudoVSETVLI:%[0-9]+]]:gpr = PseudoVSETVLI [[COPY]], 88, implicit-def $vl, implicit-def $vtype
|
||||
; CHECK: [[COPY4:%[0-9]+]]:gpr = COPY $x0
|
||||
; CHECK: BEQ [[COPY3]], [[COPY4]], %bb.2
|
||||
; CHECK: PseudoBR %bb.1
|
||||
; CHECK: bb.1.if.then:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: PseudoBR %bb.3
|
||||
; CHECK: bb.2.if.else:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6, implicit $vl, implicit $vtype
|
||||
; CHECK: bb.3.if.end:
|
||||
; CHECK: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
|
||||
; CHECK: $v8 = COPY [[PHI]]
|
||||
; CHECK: PseudoRET implicit $v8
|
||||
bb.0.entry:
|
||||
successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
||||
liveins: $x10, $v8, $v9, $x11
|
||||
|
||||
%7:gpr = COPY $x11
|
||||
%6:vr = COPY $v9
|
||||
%5:vr = COPY $v8
|
||||
%4:gpr = COPY $x10
|
||||
%0:gpr = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype
|
||||
%8:gpr = COPY $x0
|
||||
BEQ %4, %8, %bb.2
|
||||
PseudoBR %bb.1
|
||||
|
||||
bb.1.if.then:
|
||||
%1:vr = PseudoVADD_VV_M1 %5, %6, %0, 6
|
||||
PseudoBR %bb.3
|
||||
|
||||
bb.2.if.else:
|
||||
%2:vr = PseudoVSUB_VV_M1 %5, %6, %0, 6
|
||||
|
||||
bb.3.if.end:
|
||||
%3:vr = PHI %1, %bb.1, %2, %bb.2
|
||||
$v8 = COPY %3
|
||||
PseudoRET implicit $v8
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue