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Migrate ARM except for TTI, AsmPrinter, and frame lowering 

away from getSubtargetImpl.

llvm-svn: 227399
This commit is contained in:
Eric Christopher 2015-01-29 00:19:33 +00:00
parent 6f508c578b
commit 1b21f00904
12 changed files with 70 additions and 113 deletions
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11
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -354,10 +354,7 @@ bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
return false;
// We may also need a base pointer if there are dynamic allocas or stack
// pointer adjustments around calls.
if (MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->hasReservedCallFrame(MF))
if (MF.getSubtarget().getFrameLowering()->hasReservedCallFrame(MF))
return true;
// A base pointer is required and allowed. Check that it isn't too late to
// reserve it.
@ -368,10 +365,8 @@ bool ARMBaseRegisterInfo::
needsStackRealignment(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const Function *F = MF.getFunction();
unsigned StackAlign = MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->getStackAlignment();
unsigned StackAlign =
MF.getSubtarget().getFrameLowering()->getStackAlignment();
bool requiresRealignment =
((MFI->getMaxAlignment() > StackAlign) ||
F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,

6
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -383,11 +383,9 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
<< MCP->getConstants().size() << " CP entries, aligned to "
<< MCP->getConstantPoolAlignment() << " bytes *****\n");
TII = (const ARMBaseInstrInfo *)MF->getTarget()
.getSubtargetImpl()
->getInstrInfo();
STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
TII = STI->getInstrInfo();
AFI = MF->getInfo<ARMFunctionInfo>();
STI = &MF->getTarget().getSubtarget<ARMSubtarget>();
isThumb = AFI->isThumbFunction();
isThumb1 = AFI->isThumb1OnlyFunction();

8
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -1345,11 +1345,9 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
}
bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
const TargetMachine &TM = MF.getTarget();
TII = static_cast<const ARMBaseInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
TRI = TM.getSubtargetImpl()->getRegisterInfo();
STI = &TM.getSubtarget<ARMSubtarget>();
STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
AFI = MF.getInfo<ARMFunctionInfo>();
bool Modified = false;

24
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@ -95,9 +95,10 @@ class ARMFastISel final : public FastISel {
: FastISel(funcInfo, libInfo),
M(const_cast<Module &>(*funcInfo.Fn->getParent())),
TM(funcInfo.MF->getTarget()),
TII(*TM.getSubtargetImpl()->getInstrInfo()),
TLI(*TM.getSubtargetImpl()->getTargetLowering()) {
Subtarget = &TM.getSubtarget<ARMSubtarget>();
TII(*funcInfo.MF->getSubtarget().getInstrInfo()),
TLI(*funcInfo.MF->getSubtarget().getTargetLowering()) {
Subtarget =
&static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget());
AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
isThumb2 = AFI->isThumbFunction();
Context = &funcInfo.Fn->getContext();
@ -189,9 +190,7 @@ class ARMFastISel final : public FastISel {
unsigned ARMSelectCallOp(bool UseReg);
unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
const TargetLowering *getTargetLowering() {
return TM.getSubtargetImpl()->getTargetLowering();
}
const TargetLowering *getTargetLowering() { return &TLI; }
// Call handling routines.
private:
@ -2491,8 +2490,7 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
: &ARM::GPRRegClass;
const ARMBaseRegisterInfo *RegInfo =
static_cast<const ARMBaseRegisterInfo *>(
TM.getSubtargetImpl()->getRegisterInfo());
static_cast<const ARMBaseRegisterInfo *>(Subtarget->getRegisterInfo());
unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
unsigned SrcReg = FramePtr;
@ -3065,13 +3063,13 @@ namespace llvm {
FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) {
const TargetMachine &TM = funcInfo.MF->getTarget();
const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
const ARMSubtarget &STI =
static_cast<const ARMSubtarget &>(funcInfo.MF->getSubtarget());
// Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
bool UseFastISel = false;
UseFastISel |= Subtarget->isTargetMachO() && !Subtarget->isThumb1Only();
UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
UseFastISel |= STI.isTargetMachO() && !STI.isThumb1Only();
UseFastISel |= STI.isTargetLinux() && !STI.isThumb();
UseFastISel |= STI.isTargetNaCl() && !STI.isThumb();
if (UseFastISel) {
// iOS always has a FP for backtracking, force other targets

29
llvm/lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -225,7 +225,8 @@ static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI,
DebugLoc DL, const unsigned Reg,
const unsigned Alignment,
const bool MustBeSingleInstruction) {
const ARMSubtarget &AST = MF.getTarget().getSubtarget<ARMSubtarget>();
const ARMSubtarget &AST =
static_cast<const ARMSubtarget &>(MF.getSubtarget());
const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
const unsigned AlignMask = Alignment - 1;
const unsigned NrBitsToZero = countTrailingZeros(Alignment);
@ -282,15 +283,12 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
MCContext &Context = MMI.getContext();
const TargetMachine &TM = MF.getTarget();
const MCRegisterInfo *MRI = Context.getRegisterInfo();
const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
TM.getSubtargetImpl()->getRegisterInfo());
const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
assert(!AFI->isThumb1OnlyFunction() &&
"This emitPrologue does not support Thumb1!");
bool isARM = !AFI->isThumbFunction();
unsigned Align =
TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
unsigned Align = STI.getFrameLowering()->getStackAlignment();
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
unsigned NumBytes = MFI->getStackSize();
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
@ -740,10 +738,7 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
"This emitEpilogue does not support Thumb1!");
bool isARM = !AFI->isThumbFunction();
unsigned Align = MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->getStackAlignment();
unsigned Align = STI.getFrameLowering()->getStackAlignment();
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
int NumBytes = (int)MFI->getStackSize();
unsigned FramePtr = RegInfo->getFrameRegister(MF);
@ -1473,20 +1468,16 @@ static void checkNumAlignedDPRCS2Regs(MachineFunction &MF) {
return;
// We are planning to use NEON instructions vst1 / vld1.
if (!MF.getTarget().getSubtarget<ARMSubtarget>().hasNEON())
if (!static_cast<const ARMSubtarget &>(MF.getSubtarget()).hasNEON())
return;
// Don't bother if the default stack alignment is sufficiently high.
if (MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->getStackAlignment() >= 8)
if (MF.getSubtarget().getFrameLowering()->getStackAlignment() >= 8)
return;
// Aligned spills require stack realignment.
const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
if (!RegInfo->canRealignStack(MF))
if (!static_cast<const ARMBaseRegisterInfo *>(
MF.getSubtarget().getRegisterInfo())->canRealignStack(MF))
return;
// We always spill contiguous d-registers starting from d8. Count how many

5
llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
View File

@ -44,10 +44,9 @@ ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
MachineInstr *DefMI = LastMI;
const MCInstrDesc &LastMCID = LastMI->getDesc();
const TargetMachine &TM =
MI->getParent()->getParent()->getTarget();
const MachineFunction *MF = MI->getParent()->getParent();
const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
MF->getSubtarget().getInstrInfo());
// Skip over one non-VFP / NEON instruction.
if (!LastMI->isBarrier() &&

10
llvm/lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -165,9 +165,10 @@ namespace {
DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
unsigned TempReg =
MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
ARM::t2LDRpci : ARM::LDRcp;
const TargetInstrInfo &TII = *TM->getSubtargetImpl()->getInstrInfo();
const ARMSubtarget &STI =
static_cast<const ARMSubtarget &>(MF.getSubtarget());
unsigned Opc = STI.isThumb2() ? ARM::t2LDRpci : ARM::LDRcp;
const TargetInstrInfo &TII = *STI.getInstrInfo();
MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
TII.get(Opc), TempReg)
.addConstantPoolIndex(Idx);
@ -177,8 +178,7 @@ namespace {
// Fix the GOT address by adding pc.
unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
: ARM::PICADD;
Opc = STI.isThumb2() ? ARM::tPICADD : ARM::PICADD;
MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
.addReg(TempReg)
.addImm(ARMPCLabelIndex);

19
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -567,11 +567,9 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
// MOV NewBase, Base
// ADDS NewBase, #imm8.
if (Base != NewBase && Offset >= 8) {
const ARMSubtarget &Subtarget = MBB.getParent()->getTarget()
.getSubtarget<ARMSubtarget>();
// Need to insert a MOV to the new base first.
if (isARMLowRegister(NewBase) && isARMLowRegister(Base) &&
!Subtarget.hasV6Ops()) {
!STI->hasV6Ops()) {
// thumbv4t doesn't have lo->lo copies, and we can't predicate tMOVSr
if (Pred != ARMCC::AL)
return false;
@ -1798,12 +1796,11 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
}
bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
const TargetMachine &TM = Fn.getTarget();
TL = TM.getSubtargetImpl()->getTargetLowering();
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
TL = STI->getTargetLowering();
AFI = Fn.getInfo<ARMFunctionInfo>();
TII = TM.getSubtargetImpl()->getInstrInfo();
TRI = TM.getSubtargetImpl()->getRegisterInfo();
STI = &TM.getSubtarget<ARMSubtarget>();
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
RS = new RegScavenger();
isThumb2 = AFI->isThumb2Function();
isThumb1 = AFI->isThumbFunction() && !isThumb2;
@ -1813,7 +1810,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
++MFI) {
MachineBasicBlock &MBB = *MFI;
Modified |= LoadStoreMultipleOpti(MBB);
if (TM.getSubtarget<ARMSubtarget>().hasV5TOps())
if (STI->hasV5TOps())
Modified |= MergeReturnIntoLDM(MBB);
}
@ -1862,9 +1859,9 @@ namespace {
bool ARMPreAllocLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
TD = Fn.getTarget().getDataLayout();
TII = Fn.getSubtarget().getInstrInfo();
TRI = Fn.getSubtarget().getRegisterInfo();
STI = &static_cast<const ARMSubtarget &>(Fn.getSubtarget());
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
MRI = &Fn.getRegInfo();
MF = &Fn;

33
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
View File

@ -52,9 +52,9 @@ void Thumb1FrameLowering::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const Thumb1InstrInfo &TII =
*static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo());
const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
const Thumb1RegisterInfo *RegInfo =
static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
if (!hasReservedCallFrame(MF)) {
// If we have alloca, convert as follows:
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
@ -89,15 +89,12 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
MachineModuleInfo &MMI = MF.getMMI();
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
const Thumb1RegisterInfo *RegInfo =
static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
const Thumb1InstrInfo &TII =
*static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo());
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
unsigned Align = MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->getStackAlignment();
unsigned Align = STI.getFrameLowering()->getStackAlignment();
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
unsigned NumBytes = MFI->getStackSize();
assert(NumBytes >= ArgRegsSaveSize &&
@ -331,15 +328,12 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
DebugLoc dl = MBBI->getDebugLoc();
MachineFrameInfo *MFI = MF.getFrameInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
const Thumb1RegisterInfo *RegInfo = static_cast<const Thumb1RegisterInfo *>(
MF.getSubtarget().getRegisterInfo());
const Thumb1RegisterInfo *RegInfo =
static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
const Thumb1InstrInfo &TII =
*static_cast<const Thumb1InstrInfo *>(MF.getSubtarget().getInstrInfo());
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
unsigned Align = MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->getStackAlignment();
unsigned Align = STI.getFrameLowering()->getStackAlignment();
unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize(Align);
int NumBytes = (int)MFI->getStackSize();
assert((unsigned)NumBytes >= ArgRegsSaveSize &&
@ -466,8 +460,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
return false;
DebugLoc DL;
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetInstrInfo &TII = *STI.getInstrInfo();
if (MI != MBB.end()) DL = MI->getDebugLoc();
@ -506,7 +499,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineFunction &MF = *MBB.getParent();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetInstrInfo &TII = *STI.getInstrInfo();
bool isVarArg = AFI->getArgRegsSaveSize() > 0;
DebugLoc DL = MI->getDebugLoc();

22
llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -71,7 +71,7 @@ Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
"Thumb1 does not have ldr to high register");
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
const TargetInstrInfo &TII = *STI.getInstrInfo();
MachineConstantPool *ConstantPool = MF.getConstantPool();
const Constant *C = ConstantInt::get(
Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
@ -388,12 +388,7 @@ rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
int64_t Offset) const {
const ARMBaseInstrInfo &TII =
*static_cast<const ARMBaseInstrInfo *>(MI.getParent()
->getParent()
->getTarget()
.getSubtargetImpl()
->getInstrInfo());
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
int Off = Offset; // ARM doesn't need the general 64-bit offsets
unsigned i = 0;
@ -419,7 +414,7 @@ Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
// off the frame pointer (if, for example, there are alloca() calls in
// the function, the offset will be negative. Use R12 instead since that's
// a call clobbered register that we know won't be used in Thumb1 mode.
const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo();
const TargetInstrInfo &TII = *STI.getInstrInfo();
DebugLoc DL;
AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
.addReg(ARM::R12, RegState::Define)
@ -465,8 +460,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
const ARMBaseInstrInfo &TII =
*static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
DebugLoc dl = MI.getDebugLoc();
MachineInstrBuilder MIB(*MBB.getParent(), &MI);
@ -477,8 +471,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
MF.getFrameInfo()->getStackSize() + SPAdj;
if (MF.getFrameInfo()->hasVarSizedObjects()) {
assert(SPAdj == 0 && MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
"Unexpected");
assert(SPAdj == 0 && STI.getFrameLowering()->hasFP(MF) && "Unexpected");
// There are alloca()'s in this function, must reference off the frame
// pointer or base pointer instead.
if (!hasBasePointer(MF)) {
@ -494,10 +487,7 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// when !hasReservedCallFrame().
#ifndef NDEBUG
if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
assert(MF.getTarget()
.getSubtargetImpl()
->getFrameLowering()
->hasReservedCallFrame(MF) &&
assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
"Cannot use SP to access the emergency spill slot in "
"functions without a reserved call frame");
assert(!MF.getFrameInfo()->hasVarSizedObjects() &&

10
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
View File

@ -253,12 +253,12 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
}
bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
const TargetMachine &TM = Fn.getTarget();
const ARMSubtarget &STI =
static_cast<const ARMSubtarget &>(Fn.getSubtarget());
AFI = Fn.getInfo<ARMFunctionInfo>();
TII = static_cast<const Thumb2InstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
TRI = TM.getSubtargetImpl()->getRegisterInfo();
restrictIT = TM.getSubtarget<ARMSubtarget>().restrictIT();
TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
TRI = STI.getRegisterInfo();
restrictIT = STI.restrictIT();
if (!AFI->isThumbFunction())
return false;

6
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -1001,10 +1001,8 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
}
bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
const TargetMachine &TM = MF.getTarget();
TII = static_cast<const Thumb2InstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
STI = &TM.getSubtarget<ARMSubtarget>();
STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
TII = static_cast<const Thumb2InstrInfo *>(STI->getInstrInfo());
// Optimizing / minimizing size?
AttributeSet FnAttrs = MF.getFunction()->getAttributes();