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[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 

llvm-svn: 191498
This commit is contained in:
Daniel Sanders 2013-09-27 10:08:31 +00:00
parent db4c21f994
commit 1b1e25b7c5
57 changed files with 68 additions and 58 deletions
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5
llvm/lib/Target/Mips/MipsSubtarget.cpp
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@ -89,6 +89,11 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
(hasMips64() && (isABI_N32() || isABI_N64()))) &&
"Invalid Arch & ABI pair.");
if (hasMSA() && !isFP64bit())
report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
"See -mattr=+fp64.",
false);
// Is the target system Linux ?
if (TT.find("linux") == std::string::npos)
IsLinux = false;

2
llvm/test/CodeGen/Mips/msa/2r.ll
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@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 2R instruction format and
; convert scalars to vectors.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fill_b_ARG1 = global i32 23, align 16
@llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/2rf.ll
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@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/2rf_exup.ll
View File

@ -1,7 +1,7 @@
; Test the MSA floating point conversion intrinsics (e.g. float->double) that
; are encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fexupl_w_ARG1 = global <8 x half> <half 0.000000e+00, half 1.000000e+00, half 2.000000e+00, half 3.000000e+00, half 4.000000e+00, half 5.000000e+00, half 6.000000e+00, half 7.000000e+00>, align 16
@llvm_mips_fexupl_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/2rf_float_int.ll
View File

@ -1,7 +1,7 @@
; Test the MSA integer to floating point conversion intrinsics that are encoded
; with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/2rf_fq.ll
View File

@ -1,7 +1,7 @@
; Test the MSA fixed-point to floating point conversion intrinsics that are
; encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ffql_w_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_ffql_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/2rf_int_float.ll
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@ -2,7 +2,7 @@
; 2RF instruction format. This includes conversions but other instructions such
; as fclass are also here.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16

2
llvm/test/CodeGen/Mips/msa/2rf_tq.ll
View File

@ -1,7 +1,7 @@
; Test the MSA floating-point to fixed-point conversion intrinsics that are
; encoded with the 2RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ftq_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_ftq_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16

7
llvm/test/CodeGen/Mips/msa/3r-a.ll
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@ -1,7 +1,12 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'a'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
; It should fail to compile without fp64.
; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \
; RUN: FileCheck -check-prefix=FP32ERROR %s
; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode).
@llvm_mips_add_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_add_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-b.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'b'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-c.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'c'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ceq_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceq_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-d.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'd'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_div_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_div_s_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-i.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'i'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ilvev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ilvev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-m.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'm'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_max_a_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_max_a_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-p.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'p'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_pckev_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_pckev_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-s.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 's'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r-v.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format.
; There are lots of these so this covers those beginning with 'v'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_vshf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_vshf_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r_4r.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format and
; use the result as a third operand.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_maddv_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maddv_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/3r_4r_widen.ll
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@ -2,7 +2,7 @@
; use the result as a third operand and results in wider elements than the
; operands had.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_dpadd_s_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_dpadd_s_h_ARG2 = global <16 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23>, align 16

2
llvm/test/CodeGen/Mips/msa/3r_ld_st.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3R instruction format and
; are loads or stores.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ldx_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ldx_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/3r_splat.ll
View File

@ -1,7 +1,7 @@
; Test the MSA splat intrinsics that are encoded with the 3R instruction
; format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_splat_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf.ll
View File

@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf_4rf.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; use the result as a third operand.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fmadd_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fmadd_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf_4rf_q.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; use the result as a third operand and perform fixed-point operations.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_madd_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_madd_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf_exdo.ll
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@ -1,7 +1,7 @@
; Test the MSA floating-point conversion intrinsics that are encoded with the
; 3RF instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fexdo_h_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexdo_h_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf_float_int.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; take an integer as an operand.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the 3RF instruction format and
; produce an integer as a result.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_fcaf_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
@llvm_mips_fcaf_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16

2
llvm/test/CodeGen/Mips/msa/3rf_q.ll
View File

@ -1,7 +1,7 @@
; Test the MSA fixed-point intrinsics that are encoded with the 3RF instruction
; format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_mul_q_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_mul_q_h_ARG2 = global <8 x i16> <i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, align 16

2
llvm/test/CodeGen/Mips/msa/arithmetic.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: add_v16i8:

2
llvm/test/CodeGen/Mips/msa/arithmetic_float.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: add_v4f32:

2
llvm/test/CodeGen/Mips/msa/basic_operations.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
@v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0>
@v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>

2
llvm/test/CodeGen/Mips/msa/basic_operations_float.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
@v2f64 = global <2 x double> <double 0.0, double 0.0>

2
llvm/test/CodeGen/Mips/msa/bit.ll
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@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the BIT instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_sat_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sat_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

4
llvm/test/CodeGen/Mips/msa/bitcast.ll
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@ -1,7 +1,7 @@
; Test the bitcast operation for big-endian and little-endian.
; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=LITENDIAN %s
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=BIGENDIAN %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=LITENDIAN %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=BIGENDIAN %s
define void @v16i8_to_v16i8(<16 x i8>* %src, <16 x i8>* %dst) nounwind {
entry:

2
llvm/test/CodeGen/Mips/msa/bitwise.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @and_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: and_v16i8:

2
llvm/test/CodeGen/Mips/msa/compare.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @ceq_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: ceq_v16i8:

2
llvm/test/CodeGen/Mips/msa/compare_float.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
declare <4 x float> @llvm.mips.fmax.w(<4 x float>, <4 x float>) nounwind
declare <2 x double> @llvm.mips.fmax.d(<2 x double>, <2 x double>) nounwind

2
llvm/test/CodeGen/Mips/msa/elm_copy.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are element extraction operations.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_copy_s_b_RES = global i32 0, align 16

2
llvm/test/CodeGen/Mips/msa/elm_cxcmsa.ll
View File

@ -1,7 +1,7 @@
; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM
; instruction format).
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define i32 @msa_ir_cfcmsa_test() nounwind {
entry:

2
llvm/test/CodeGen/Mips/msa/elm_insv.ll
View File

@ -1,7 +1,7 @@
; Test the MSA element insertion intrinsics that are encoded with the ELM
; instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_insert_b_ARG3 = global i32 27, align 16

2
llvm/test/CodeGen/Mips/msa/elm_move.ll
View File

@ -1,7 +1,7 @@
; Test the MSA move intrinsics (which are encoded with the ELM instruction
; format).
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/elm_shift_slide.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the ELM instruction format and
; are either shifts or slides.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_sldi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_sldi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i10.ll
View File

@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the I10 instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_bnz_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16

2
llvm/test/CodeGen/Mips/msa/i5-a.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'a'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_addvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_addvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i5-b.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'b'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i5-c.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'c'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ceqi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ceqi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i5-m.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 'm'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_maxi_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_maxi_s_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i5-s.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 's'
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_subvi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_subvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i5_ld_st.ll
View File

@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the I5 instruction format and
; are loads or stores.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_ld_b_ARG = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ld_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/i8.ll
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@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the I8 instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16

2
llvm/test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+MSA < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
; This test originally failed for MSA with a
; `Num < NumOperands && "Invalid child # of SDNode!"' assertion.

2
llvm/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=mips < %s
; RUN: llc -march=mips -mattr=+MSA < %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s
; This test originally failed to select code for a truncstore of a
; build_vector.

2
llvm/test/CodeGen/Mips/msa/shuffle.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @vshf_v16i8_0(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
; CHECK: vshf_v16i8_0:

2
llvm/test/CodeGen/Mips/msa/spill.ll
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@ -1,7 +1,7 @@
; Test that the correct instruction is chosen for spill and reload by trying
; to have 33 live MSA registers simultaneously
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define i32 @test_i8(<16 x i8>* %p0, <16 x i8>* %q1) nounwind {
entry:

4
llvm/test/CodeGen/Mips/msa/vec.ll
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@ -1,7 +1,7 @@
; Test the MSA intrinsics that are encoded with the VEC instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
; RUN: llc -march=mipsel -mattr=+msa < %s | FileCheck -check-prefix=ANYENDIAN %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ANYENDIAN %s
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ANYENDIAN %s
@llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16

2
llvm/test/CodeGen/Mips/msa/vecs10.ll
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@ -1,6 +1,6 @@
; Test the MSA intrinsics that are encoded with the VECS10 instruction format.
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
@llvm_mips_bnz_v_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16