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[Clang/Test]: Rename enable_noundef_analysis to disable-noundef-analysis and turn it off by default 

Turning on `enable_noundef_analysis` flag allows better codegen by removing freeze instructions.
I modified clang by renaming `enable_noundef_analysis` flag to `disable-noundef-analysis` and turning it off by default.

Test updates are made as a separate patch: D108453

Reviewed By: eugenis

Differential Revision: https://reviews.llvm.org/D105169
This commit is contained in:
hyeongyu kim 2022-01-16 18:53:11 +09:00
parent e7c8cd4a93
commit 1b1c8d83d3
1128 changed files with 41216 additions and 41361 deletions
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2
clang/include/clang/Basic/CodeGenOptions.def
View File

@ -64,7 +64,7 @@ CODEGENOPT(DisableLifetimeMarkers, 1, 0) ///< Don't emit any lifetime markers
CODEGENOPT(DisableO0ImplyOptNone , 1, 0) ///< Don't annonate function with optnone at O0
CODEGENOPT(ExperimentalStrictFloatingPoint, 1, 0) ///< Enables the new, experimental
///< strict floating point.
CODEGENOPT(EnableNoundefAttrs, 1, 0) ///< Enable emitting `noundef` attributes on IR call arguments and return values
CODEGENOPT(DisableNoundefAttrs, 1, 0) ///< Disable emitting `noundef` attributes on IR call arguments and return values
CODEGENOPT(LegacyPassManager, 1, 0) ///< Use the legacy pass manager.
CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new
///< pass manager.

7
clang/include/clang/Driver/Options.td
View File

@ -5396,10 +5396,9 @@ defm clear_ast_before_backend : BoolOption<"",
PosFlag<SetTrue, [], "Clear">,
NegFlag<SetFalse, [], "Don't clear">,
BothFlags<[], " the Clang AST before running backend code generation">>;
def enable_noundef_analysis : Flag<["-"], "enable-noundef-analysis">, Group<f_Group>,
HelpText<"Enable analyzing function argument and return types for mandatory definedness">,
MarshallingInfoFlag<CodeGenOpts<"EnableNoundefAttrs">>,
ImpliedByAnyOf<[fsanitize_memory_param_retval.KeyPath]>;
def disable_noundef_analysis : Flag<["-"], "disable-noundef-analysis">, Group<f_Group>,
HelpText<"Disable analyzing function argument and return types for mandatory definedness">,
MarshallingInfoFlag<CodeGenOpts<"DisableNoundefAttrs">>;
def discard_value_names : Flag<["-"], "discard-value-names">,
HelpText<"Discard value names in LLVM IR">,
MarshallingInfoFlag<CodeGenOpts<"DiscardValueNames">>;

4
clang/lib/CodeGen/CGCall.cpp
View File

@ -2243,7 +2243,7 @@ void CodeGenModule::ConstructAttributeList(StringRef Name,
getLangOpts().Sanitize.has(SanitizerKind::Return);
// Determine if the return type could be partially undef
if (CodeGenOpts.EnableNoundefAttrs && HasStrictReturn) {
if (!CodeGenOpts.DisableNoundefAttrs && HasStrictReturn) {
if (!RetTy->isVoidType() && RetAI.getKind() != ABIArgInfo::Indirect &&
DetermineNoUndef(RetTy, getTypes(), DL, RetAI))
RetAttrs.addAttribute(llvm::Attribute::NoUndef);
@ -2377,7 +2377,7 @@ void CodeGenModule::ConstructAttributeList(StringRef Name,
}
// Decide whether the argument we're handling could be partially undef
if (CodeGenOpts.EnableNoundefAttrs &&
if (!CodeGenOpts.DisableNoundefAttrs &&
DetermineNoUndef(ParamType, getTypes(), DL, AI)) {
Attrs.addAttribute(llvm::Attribute::NoUndef);
}

4
clang/test/CXX/except/except.spec/p14-ir.cpp
View File

@ -26,12 +26,12 @@ struct X4 {
struct X5 : X0, X4 { };
void test(X2 x2, X3 x3, X5 x5) {
// CHECK: define linkonce_odr void @_ZN2X2C1ERKS_(%struct.X2* {{[^,]*}} %this, %struct.X2* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr
// CHECK: define linkonce_odr void @_ZN2X2C1ERKS_(%struct.X2* {{[^,]*}} %this, %struct.X2* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr
// CHECK: call void @_ZN2X2C2ERKS_({{.*}}) [[NUW:#[0-9]+]]
// CHECK-NEXT: ret void
// CHECK-NEXT: }
X2 x2a(x2);
// CHECK: define linkonce_odr void @_ZN2X3C1ERKS_(%struct.X3* {{[^,]*}} %this, %struct.X3* nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr
// CHECK: define linkonce_odr void @_ZN2X3C1ERKS_(%struct.X3* {{[^,]*}} %this, %struct.X3* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %0) unnamed_addr
// CHECK: call void @_ZN2X3C2ERKS_({{.*}}) [[NUW]]
// CHECK-NEXT: ret void
// CHECK-NEXT: }

4
clang/test/CXX/expr/expr.prim/expr.prim.lambda/blocks-irgen.mm
View File

@ -13,8 +13,8 @@ namespace PR12746 {
return outer();
}
// CHECK: define internal zeroext i1 @___ZN7PR127462f1EPi_block_invoke
// CHECK: call zeroext i1 @"_ZZZN7PR127462f1EPiEUb_ENK3$_0clEv"
// CHECK: define internal noundef zeroext i1 @___ZN7PR127462f1EPi_block_invoke
// CHECK: call noundef zeroext i1 @"_ZZZN7PR127462f1EPiEUb_ENK3$_0clEv"
bool f2(int *x) {
auto outer = [&]() -> bool {

10
clang/test/CodeGen/2005-01-02-ConstantInits.c
View File

@ -29,21 +29,21 @@ int i = (int) &( ((struct X *)0) -> a[1]);
int Arr[100];
// CHECK-LABEL: define {{[^@]+}}@foo
// CHECK-SAME: (i32 [[I:%.*]]) #[[ATTR0]] {
// CHECK-SAME: (i32 noundef [[I:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[I]], i32* [[I_ADDR]], align 4
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* getelementptr inbounds ([100 x i32], [100 x i32]* @Arr, i64 0, i64 49))
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* noundef getelementptr inbounds ([100 x i32], [100 x i32]* @Arr, i64 0, i64 49))
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[I_ADDR]], align 4
// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP0]] to i64
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], [100 x i32]* @Arr, i64 0, i64 [[IDXPROM]]
// CHECK-NEXT: [[CALL1:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* [[ARRAYIDX]])
// CHECK-NEXT: [[CALL1:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* noundef [[ARRAYIDX]])
// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
// CHECK-NEXT: ret i32 [[ADD]]
//
int foo(int i) { return bar(&Arr[49])+bar(&Arr[i]); }
// CHECK-LABEL: define {{[^@]+}}@foo2
// CHECK-SAME: (i32 [[I:%.*]]) #[[ATTR0]] {
// CHECK-SAME: (i32 noundef [[I:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[I_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[P:%.*]] = alloca i32*, align 8
@ -55,7 +55,7 @@ int foo(int i) { return bar(&Arr[49])+bar(&Arr[i]); }
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[I_ADDR]], align 4
// CHECK-NEXT: [[IDX_EXT:%.*]] = sext i32 [[TMP1]] to i64
// CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @Arr, i64 0, i64 0), i64 [[IDX_EXT]]
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* [[ADD_PTR]])
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i32*, ...) bitcast (i32 (...)* @bar to i32 (i32*, ...)*)(i32* noundef [[ADD_PTR]])
// CHECK-NEXT: ret i32 [[CALL]]
//
int foo2(int i) {

2
clang/test/CodeGen/2006-05-19-SingleEltReturn.c
View File

@ -23,7 +23,7 @@ struct Y bar() {
}
// X86_32: define{{.*}} void @foo(%struct.Y* %P)
// X86_32: define{{.*}} void @foo(%struct.Y* noundef %P)
// X86_32: call void @bar(%struct.Y* sret(%struct.Y) align 4 %{{[^),]*}})
// X86_32: define{{.*}} void @bar(%struct.Y* noalias sret(%struct.Y) align 4 %{{[^,)]*}})

2
clang/test/CodeGen/2007-06-18-SextAttrAggregate.c
View File

@ -1,4 +1,4 @@
// RUN: %clang_cc1 %s -o - -emit-llvm | FileCheck %s
// RUN: %clang_cc1 -disable-noundef-analysis %s -o - -emit-llvm | FileCheck %s
// XFAIL: aarch64, arm64, x86_64-pc-windows-msvc, x86_64-w64-windows-gnu, x86_64-pc-windows-gnu
// PR1513

2
clang/test/CodeGen/2009-02-13-zerosize-union-field.c
View File

@ -1,4 +1,4 @@
// RUN: %clang_cc1 %s -triple i686-apple-darwin -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 %s -disable-noundef-analysis -triple i686-apple-darwin -emit-llvm -o - | FileCheck %s
// Every printf has 'i32 0' for the GEP of the string; no point counting those.
typedef unsigned int Foo __attribute__((aligned(32)));
typedef union{Foo:0;}a;

2
clang/test/CodeGen/2009-05-04-EnumInreg.c
View File

@ -1,4 +1,4 @@
// RUN: %clang_cc1 -emit-llvm -triple i686-apple-darwin -mregparm 3 %s -o - | FileCheck %s
// RUN: %clang_cc1 -disable-noundef-analysis -emit-llvm -triple i686-apple-darwin -mregparm 3 %s -o - | FileCheck %s
// PR3967
enum kobject_action {

8
clang/test/CodeGen/64bit-swiftcall.c
View File

@ -1,7 +1,7 @@
// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=X86-64
// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64
// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -disable-noundef-analysis -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s --check-prefix=X86-64
// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -disable-noundef-analysis -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64
// REQUIRES: aarch64-registered-target,x86-registered-target

2
clang/test/CodeGen/RISCV/riscv-inline-asm.c
View File

@ -40,7 +40,7 @@ void test_f() {
}
void test_A(int *p) {
// CHECK-LABEL: define{{.*}} void @test_A(i32* %p)
// CHECK-LABEL: define{{.*}} void @test_A(i32* noundef %p)
// CHECK: call void asm sideeffect "", "*A"(i32* elementtype(i32) %p)
asm volatile("" :: "A"(*p));
}

8
clang/test/CodeGen/RISCV/riscv32-ilp32-abi.c
View File

@ -25,7 +25,7 @@ struct large {
// Scalars passed on the stack should not have signext/zeroext attributes
// (they are anyext).
// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a, i64 %b, float %c, double %d, fp128 %e, i8 zeroext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 noundef %a, i64 noundef %b, float noundef %c, double noundef %d, fp128 noundef %e, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_1(int32_t a, int64_t b, float c, double d, long double e,
uint8_t f, int8_t g, uint8_t h) {
return g + h;
@ -35,7 +35,7 @@ int f_scalar_stack_1(int32_t a, int64_t b, float c, double d, long double e,
// the presence of large return values that consume a register due to the need
// to pass a pointer.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, float %a, i64 %b, double %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, float noundef %a, i64 noundef %b, double noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
struct large f_scalar_stack_2(float a, int64_t b, double c, long double d,
uint8_t e, int8_t f, uint8_t g) {
return (struct large){a, e, f, g};
@ -44,10 +44,10 @@ struct large f_scalar_stack_2(float a, int64_t b, double c, long double d,
// Aggregates and >=XLen scalars passed on the stack should be lowered just as
// they would be if passed via registers.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, float %g, double %h, fp128 %i)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 noundef %e, i64 noundef %f, float noundef %g, double noundef %h, fp128 noundef %i)
void f_scalar_stack_3(double a, int64_t b, double c, int64_t d, int e,
int64_t f, float g, double h, long double i) {}
// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h)
// CHECK-LABEL: define{{.*}} void @f_agg_stack(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* noundef %h)
void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e,
struct small f, struct small_aligned g, struct large h) {}

8
clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-abi.c
View File

@ -27,7 +27,7 @@ struct large {
// Scalars passed on the stack should not have signext/zeroext attributes
// (they are anyext).
// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a, i64 %b, i32 %c, double %d, fp128 %e, i8 zeroext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 noundef %a, i64 noundef %b, i32 noundef %c, double noundef %d, fp128 noundef %e, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_1(int32_t a, int64_t b, int32_t c, double d, long double e,
uint8_t f, int8_t g, uint8_t h) {
return g + h;
@ -37,7 +37,7 @@ int f_scalar_stack_1(int32_t a, int64_t b, int32_t c, double d, long double e,
// the presence of large return values that consume a register due to the need
// to pass a pointer.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %a, i64 %b, double %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 noundef %a, i64 noundef %b, double noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
struct large f_scalar_stack_2(int32_t a, int64_t b, double c, long double d,
uint8_t e, int8_t f, uint8_t g) {
return (struct large){a, e, f, g};
@ -46,10 +46,10 @@ struct large f_scalar_stack_2(int32_t a, int64_t b, double c, long double d,
// Aggregates and >=XLen scalars passed on the stack should be lowered just as
// they would be if passed via registers.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, i32 %g, double %h, fp128 %i)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 noundef %e, i64 noundef %f, i32 noundef %g, double noundef %h, fp128 noundef %i)
void f_scalar_stack_3(double a, int64_t b, double c, int64_t d, int e,
int64_t f, int32_t g, double h, long double i) {}
// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h)
// CHECK-LABEL: define{{.*}} void @f_agg_stack(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* noundef %h)
void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e,
struct small f, struct small_aligned g, struct large h) {}

48
clang/test/CodeGen/RISCV/riscv32-ilp32-ilp32f-ilp32d-abi.c
View File

@ -18,37 +18,37 @@ void f_void(void) {}
// Scalar arguments and return values smaller than the word size are extended
// according to the sign of their type, up to 32 bits
// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 zeroext %x)
// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 noundef zeroext %x)
_Bool f_scalar_0(_Bool x) { return x; }
// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 signext %x)
// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 noundef signext %x)
int8_t f_scalar_1(int8_t x) { return x; }
// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 zeroext %x)
// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 noundef zeroext %x)
uint8_t f_scalar_2(uint8_t x) { return x; }
// CHECK-LABEL: define{{.*}} i32 @f_scalar_3(i32 %x)
// CHECK-LABEL: define{{.*}} i32 @f_scalar_3(i32 noundef %x)
int32_t f_scalar_3(int32_t x) { return x; }
// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 %x)
// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 noundef %x)
int64_t f_scalar_4(int64_t x) { return x; }
#ifdef __SIZEOF_INT128__
// CHECK-FORCEINT128-LABEL: define{{.*}} i128 @f_scalar_5(i128 %x)
// CHECK-FORCEINT128-LABEL: define{{.*}} i128 @f_scalar_5(i128 noundef %x)
__int128_t f_scalar_5(__int128_t x) { return x; }
#endif
// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float %x)
// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float noundef %x)
float f_fp_scalar_1(float x) { return x; }
// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double %x)
// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double noundef %x)
double f_fp_scalar_2(double x) { return x; }
// Scalars larger than 2*xlen are passed/returned indirect. However, the
// RISC-V LLVM backend can handle this fine, so the function doesn't need to
// be modified.
// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 %x)
// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 noundef %x)
long double f_fp_scalar_3(long double x) { return x; }
// Empty structs or unions are ignored.
@ -88,7 +88,7 @@ struct tiny f_agg_tiny_ret() {
typedef uint8_t v4i8 __attribute__((vector_size(4)));
typedef int32_t v1i32 __attribute__((vector_size(4)));
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i8(i32 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i8(i32 noundef %x.coerce)
void f_vec_tiny_v4i8(v4i8 x) {
x[0] = x[1];
x[2] = x[3];
@ -99,7 +99,7 @@ v4i8 f_vec_tiny_v4i8_ret() {
return (v4i8){1, 2, 3, 4};
}
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i32(i32 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i32(i32 noundef %x.coerce)
void f_vec_tiny_v1i32(v1i32 x) {
x[0] = 114;
}
@ -127,7 +127,7 @@ struct small f_agg_small_ret() {
typedef uint8_t v8i8 __attribute__((vector_size(8)));
typedef int64_t v1i64 __attribute__((vector_size(8)));
// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i8(i64 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i8(i64 noundef %x.coerce)
void f_vec_small_v8i8(v8i8 x) {
x[0] = x[7];
}
@ -137,7 +137,7 @@ v8i8 f_vec_small_v8i8_ret() {
return (v8i8){1, 2, 3, 4, 5, 6, 7, 8};
}
// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i64(i64 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i64(i64 noundef %x.coerce)
void f_vec_small_v1i64(v1i64 x) {
x[0] = 114;
}
@ -170,21 +170,21 @@ struct large {
int32_t a, b, c, d;
};
// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* %x)
// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* noundef %x)
void f_agg_large(struct large x) {
x.a = x.b + x.c + x.d;
}
// The address where the struct should be written to will be the first
// argument
// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %i, i8 signext %j)
// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 noundef %i, i8 noundef signext %j)
struct large f_agg_large_ret(int32_t i, int8_t j) {
return (struct large){1, 2, 3, 4};
}
typedef unsigned char v16i8 __attribute__((vector_size(16)));
// CHECK-LABEL: define{{.*}} void @f_vec_large_v16i8(<16 x i8>* %0)
// CHECK-LABEL: define{{.*}} void @f_vec_large_v16i8(<16 x i8>* noundef %0)
void f_vec_large_v16i8(v16i8 x) {
x[0] = x[7];
}
@ -197,7 +197,7 @@ v16i8 f_vec_large_v16i8_ret() {
// Scalars passed on the stack should not have signext/zeroext attributes
// (they are anyext).
// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a.coerce, [2 x i32] %b.coerce, i64 %c.coerce, %struct.large* %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} i32 @f_scalar_stack_1(i32 %a.coerce, [2 x i32] %b.coerce, i64 %c.coerce, %struct.large* noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c,
struct large d, uint8_t e, int8_t f, uint8_t g, int8_t h) {
return g + h;
@ -207,13 +207,13 @@ int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c,
// the presence of large return values that consume a register due to the need
// to pass a pointer.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 %a, i64 %b, i64 %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 4 %agg.result, i32 noundef %a, i64 noundef %b, i64 noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
struct large f_scalar_stack_2(int32_t a, int64_t b, int64_t c, long double d,
uint8_t e, int8_t f, uint8_t g) {
return (struct large){a, e, f, g};
}
// CHECK-LABEL: define{{.*}} fp128 @f_scalar_stack_4(i32 %a, i64 %b, i64 %c, fp128 %d, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} fp128 @f_scalar_stack_4(i32 noundef %a, i64 noundef %b, i64 noundef %c, fp128 noundef %d, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
long double f_scalar_stack_4(int32_t a, int64_t b, int64_t c, long double d,
uint8_t e, int8_t f, uint8_t g) {
return d;
@ -222,11 +222,11 @@ long double f_scalar_stack_4(int32_t a, int64_t b, int64_t c, long double d,
// Aggregates and >=XLen scalars passed on the stack should be lowered just as
// they would be if passed via registers.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_5(double %a, i64 %b, double %c, i64 %d, i32 %e, i64 %f, float %g, double %h, fp128 %i)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_5(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 noundef %e, i64 noundef %f, float noundef %g, double noundef %h, fp128 noundef %i)
void f_scalar_stack_5(double a, int64_t b, double c, int64_t d, int e,
int64_t f, float g, double h, long double i) {}
// CHECK-LABEL: define{{.*}} void @f_agg_stack(double %a, i64 %b, double %c, i64 %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* %h)
// CHECK-LABEL: define{{.*}} void @f_agg_stack(double noundef %a, i64 noundef %b, double noundef %c, i64 noundef %d, i32 %e.coerce, [2 x i32] %f.coerce, i64 %g.coerce, %struct.large* noundef %h)
void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e,
struct small f, struct small_aligned g, struct large h) {}
@ -237,14 +237,14 @@ void f_agg_stack(double a, int64_t b, double c, int64_t d, struct tiny e,
int f_va_callee(int, ...);
// CHECK-LABEL: define{{.*}} void @f_va_caller()
// CHECK: call i32 (i32, ...) @f_va_callee(i32 1, i32 2, i64 3, double 4.000000e+00, double 5.000000e+00, i32 {{%.*}}, [2 x i32] {{%.*}}, i64 {{%.*}}, %struct.large* {{%.*}})
// CHECK: call i32 (i32, ...) @f_va_callee(i32 noundef 1, i32 noundef 2, i64 noundef 3, double noundef 4.000000e+00, double noundef 5.000000e+00, i32 {{%.*}}, [2 x i32] {{%.*}}, i64 {{%.*}}, %struct.large* noundef {{%.*}})
void f_va_caller() {
f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9},
(struct small){10, NULL}, (struct small_aligned){11},
(struct large){12, 13, 14, 15});
}
// CHECK-LABEL: define{{.*}} i32 @f_va_1(i8* %fmt, ...) {{.*}} {
// CHECK-LABEL: define{{.*}} i32 @f_va_1(i8* noundef %fmt, ...) {{.*}} {
// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4
// CHECK: [[VA:%.*]] = alloca i8*, align 4
// CHECK: [[V:%.*]] = alloca i32, align 4
@ -362,7 +362,7 @@ double f_va_3(char *fmt, ...) {
return v + x;
}
// CHECK-LABEL: define{{.*}} i32 @f_va_4(i8* %fmt, ...) {{.*}} {
// CHECK-LABEL: define{{.*}} i32 @f_va_4(i8* noundef %fmt, ...) {{.*}} {
// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 4
// CHECK-NEXT: [[VA:%.*]] = alloca i8*, align 4
// CHECK-NEXT: [[V:%.*]] = alloca i32, align 4

24
clang/test/CodeGen/RISCV/riscv32-ilp32d-abi.c
View File

@ -9,7 +9,7 @@
// Doubles are passed in FPRs, so argument 'i' will be passed zero-extended
// because it will be passed in a GPR.
// CHECK: define{{.*}} void @f_fpr_tracking(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, i8 zeroext %i)
// CHECK: define{{.*}} void @f_fpr_tracking(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, i8 noundef zeroext %i)
void f_fpr_tracking(double a, double b, double c, double d, double e, double f,
double g, double h, uint8_t i) {}
@ -77,7 +77,7 @@ struct double_float_s f_ret_double_float_s() {
return (struct double_float_s){1.0, 2.0};
}
// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, %struct.double_double_s* %h)
// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, %struct.double_double_s* noundef %h)
void f_double_double_s_arg_insufficient_fprs(float a, double b, double c, double d,
double e, double f, double g, struct double_double_s h) {}
@ -116,7 +116,7 @@ struct double_int32_s f_ret_double_int32_s() {
return (struct double_int32_s){1.0, 2};
}
// CHECK: define{{.*}} void @f_double_int64_s_arg(%struct.double_int64_s* %a)
// CHECK: define{{.*}} void @f_double_int64_s_arg(%struct.double_int64_s* noundef %a)
void f_double_int64_s_arg(struct double_int64_s a) {}
// CHECK: define{{.*}} void @f_ret_double_int64_s(%struct.double_int64_s* noalias sret(%struct.double_int64_s) align 8 %agg.result)
@ -143,18 +143,18 @@ struct double_int8_zbf_s f_ret_double_int8_zbf_s() {
return (struct double_int8_zbf_s){1.0, 2};
}
// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, %struct.double_int8_s* %i)
// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, i32 noundef %h, %struct.double_int8_s* noundef %i)
void f_double_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e,
int f, int g, int h, struct double_int8_s i) {}
// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, %struct.double_int8_s* %i)
// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, %struct.double_int8_s* noundef %i)
void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double d,
double e, double f, double g, double h, struct double_int8_s i) {}
// Complex floating-point values or structs containing a single complex
// floating-point value should be passed as if it were an fp+fp struct.
// CHECK: define{{.*}} void @f_doublecomplex(double %a.coerce0, double %a.coerce1)
// CHECK: define{{.*}} void @f_doublecomplex(double noundef %a.coerce0, double noundef %a.coerce1)
void f_doublecomplex(double __complex__ a) {}
// CHECK: define{{.*}} { double, double } @f_ret_doublecomplex()
@ -240,7 +240,7 @@ struct doublearr2_tricky4_s f_ret_doublearr2_tricky4_s() {
struct int_double_int_s { int a; double b; int c; };
// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* %a)
// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* noundef %a)
void f_int_double_int_s_arg(struct int_double_int_s a) {}
// CHECK: define{{.*}} void @f_ret_int_double_int_s(%struct.int_double_int_s* noalias sret(%struct.int_double_int_s) align 8 %agg.result)
@ -250,7 +250,7 @@ struct int_double_int_s f_ret_int_double_int_s() {
struct int64_double_s { int64_t a; double b; };
// CHECK: define{{.*}} void @f_int64_double_s_arg(%struct.int64_double_s* %a)
// CHECK: define{{.*}} void @f_int64_double_s_arg(%struct.int64_double_s* noundef %a)
void f_int64_double_s_arg(struct int64_double_s a) {}
// CHECK: define{{.*}} void @f_ret_int64_double_s(%struct.int64_double_s* noalias sret(%struct.int64_double_s) align 8 %agg.result)
@ -260,7 +260,7 @@ struct int64_double_s f_ret_int64_double_s() {
struct char_char_double_s { char a; char b; double c; };
// CHECK-LABEL: define{{.*}} void @f_char_char_double_s_arg(%struct.char_char_double_s* %a)
// CHECK-LABEL: define{{.*}} void @f_char_char_double_s_arg(%struct.char_char_double_s* noundef %a)
void f_char_char_double_s_arg(struct char_char_double_s a) {}
// CHECK: define{{.*}} void @f_ret_char_char_double_s(%struct.char_char_double_s* noalias sret(%struct.char_char_double_s) align 8 %agg.result)
@ -287,19 +287,19 @@ union double_u f_ret_double_u() {
// returned in registers). This includes complex doubles, which are treated as
// double+double structs by the ABI.
// CHECK: define{{.*}} { double, i32 } @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double %0, i32 %1)
// CHECK: define{{.*}} { double, i32 } @f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, double %0, i32 %1)
struct double_int32_s f_ret_double_int32_s_double_int32_s_just_sufficient_gprs(
int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) {
return (struct double_int32_s){1.0, 2};
}
// CHECK: define{{.*}} { double, double } @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double %0, i32 %1)
// CHECK: define{{.*}} { double, double } @f_ret_double_double_s_double_int32_s_just_sufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, double %0, i32 %1)
struct double_double_s f_ret_double_double_s_double_int32_s_just_sufficient_gprs(
int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) {
return (struct double_double_s){1.0, 2.0};
}
// CHECK: define{{.*}} { double, double } @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, double %0, i32 %1)
// CHECK: define{{.*}} { double, double } @f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, double %0, i32 %1)
double __complex__ f_ret_doublecomplex_double_int32_s_just_sufficient_gprs(
int a, int b, int c, int d, int e, int f, int g, struct double_int32_s h) {
return 1.0;

6
clang/test/CodeGen/RISCV/riscv32-ilp32f-abi.c
View File

@ -6,7 +6,7 @@
// Doubles are still passed in GPRs, so the 'e' argument will be anyext as
// GPRs are exhausted.
// CHECK: define{{.*}} void @f_fpr_tracking(double %a, double %b, double %c, double %d, i8 %e)
// CHECK: define{{.*}} void @f_fpr_tracking(double noundef %a, double noundef %b, double noundef %c, double noundef %d, i8 noundef %e)
void f_fpr_tracking(double a, double b, double c, double d, int8_t e) {}
// Lowering for doubles is unnmodified, as 64 > FLEN.
@ -23,7 +23,7 @@ struct double_s f_ret_double_s() {
struct double_double_s { double d; double e; };
// CHECK: define{{.*}} void @f_double_double_s_arg(%struct.double_double_s* %a)
// CHECK: define{{.*}} void @f_double_double_s_arg(%struct.double_double_s* noundef %a)
void f_double_double_s_arg(struct double_double_s a) {}
// CHECK: define{{.*}} void @f_ret_double_double_s(%struct.double_double_s* noalias sret(%struct.double_double_s) align 8 %agg.result)
@ -35,7 +35,7 @@ struct double_int8_s { double d; int64_t i; };
struct int_double_s { int a; double b; };
// CHECK: define{{.*}} void @f_int_double_s_arg(%struct.int_double_s* %a)
// CHECK: define{{.*}} void @f_int_double_s_arg(%struct.int_double_s* noundef %a)
void f_int_double_s_arg(struct int_double_s a) {}
// CHECK: define{{.*}} void @f_ret_int_double_s(%struct.int_double_s* noalias sret(%struct.int_double_s) align 8 %agg.result)

16
clang/test/CodeGen/RISCV/riscv32-ilp32f-ilp32d-abi.c
View File

@ -11,7 +11,7 @@
// Floats are passed in FPRs, so argument 'i' will be passed zero-extended
// because it will be passed in a GPR.
// CHECK: define{{.*}} void @f_fpr_tracking(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, i8 zeroext %i)
// CHECK: define{{.*}} void @f_fpr_tracking(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, i8 noundef zeroext %i)
void f_fpr_tracking(float a, float b, float c, float d, float e, float f,
float g, float h, uint8_t i) {}
@ -70,7 +70,7 @@ struct float_float_s f_ret_float_float_s() {
return (struct float_float_s){1.0, 2.0};
}
// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, [2 x i32] %h.coerce)
// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, [2 x i32] %h.coerce)
void f_float_float_s_arg_insufficient_fprs(float a, float b, float c, float d,
float e, float f, float g, struct float_float_s h) {}
@ -109,7 +109,7 @@ struct float_int32_s f_ret_float_int32_s() {
return (struct float_int32_s){1.0, 2};
}
// CHECK: define{{.*}} void @f_float_int64_s_arg(%struct.float_int64_s* %a)
// CHECK: define{{.*}} void @f_float_int64_s_arg(%struct.float_int64_s* noundef %a)
void f_float_int64_s_arg(struct float_int64_s a) {}
// CHECK: define{{.*}} void @f_ret_float_int64_s(%struct.float_int64_s* noalias sret(%struct.float_int64_s) align 8 %agg.result)
@ -136,18 +136,18 @@ struct float_int8_zbf_s f_ret_float_int8_zbf_s() {
return (struct float_int8_zbf_s){1.0, 2};
}
// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, [2 x i32] %i.coerce)
// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, i32 noundef %e, i32 noundef %f, i32 noundef %g, i32 noundef %h, [2 x i32] %i.coerce)
void f_float_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e,
int f, int g, int h, struct float_int8_s i) {}
// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, [2 x i32] %i.coerce)
// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, [2 x i32] %i.coerce)
void f_struct_float_int8_insufficient_fprs(float a, float b, float c, float d,
float e, float f, float g, float h, struct float_int8_s i) {}
// Complex floating-point values or structs containing a single complex
// floating-point value should be passed as if it were an fp+fp struct.
// CHECK: define{{.*}} void @f_floatcomplex(float %a.coerce0, float %a.coerce1)
// CHECK: define{{.*}} void @f_floatcomplex(float noundef %a.coerce0, float noundef %a.coerce1)
void f_floatcomplex(float __complex__ a) {}
// CHECK: define{{.*}} { float, float } @f_ret_floatcomplex()
@ -233,7 +233,7 @@ struct floatarr2_tricky4_s f_ret_floatarr2_tricky4_s() {
struct int_float_int_s { int a; float b; int c; };
// CHECK: define{{.*}} void @f_int_float_int_s_arg(%struct.int_float_int_s* %a)
// CHECK: define{{.*}} void @f_int_float_int_s_arg(%struct.int_float_int_s* noundef %a)
void f_int_float_int_s_arg(struct int_float_int_s a) {}
// CHECK: define{{.*}} void @f_ret_int_float_int_s(%struct.int_float_int_s* noalias sret(%struct.int_float_int_s) align 4 %agg.result)
@ -243,7 +243,7 @@ struct int_float_int_s f_ret_int_float_int_s() {
struct int64_float_s { int64_t a; float b; };
// CHECK: define{{.*}} void @f_int64_float_s_arg(%struct.int64_float_s* %a)
// CHECK: define{{.*}} void @f_int64_float_s_arg(%struct.int64_float_s* noundef %a)
void f_int64_float_s_arg(struct int64_float_s a) {}
// CHECK: define{{.*}} void @f_ret_int64_float_s(%struct.int64_float_s* noalias sret(%struct.int64_float_s) align 8 %agg.result)

6
clang/test/CodeGen/RISCV/riscv64-lp64-abi.c
View File

@ -15,7 +15,7 @@ typedef unsigned char v32i8 __attribute__((vector_size(32)));
// Scalars passed on the stack should not have signext/zeroext attributes
// (they are anyext).
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 signext %a, i128 %b, float %c, fp128 %d, <32 x i8>* %0, i8 zeroext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 noundef signext %a, i128 noundef %b, float noundef %c, fp128 noundef %d, <32 x i8>* noundef %0, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_1(int32_t a, __int128_t b, float c, long double d, v32i8 e,
uint8_t f, int8_t g, uint8_t h) {
return g + h;
@ -25,7 +25,7 @@ int f_scalar_stack_1(int32_t a, __int128_t b, float c, long double d, v32i8 e,
// the presence of large return values that consume a register due to the need
// to pass a pointer.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double %a, i128 %b, fp128 %c, <32 x i8>* %0, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double noundef %a, i128 noundef %b, fp128 noundef %c, <32 x i8>* noundef %0, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
struct large f_scalar_stack_2(double a, __int128_t b, long double c, v32i8 d,
uint8_t e, int8_t f, uint8_t g) {
return (struct large){a, e, f, g};
@ -34,7 +34,7 @@ struct large f_scalar_stack_2(double a, __int128_t b, long double c, v32i8 d,
// Complex floating-point values or structs containing a single complex
// floating-point value should be passed in a GPR.
// CHECK: define{{.*}} void @f_floatcomplex(i64 %a.coerce)
// CHECK: define{{.*}} void @f_floatcomplex(i64 noundef %a.coerce)
void f_floatcomplex(float __complex__ a) {}
// CHECK: define{{.*}} i64 @f_ret_floatcomplex()

4
clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-abi.c
View File

@ -17,7 +17,7 @@ typedef unsigned char v32i8 __attribute__((vector_size(32)));
// Scalars passed on the stack should not have signext/zeroext attributes
// (they are anyext).
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 signext %a, i128 %b, double %c, fp128 %d, <32 x i8>* %0, i8 zeroext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i32 noundef signext %a, i128 noundef %b, double noundef %c, fp128 noundef %d, <32 x i8>* noundef %0, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_1(int32_t a, __int128_t b, double c, long double d, v32i8 e,
uint8_t f, int8_t g, uint8_t h) {
return g + h;
@ -27,7 +27,7 @@ int f_scalar_stack_1(int32_t a, __int128_t b, double c, long double d, v32i8 e,
// the presence of large return values that consume a register due to the need
// to pass a pointer.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double %a, i128 %b, fp128 %c, <32 x i8>* %0, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_2(%struct.large* noalias sret(%struct.large) align 8 %agg.result, double noundef %a, i128 noundef %b, fp128 noundef %c, <32 x i8>* noundef %0, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
struct large f_scalar_stack_2(double a, __int128_t b, long double c, v32i8 d,
uint8_t e, int8_t f, uint8_t g) {
return (struct large){a, e, f, g};

58
clang/test/CodeGen/RISCV/riscv64-lp64-lp64f-lp64d-abi.c
View File

@ -16,28 +16,28 @@ void f_void(void) {}
// Scalar arguments and return values smaller than the word size are extended
// according to the sign of their type, up to 32 bits
// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 zeroext %x)
// CHECK-LABEL: define{{.*}} zeroext i1 @f_scalar_0(i1 noundef zeroext %x)
_Bool f_scalar_0(_Bool x) { return x; }
// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 signext %x)
// CHECK-LABEL: define{{.*}} signext i8 @f_scalar_1(i8 noundef signext %x)
int8_t f_scalar_1(int8_t x) { return x; }
// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 zeroext %x)
// CHECK-LABEL: define{{.*}} zeroext i8 @f_scalar_2(i8 noundef zeroext %x)
uint8_t f_scalar_2(uint8_t x) { return x; }
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_3(i32 signext %x)
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_3(i32 noundef signext %x)
uint32_t f_scalar_3(int32_t x) { return x; }
// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 %x)
// CHECK-LABEL: define{{.*}} i64 @f_scalar_4(i64 noundef %x)
int64_t f_scalar_4(int64_t x) { return x; }
// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float %x)
// CHECK-LABEL: define{{.*}} float @f_fp_scalar_1(float noundef %x)
float f_fp_scalar_1(float x) { return x; }
// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double %x)
// CHECK-LABEL: define{{.*}} double @f_fp_scalar_2(double noundef %x)
double f_fp_scalar_2(double x) { return x; }
// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 %x)
// CHECK-LABEL: define{{.*}} fp128 @f_fp_scalar_3(fp128 noundef %x)
long double f_fp_scalar_3(long double x) { return x; }
// Empty structs or unions are ignored.
@ -77,7 +77,7 @@ struct tiny f_agg_tiny_ret() {
typedef uint16_t v4i16 __attribute__((vector_size(8)));
typedef int64_t v1i64 __attribute__((vector_size(8)));
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i16(i64 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v4i16(i64 noundef %x.coerce)
void f_vec_tiny_v4i16(v4i16 x) {
x[0] = x[1];
x[2] = x[3];
@ -88,7 +88,7 @@ v4i16 f_vec_tiny_v4i16_ret() {
return (v4i16){1, 2, 3, 4};
}
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i64(i64 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_tiny_v1i64(i64 noundef %x.coerce)
void f_vec_tiny_v1i64(v1i64 x) {
x[0] = 114;
}
@ -116,7 +116,7 @@ struct small f_agg_small_ret() {
typedef uint16_t v8i16 __attribute__((vector_size(16)));
typedef __int128_t v1i128 __attribute__((vector_size(16)));
// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i16(i128 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_small_v8i16(i128 noundef %x.coerce)
void f_vec_small_v8i16(v8i16 x) {
x[0] = x[7];
}
@ -126,7 +126,7 @@ v8i16 f_vec_small_v8i16_ret() {
return (v8i16){1, 2, 3, 4, 5, 6, 7, 8};
}
// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i128(i128 %x.coerce)
// CHECK-LABEL: define{{.*}} void @f_vec_small_v1i128(i128 noundef %x.coerce)
void f_vec_small_v1i128(v1i128 x) {
x[0] = 114;
}
@ -159,21 +159,21 @@ struct large {
int64_t a, b, c, d;
};
// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* %x)
// CHECK-LABEL: define{{.*}} void @f_agg_large(%struct.large* noundef %x)
void f_agg_large(struct large x) {
x.a = x.b + x.c + x.d;
}
// The address where the struct should be written to will be the first
// argument
// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 signext %i, i8 signext %j)
// CHECK-LABEL: define{{.*}} void @f_agg_large_ret(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 noundef signext %i, i8 noundef signext %j)
struct large f_agg_large_ret(int32_t i, int8_t j) {
return (struct large){1, 2, 3, 4};
}
typedef unsigned char v32i8 __attribute__((vector_size(32)));
// CHECK-LABEL: define{{.*}} void @f_vec_large_v32i8(<32 x i8>* %0)
// CHECK-LABEL: define{{.*}} void @f_vec_large_v32i8(<32 x i8>* noundef %0)
void f_vec_large_v32i8(v32i8 x) {
x[0] = x[7];
}
@ -186,13 +186,13 @@ v32i8 f_vec_large_v32i8_ret() {
// Scalars passed on the stack should not have signext/zeroext attributes
// (they are anyext).
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i64 %a.coerce, [2 x i64] %b.coerce, i128 %c.coerce, %struct.large* %d, i8 zeroext %e, i8 signext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_1(i64 %a.coerce, [2 x i64] %b.coerce, i128 %c.coerce, %struct.large* noundef %d, i8 noundef zeroext %e, i8 noundef signext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_1(struct tiny a, struct small b, struct small_aligned c,
struct large d, uint8_t e, int8_t f, uint8_t g, int8_t h) {
return g + h;
}
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_2(i32 signext %a, i128 %b, i64 %c, fp128 %d, <32 x i8>* %0, i8 zeroext %f, i8 %g, i8 %h)
// CHECK-LABEL: define{{.*}} signext i32 @f_scalar_stack_2(i32 noundef signext %a, i128 noundef %b, i64 noundef %c, fp128 noundef %d, <32 x i8>* noundef %0, i8 noundef zeroext %f, i8 noundef %g, i8 noundef %h)
int f_scalar_stack_2(int32_t a, __int128_t b, int64_t c, long double d, v32i8 e,
uint8_t f, int8_t g, uint8_t h) {
return g + h;
@ -202,7 +202,7 @@ int f_scalar_stack_2(int32_t a, __int128_t b, int64_t c, long double d, v32i8 e,
// the presence of large return values that consume a register due to the need
// to pass a pointer.
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 signext %a, i128 %b, fp128 %c, <32 x i8>* %0, i8 zeroext %e, i8 %f, i8 %g)
// CHECK-LABEL: define{{.*}} void @f_scalar_stack_3(%struct.large* noalias sret(%struct.large) align 8 %agg.result, i32 noundef signext %a, i128 noundef %b, fp128 noundef %c, <32 x i8>* noundef %0, i8 noundef zeroext %e, i8 noundef %f, i8 noundef %g)
struct large f_scalar_stack_3(uint32_t a, __int128_t b, long double c, v32i8 d,
uint8_t e, int8_t f, uint8_t g) {
return (struct large){a, e, f, g};
@ -217,31 +217,31 @@ int f_va_callee(int, ...);
// CHECK-LABEL: define{{.*}} void @f_va_caller()
void f_va_caller() {
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i64 3, double 4.000000e+00, double 5.000000e+00, i64 {{%.*}}, [2 x i64] {{%.*}}, i128 {{%.*}}, %struct.large* {{%.*}})
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i64 noundef 3, double noundef 4.000000e+00, double noundef 5.000000e+00, i64 {{%.*}}, [2 x i64] {{%.*}}, i128 {{%.*}}, %struct.large* noundef {{%.*}})
f_va_callee(1, 2, 3LL, 4.0f, 5.0, (struct tiny){6, 7, 8, 9},
(struct small){10, NULL}, (struct small_aligned){11},
(struct large){12, 13, 14, 15});
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, fp128 0xL00000000000000004001400000000000, i32 signext 6, i32 signext 7, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, fp128 noundef 0xL00000000000000004001400000000000, i32 noundef signext 6, i32 noundef signext 7, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5.0L, 6, 7, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i128 {{%.*}}, i32 signext 6, i32 signext 7, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i128 {{%.*}}, i32 noundef signext 6, i32 noundef signext 7, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, (struct small_aligned){5}, 6, 7, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, [2 x i64] {{%.*}}, i32 signext 6, i32 signext 7, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, [2 x i64] {{%.*}}, i32 noundef signext 6, i32 noundef signext 7, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, (struct small){5, NULL}, 6, 7, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, fp128 0xL00000000000000004001800000000000, i32 7, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, fp128 noundef 0xL00000000000000004001800000000000, i32 noundef 7, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5, 6.0L, 7, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i128 {{%.*}}, i32 7, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i128 {{%.*}}, i32 noundef 7, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5, (struct small_aligned){6}, 7, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, [2 x i64] {{%.*}}, i32 signext 7, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, [2 x i64] {{%.*}}, i32 noundef signext 7, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5, (struct small){6, NULL}, 7, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, fp128 0xL00000000000000004001C00000000000, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, fp128 noundef 0xL00000000000000004001C00000000000, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5, 6, 7.0L, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, i128 {{%.*}}, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, i128 {{%.*}}, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5, 6, (struct small_aligned){7}, 8, 9);
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 signext 1, i32 signext 2, i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6, [2 x i64] {{.*}}, i32 8, i32 9)
// CHECK: call signext i32 (i32, ...) @f_va_callee(i32 noundef signext 1, i32 noundef signext 2, i32 noundef signext 3, i32 noundef signext 4, i32 noundef signext 5, i32 noundef signext 6, [2 x i64] {{.*}}, i32 noundef 8, i32 noundef 9)
f_va_callee(1, 2, 3, 4, 5, 6, (struct small){7, NULL}, 8, 9);
}
// CHECK-LABEL: define{{.*}} signext i32 @f_va_1(i8* %fmt, ...) {{.*}} {
// CHECK-LABEL: define{{.*}} signext i32 @f_va_1(i8* noundef %fmt, ...) {{.*}} {
// CHECK: [[FMT_ADDR:%.*]] = alloca i8*, align 8
// CHECK: [[VA:%.*]] = alloca i8*, align 8
// CHECK: [[V:%.*]] = alloca i32, align 4

12
clang/test/CodeGen/RISCV/riscv64-lp64d-abi.c
View File

@ -9,7 +9,7 @@
// Doubles are passed in FPRs, so argument 'i' will be passed zero-extended
// because it will be passed in a GPR.
// CHECK: define{{.*}} void @f_fpr_tracking(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, i8 zeroext %i)
// CHECK: define{{.*}} void @f_fpr_tracking(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, i8 noundef zeroext %i)
void f_fpr_tracking(double a, double b, double c, double d, double e, double f,
double g, double h, uint8_t i) {}
@ -77,7 +77,7 @@ struct double_float_s f_ret_double_float_s() {
return (struct double_float_s){1.0, 2.0};
}
// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, [2 x i64] %h.coerce)
// CHECK: define{{.*}} void @f_double_double_s_arg_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, [2 x i64] %h.coerce)
void f_double_double_s_arg_insufficient_fprs(float a, double b, double c, double d,
double e, double f, double g, struct double_double_s h) {}
@ -143,18 +143,18 @@ struct double_int8_zbf_s f_ret_double_int8_zbf_s() {
return (struct double_int8_zbf_s){1.0, 2};
}
// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h, [2 x i64] %i.coerce)
// CHECK: define{{.*}} void @f_double_int8_s_arg_insufficient_gprs(i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %c, i32 noundef signext %d, i32 noundef signext %e, i32 noundef signext %f, i32 noundef signext %g, i32 noundef signext %h, [2 x i64] %i.coerce)
void f_double_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e,
int f, int g, int h, struct double_int8_s i) {}
// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, [2 x i64] %i.coerce)
// CHECK: define{{.*}} void @f_struct_double_int8_insufficient_fprs(float noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, [2 x i64] %i.coerce)
void f_struct_double_int8_insufficient_fprs(float a, double b, double c, double d,
double e, double f, double g, double h, struct double_int8_s i) {}
// Complex floating-point values or structs containing a single complex
// floating-point value should be passed as if it were an fp+fp struct.
// CHECK: define{{.*}} void @f_doublecomplex(double %a.coerce0, double %a.coerce1)
// CHECK: define{{.*}} void @f_doublecomplex(double noundef %a.coerce0, double noundef %a.coerce1)
void f_doublecomplex(double __complex__ a) {}
// CHECK: define{{.*}} { double, double } @f_ret_doublecomplex()
@ -240,7 +240,7 @@ struct doublearr2_tricky4_s f_ret_doublearr2_tricky4_s() {
struct int_double_int_s { int a; double b; int c; };
// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* %a)
// CHECK: define{{.*}} void @f_int_double_int_s_arg(%struct.int_double_int_s* noundef %a)
void f_int_double_int_s_arg(struct int_double_int_s a) {}
// CHECK: define{{.*}} void @f_ret_int_double_int_s(%struct.int_double_int_s* noalias sret(%struct.int_double_int_s) align 8 %agg.result)

16
clang/test/CodeGen/RISCV/riscv64-lp64f-lp64d-abi.c
View File

@ -11,7 +11,7 @@
// Floats are passed in FPRs, so argument 'i' will be passed zero-extended
// because it will be passed in a GPR.
// CHECK: define{{.*}} void @f_fpr_tracking(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, i8 zeroext %i)
// CHECK: define{{.*}} void @f_fpr_tracking(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, i8 noundef zeroext %i)
void f_fpr_tracking(float a, float b, float c, float d, float e, float f,
float g, float h, uint8_t i) {}
@ -70,7 +70,7 @@ struct float_float_s f_ret_float_float_s() {
return (struct float_float_s){1.0, 2.0};
}
// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, i64 %h.coerce)
// CHECK: define{{.*}} void @f_float_float_s_arg_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, i64 %h.coerce)
void f_float_float_s_arg_insufficient_fprs(float a, float b, float c, float d,
float e, float f, float g, struct float_float_s h) {}
@ -136,18 +136,18 @@ struct float_int8_zbf_s f_ret_float_int8_zbf_s() {
return (struct float_int8_zbf_s){1.0, 2};
}
// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h, i64 %i.coerce)
// CHECK: define{{.*}} void @f_float_int8_s_arg_insufficient_gprs(i32 noundef signext %a, i32 noundef signext %b, i32 noundef signext %c, i32 noundef signext %d, i32 noundef signext %e, i32 noundef signext %f, i32 noundef signext %g, i32 noundef signext %h, i64 %i.coerce)
void f_float_int8_s_arg_insufficient_gprs(int a, int b, int c, int d, int e,
int f, int g, int h, struct float_int8_s i) {}
// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, i64 %i.coerce)
// CHECK: define{{.*}} void @f_struct_float_int8_insufficient_fprs(float noundef %a, float noundef %b, float noundef %c, float noundef %d, float noundef %e, float noundef %f, float noundef %g, float noundef %h, i64 %i.coerce)
void f_struct_float_int8_insufficient_fprs(float a, float b, float c, float d,
float e, float f, float g, float h, struct float_int8_s i) {}
// Complex floating-point values or structs containing a single complex
// floating-point value should be passed as if it were an fp+fp struct.
// CHECK: define{{.*}} void @f_floatcomplex(float %a.coerce0, float %a.coerce1)
// CHECK: define{{.*}} void @f_floatcomplex(float noundef %a.coerce0, float noundef %a.coerce1)
void f_floatcomplex(float __complex__ a) {}
// CHECK: define{{.*}} { float, float } @f_ret_floatcomplex()
@ -168,7 +168,7 @@ struct floatcomplex_s f_ret_floatcomplex_s() {
// Complex floating-point values or structs containing a single complex
// floating-point value should be passed in GPRs if no two FPRs is available.
// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs1(float %a.coerce0, float %a.coerce1, float %b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce)
// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs1(float noundef %a.coerce0, float noundef %a.coerce1, float noundef %b.coerce0, float noundef %b.coerce1, float noundef %c.coerce0, float noundef %c.coerce1, float noundef %d.coerce0, float noundef %d.coerce1, i64 noundef %e.coerce)
void f_floatcomplex_insufficient_fprs1(float __complex__ a, float __complex__ b,
float __complex__ c, float __complex__ d,
float __complex__ e) {}
@ -181,13 +181,13 @@ void f_floatcomplex_s_arg_insufficient_fprs1(struct floatcomplex_s a,
struct floatcomplex_s d,
struct floatcomplex_s e) {}
// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs2(float %a, float %b.coerce0, float %b.coerce1, float %c.coerce0, float %c.coerce1, float %d.coerce0, float %d.coerce1, i64 %e.coerce)
// CHECK: define{{.*}} void @f_floatcomplex_insufficient_fprs2(float noundef %a, float noundef %b.coerce0, float noundef %b.coerce1, float noundef %c.coerce0, float noundef %c.coerce1, float noundef %d.coerce0, float noundef %d.coerce1, i64 noundef %e.coerce)
void f_floatcomplex_insufficient_fprs2(float a,
float __complex__ b, float __complex__ c,
float __complex__ d, float __complex__ e) {}
// CHECK: define{{.*}} void @f_floatcomplex_s_arg_insufficient_fprs2(float %a, float %0, float %1, float %2, float %3, float %4, float %5, i64 %e.coerce)
// CHECK: define{{.*}} void @f_floatcomplex_s_arg_insufficient_fprs2(float noundef %a, float %0, float %1, float %2, float %3, float %4, float %5, i64 %e.coerce)
void f_floatcomplex_s_arg_insufficient_fprs2(float a,
struct floatcomplex_s b,
struct floatcomplex_s c,

18
clang/test/CodeGen/SystemZ/systemz-abi-vector.c
View File

@ -1,20 +1,20 @@
// RUN: %clang_cc1 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu \
// RUN: -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-feature +vector \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-feature +vector \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z13 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch11 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch11 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z14 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z14 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch12 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch12 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z15 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z15 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch13 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch13 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
// Vector types

22
clang/test/CodeGen/SystemZ/systemz-abi.c
View File

@ -1,25 +1,25 @@
// RUN: %clang_cc1 -triple s390x-linux-gnu \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-feature +vector \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-feature +vector \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z13 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch11 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch11 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z14 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z14 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch12 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch12 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z15 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu z15 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch13 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch13 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch13 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch13 \
// RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \
// RUN: --check-prefixes=CHECK,SOFT-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
// RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: %clang_cc1 -disable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
// RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \
// RUN: --check-prefixes=CHECK,SOFT-FLOAT

24
clang/test/CodeGen/SystemZ/systemz-inline-asm.c
View File

@ -5,31 +5,31 @@ unsigned long gl;
void test_store_m(unsigned int i) {
asm("st %1, %0" : "=m" (gi) : "r" (i));
// CHECK-LABEL: define{{.*}} void @test_store_m(i32 zeroext %i)
// CHECK-LABEL: define{{.*}} void @test_store_m(i32 noundef zeroext %i)
// CHECK: call void asm "st $1, $0", "=*m,r"(i32* nonnull elementtype(i32) @gi, i32 %i)
}
void test_store_Q(unsigned int i) {
asm("st %1, %0" : "=Q" (gi) : "r" (i));
// CHECK-LABEL: define{{.*}} void @test_store_Q(i32 zeroext %i)
// CHECK-LABEL: define{{.*}} void @test_store_Q(i32 noundef zeroext %i)
// CHECK: call void asm "st $1, $0", "=*Q,r"(i32* nonnull elementtype(i32) @gi, i32 %i)
}
void test_store_R(unsigned int i) {
asm("st %1, %0" : "=R" (gi) : "r" (i));
// CHECK-LABEL: define{{.*}} void @test_store_R(i32 zeroext %i)
// CHECK-LABEL: define{{.*}} void @test_store_R(i32 noundef zeroext %i)
// CHECK: call void asm "st $1, $0", "=*R,r"(i32* nonnull elementtype(i32) @gi, i32 %i)
}
void test_store_S(unsigned int i) {
asm("st %1, %0" : "=S" (gi) : "r" (i));
// CHECK-LABEL: define{{.*}} void @test_store_S(i32 zeroext %i)
// CHECK-LABEL: define{{.*}} void @test_store_S(i32 noundef zeroext %i)
// CHECK: call void asm "st $1, $0", "=*S,r"(i32* nonnull elementtype(i32) @gi, i32 %i)
}
void test_store_T(unsigned int i) {
asm("st %1, %0" : "=T" (gi) : "r" (i));
// CHECK-LABEL: define{{.*}} void @test_store_T(i32 zeroext %i)
// CHECK-LABEL: define{{.*}} void @test_store_T(i32 noundef zeroext %i)
// CHECK: call void asm "st $1, $0", "=*T,r"(i32* nonnull elementtype(i32) @gi, i32 %i)
}
@ -75,28 +75,28 @@ int test_load_T() {
void test_mI(unsigned char *c) {
asm volatile("cli %0, %1" :: "Q" (*c), "I" (100));
// CHECK-LABEL: define{{.*}} void @test_mI(i8* %c)
// CHECK-LABEL: define{{.*}} void @test_mI(i8* noundef %c)
// CHECK: call void asm sideeffect "cli $0, $1", "*Q,I"(i8* elementtype(i8) %c, i32 100)
}
unsigned int test_dJa(unsigned int i, unsigned int j) {
asm("sll %0, %2(%3)" : "=d" (i) : "0" (i), "J" (1000), "a" (j));
return i;
// CHECK-LABEL: define{{.*}} zeroext i32 @test_dJa(i32 zeroext %i, i32 zeroext %j)
// CHECK-LABEL: define{{.*}} zeroext i32 @test_dJa(i32 noundef zeroext %i, i32 noundef zeroext %j)
// CHECK: call i32 asm "sll $0, $2($3)", "=d,0,J,a"(i32 %i, i32 1000, i32 %j)
}
unsigned long test_rK(unsigned long i) {
asm("aghi %0, %2" : "=r" (i) : "0" (i), "K" (-30000));
return i;
// CHECK-LABEL: define{{.*}} i64 @test_rK(i64 %i)
// CHECK-LABEL: define{{.*}} i64 @test_rK(i64 noundef %i)
// CHECK: call i64 asm "aghi $0, $2", "=r,0,K"(i64 %i, i32 -30000)
}
unsigned long test_rL(unsigned long i) {
asm("sllg %0, %1, %2" : "=r" (i) : "r" (i), "L" (500000));
return i;
// CHECK-LABEL: define{{.*}} i64 @test_rL(i64 %i)
// CHECK-LABEL: define{{.*}} i64 @test_rL(i64 noundef %i)
// CHECK: call i64 asm "sllg $0, $1, $2", "=r,r,L"(i64 %i, i32 500000)
}
@ -109,21 +109,21 @@ void test_M() {
float test_f32(float f, float g) {
asm("aebr %0, %2" : "=f" (f) : "0" (f), "f" (g));
return f;
// CHECK-LABEL: define{{.*}} float @test_f32(float %f, float %g)
// CHECK-LABEL: define{{.*}} float @test_f32(float noundef %f, float noundef %g)
// CHECK: call float asm "aebr $0, $2", "=f,0,f"(float %f, float %g)
}
double test_f64(double f, double g) {
asm("adbr %0, %2" : "=f" (f) : "0" (f), "f" (g));
return f;
// CHECK-LABEL: define{{.*}} double @test_f64(double %f, double %g)
// CHECK-LABEL: define{{.*}} double @test_f64(double noundef %f, double noundef %g)
// CHECK: call double asm "adbr $0, $2", "=f,0,f"(double %f, double %g)
}
long double test_f128(long double f, long double g) {
asm("axbr %0, %2" : "=f" (f) : "0" (f), "f" (g));
return f;
// CHECK: define{{.*}} void @test_f128(fp128* noalias nocapture writeonly sret(fp128) align 8 [[DEST:%.*]], fp128* nocapture readonly %0, fp128* nocapture readonly %1)
// CHECK: define{{.*}} void @test_f128(fp128* noalias nocapture writeonly sret(fp128) align 8 [[DEST:%.*]], fp128* nocapture noundef readonly %0, fp128* nocapture noundef readonly %1)
// CHECK: %f = load fp128, fp128* %0
// CHECK: %g = load fp128, fp128* %1
// CHECK: [[RESULT:%.*]] = tail call fp128 asm "axbr $0, $2", "=f,0,f"(fp128 %f, fp128 %g)

38
clang/test/CodeGen/WebAssembly/wasm-arguments.c
View File

@ -7,8 +7,8 @@
// Basic argument/attribute and return tests for WebAssembly
// WEBASSEMBLY32: define void @misc_args(i32 %i, i32 %j, i64 %k, double %l, fp128 %m)
// WEBASSEMBLY64: define void @misc_args(i32 %i, i64 %j, i64 %k, double %l, fp128 %m)
// WEBASSEMBLY32: define void @misc_args(i32 noundef %i, i32 noundef %j, i64 noundef %k, double noundef %l, fp128 noundef %m)
// WEBASSEMBLY64: define void @misc_args(i32 noundef %i, i64 noundef %j, i64 noundef %k, double noundef %l, fp128 noundef %m)
void misc_args(int i, long j, long long k, double l, long double m) {}
typedef struct {
@ -17,8 +17,8 @@ typedef struct {
} s1;
// Structs should be passed byval and not split up.
// WEBASSEMBLY32: define void @struct_arg(%struct.s1* byval(%struct.s1) align 4 %i)
// WEBASSEMBLY64: define void @struct_arg(%struct.s1* byval(%struct.s1) align 4 %i)
// WEBASSEMBLY32: define void @struct_arg(%struct.s1* noundef byval(%struct.s1) align 4 %i)
// WEBASSEMBLY64: define void @struct_arg(%struct.s1* noundef byval(%struct.s1) align 4 %i)
// Except in the experimental multivalue ABI, where structs are passed in args
// EXPERIMENTAL-MV: define void @struct_arg(i32 %i.0, i32 %i.1)
@ -58,17 +58,17 @@ s2 single_elem_ret() {
return foo;
}
// WEBASSEMBLY32: define void @long_long_arg(i64 %i)
// WEBASSEMBLY64: define void @long_long_arg(i64 %i)
// WEBASSEMBLY32: define void @long_long_arg(i64 noundef %i)
// WEBASSEMBLY64: define void @long_long_arg(i64 noundef %i)
void long_long_arg(long long i) {}
// i8/i16 should be signext, i32 and higher should not.
// WEBASSEMBLY32: define void @char_short_arg(i8 signext %a, i16 signext %b)
// WEBASSEMBLY64: define void @char_short_arg(i8 signext %a, i16 signext %b)
// WEBASSEMBLY32: define void @char_short_arg(i8 noundef signext %a, i16 noundef signext %b)
// WEBASSEMBLY64: define void @char_short_arg(i8 noundef signext %a, i16 noundef signext %b)
void char_short_arg(char a, short b) {}
// WEBASSEMBLY32: define void @uchar_ushort_arg(i8 zeroext %a, i16 zeroext %b)
// WEBASSEMBLY64: define void @uchar_ushort_arg(i8 zeroext %a, i16 zeroext %b)
// WEBASSEMBLY32: define void @uchar_ushort_arg(i8 noundef zeroext %a, i16 noundef zeroext %b)
// WEBASSEMBLY64: define void @uchar_ushort_arg(i8 noundef zeroext %a, i16 noundef zeroext %b)
void uchar_ushort_arg(unsigned char a, unsigned short b) {}
enum my_enum {
@ -78,8 +78,8 @@ enum my_enum {
};
// Enums should be treated as the underlying i32.
// WEBASSEMBLY32: define void @enum_arg(i32 %a)
// WEBASSEMBLY64: define void @enum_arg(i32 %a)
// WEBASSEMBLY32: define void @enum_arg(i32 noundef %a)
// WEBASSEMBLY64: define void @enum_arg(i32 noundef %a)
void enum_arg(enum my_enum a) {}
enum my_big_enum {
@ -87,8 +87,8 @@ enum my_big_enum {
};
// Big enums should be treated as the underlying i64.
// WEBASSEMBLY32: define void @big_enum_arg(i64 %a)
// WEBASSEMBLY64: define void @big_enum_arg(i64 %a)
// WEBASSEMBLY32: define void @big_enum_arg(i64 noundef %a)
// WEBASSEMBLY64: define void @big_enum_arg(i64 noundef %a)
void big_enum_arg(enum my_big_enum a) {}
union simple_union {
@ -97,8 +97,8 @@ union simple_union {
};
// Unions should be passed as byval structs.
// WEBASSEMBLY32: define void @union_arg(%union.simple_union* byval(%union.simple_union) align 4 %s)
// WEBASSEMBLY64: define void @union_arg(%union.simple_union* byval(%union.simple_union) align 4 %s)
// WEBASSEMBLY32: define void @union_arg(%union.simple_union* noundef byval(%union.simple_union) align 4 %s)
// WEBASSEMBLY64: define void @union_arg(%union.simple_union* noundef byval(%union.simple_union) align 4 %s)
// EXPERIMENTAL-MV: define void @union_arg(i32 %s.0)
void union_arg(union simple_union s) {}
@ -123,9 +123,9 @@ typedef struct {
} bitfield1;
// Bitfields should be passed as byval structs.
// WEBASSEMBLY32: define void @bitfield_arg(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1)
// WEBASSEMBLY64: define void @bitfield_arg(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1)
// EXPERIMENTAL-MV: define void @bitfield_arg(%struct.bitfield1* byval(%struct.bitfield1) align 4 %bf1)
// WEBASSEMBLY32: define void @bitfield_arg(%struct.bitfield1* noundef byval(%struct.bitfield1) align 4 %bf1)
// WEBASSEMBLY64: define void @bitfield_arg(%struct.bitfield1* noundef byval(%struct.bitfield1) align 4 %bf1)
// EXPERIMENTAL-MV: define void @bitfield_arg(%struct.bitfield1* noundef byval(%struct.bitfield1) align 4 %bf1)
void bitfield_arg(bitfield1 bf1) {}
// And returned via sret pointers.

2
clang/test/CodeGen/WebAssembly/wasm-main_argc_argv.c
View File

@ -6,4 +6,4 @@ int main(int argc, char **argv) {
return 0;
}
// CHECK-LABEL: define i32 @__main_argc_argv(i32 %argc, i8** %argv)
// CHECK-LABEL: define i32 @__main_argc_argv(i32 noundef %argc, i8** noundef %argv)

6
clang/test/CodeGen/X86/avx-union.c
View File

@ -27,10 +27,10 @@ union M256 m1;
union M512 m2;
// CHECK-LABEL: define{{.*}} void @test()
// CHECK: call void @foo1(<4 x double>
// CHECK-LEGACY: call void @foo1(%union.M256* byval(%union.M256) align 32
// AVX: call void @foo2(%union.M512* byval(%union.M512) align 64
// CHECK-LEGACY: call void @foo1(%union.M256* noundef byval(%union.M256) align 32
// AVX: call void @foo2(%union.M512* noundef byval(%union.M512) align 64
// AVX512: call void @foo2(<8 x double>
// AVX512-LEGACY: call void @foo2(%union.M512* byval(%union.M512) align 64
// AVX512-LEGACY: call void @foo2(%union.M512* noundef byval(%union.M512) align 64
void test() {
foo1(m1);
foo2(m2);

2
clang/test/CodeGen/X86/avx512fp16-complex-abi.c
View File

@ -2,6 +2,6 @@
// Return value should be passed in <2 x half> so the backend will use xmm0
_Complex _Float16 f16(_Complex _Float16 A, _Complex _Float16 B) {
// CHECK-LABEL: define{{.*}}<2 x half> @f16({ half, half }* byval({ half, half }) align 4 %{{.*}}, { half, half }* byval({ half, half }) align 4 %{{.*}})
// CHECK-LABEL: define{{.*}}<2 x half> @f16({ half, half }* noundef byval({ half, half }) align 4 %{{.*}}, { half, half }* noundef byval({ half, half }) align 4 %{{.*}})
return A + B;
}

32
clang/test/CodeGen/X86/ms-x86-intrinsics.c
View File

@ -11,7 +11,7 @@
char test__readfsbyte(unsigned long Offset) {
return __readfsbyte(++Offset);
}
// CHECK-I386-LABEL: define dso_local signext i8 @test__readfsbyte(i32 %Offset)
// CHECK-I386-LABEL: define dso_local signext i8 @test__readfsbyte(i32 noundef %Offset)
// CHECK-I386: %inc = add i32 %Offset, 1
// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i8 addrspace(257)*
// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i8, i8 addrspace(257)* [[PTR]], align 1
@ -20,7 +20,7 @@ char test__readfsbyte(unsigned long Offset) {
short test__readfsword(unsigned long Offset) {
return __readfsword(++Offset);
}
// CHECK-I386-LABEL: define dso_local signext i16 @test__readfsword(i32 %Offset)
// CHECK-I386-LABEL: define dso_local signext i16 @test__readfsword(i32 noundef %Offset)
// CHECK-I386: %inc = add i32 %Offset, 1
// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i16 addrspace(257)*
// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i16, i16 addrspace(257)* [[PTR]], align 2
@ -29,7 +29,7 @@ short test__readfsword(unsigned long Offset) {
long test__readfsdword(unsigned long Offset) {
return __readfsdword(++Offset);
}
// CHECK-I386-LABEL: define dso_local i32 @test__readfsdword(i32 %Offset)
// CHECK-I386-LABEL: define dso_local i32 @test__readfsdword(i32 noundef %Offset)
// CHECK-I386: %inc = add i32 %Offset, 1
// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i32 addrspace(257)*
// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i32, i32 addrspace(257)* [[PTR]], align 4
@ -38,7 +38,7 @@ long test__readfsdword(unsigned long Offset) {
long long test__readfsqword(unsigned long Offset) {
return __readfsqword(++Offset);
}
// CHECK-I386-LABEL: define dso_local i64 @test__readfsqword(i32 %Offset)
// CHECK-I386-LABEL: define dso_local i64 @test__readfsqword(i32 noundef %Offset)
// CHECK-I386: %inc = add i32 %Offset, 1
// CHECK-I386: [[PTR:%[0-9]+]] = inttoptr i32 %inc to i64 addrspace(257)*
// CHECK-I386: [[VALUE:%[0-9]+]] = load volatile i64, i64 addrspace(257)* [[PTR]], align 8
@ -48,7 +48,7 @@ long long test__readfsqword(unsigned long Offset) {
__int64 test__emul(int a, int b) {
return __emul(a, b);
}
// CHECK-LABEL: define dso_local i64 @test__emul(i32 %a, i32 %b)
// CHECK-LABEL: define dso_local i64 @test__emul(i32 noundef %a, i32 noundef %b)
// CHECK: [[X:%[0-9]+]] = sext i32 %a to i64
// CHECK: [[Y:%[0-9]+]] = sext i32 %b to i64
// CHECK: [[RES:%[0-9]+]] = mul nsw i64 [[Y]], [[X]]
@ -57,7 +57,7 @@ __int64 test__emul(int a, int b) {
unsigned __int64 test__emulu(unsigned int a, unsigned int b) {
return __emulu(a, b);
}
// CHECK-LABEL: define dso_local i64 @test__emulu(i32 %a, i32 %b)
// CHECK-LABEL: define dso_local i64 @test__emulu(i32 noundef %a, i32 noundef %b)
// CHECK: [[X:%[0-9]+]] = zext i32 %a to i64
// CHECK: [[Y:%[0-9]+]] = zext i32 %b to i64
// CHECK: [[RES:%[0-9]+]] = mul nuw i64 [[Y]], [[X]]
@ -68,7 +68,7 @@ unsigned __int64 test__emulu(unsigned int a, unsigned int b) {
char test__readgsbyte(unsigned long Offset) {
return __readgsbyte(++Offset);
}
// CHECK-X64-LABEL: define dso_local i8 @test__readgsbyte(i32 %Offset)
// CHECK-X64-LABEL: define dso_local i8 @test__readgsbyte(i32 noundef %Offset)
// CHECK-X64: %inc = add i32 %Offset, 1
// CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64
// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i8 addrspace(256)*
@ -78,7 +78,7 @@ char test__readgsbyte(unsigned long Offset) {
short test__readgsword(unsigned long Offset) {
return __readgsword(++Offset);
}
// CHECK-X64-LABEL: define dso_local i16 @test__readgsword(i32 %Offset)
// CHECK-X64-LABEL: define dso_local i16 @test__readgsword(i32 noundef %Offset)
// CHECK-X64: %inc = add i32 %Offset, 1
// CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64
// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i16 addrspace(256)*
@ -88,7 +88,7 @@ short test__readgsword(unsigned long Offset) {
long test__readgsdword(unsigned long Offset) {
return __readgsdword(++Offset);
}
// CHECK-X64-LABEL: define dso_local i32 @test__readgsdword(i32 %Offset)
// CHECK-X64-LABEL: define dso_local i32 @test__readgsdword(i32 noundef %Offset)
// CHECK-X64: %inc = add i32 %Offset, 1
// CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64
// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i32 addrspace(256)*
@ -98,7 +98,7 @@ long test__readgsdword(unsigned long Offset) {
long long test__readgsqword(unsigned long Offset) {
return __readgsqword(++Offset);
}
// CHECK-X64-LABEL: define dso_local i64 @test__readgsqword(i32 %Offset)
// CHECK-X64-LABEL: define dso_local i64 @test__readgsqword(i32 noundef %Offset)
// CHECK-X64: %inc = add i32 %Offset, 1
// CHECK-X64: [[ZEXT:%[0-9]+]] = zext i32 %inc to i64
// CHECK-X64: [[PTR:%[0-9]+]] = inttoptr i64 [[ZEXT]] to i64 addrspace(256)*
@ -108,13 +108,13 @@ long long test__readgsqword(unsigned long Offset) {
__int64 test__mulh(__int64 a, __int64 b) {
return __mulh(a, b);
}
// CHECK-X64-LABEL: define dso_local i64 @test__mulh(i64 %a, i64 %b)
// CHECK-X64-LABEL: define dso_local i64 @test__mulh(i64 noundef %a, i64 noundef %b)
// CHECK-X64: = mul nsw i128 %
unsigned __int64 test__umulh(unsigned __int64 a, unsigned __int64 b) {
return __umulh(a, b);
}
// CHECK-X64-LABEL: define dso_local i64 @test__umulh(i64 %a, i64 %b)
// CHECK-X64-LABEL: define dso_local i64 @test__umulh(i64 noundef %a, i64 noundef %b)
// CHECK-X64: = mul nuw i128 %
__int64 test_mul128(__int64 Multiplier,
@ -122,7 +122,7 @@ __int64 test_mul128(__int64 Multiplier,
__int64 *HighProduct) {
return _mul128(Multiplier, Multiplicand, HighProduct);
}
// CHECK-X64-LABEL: define dso_local i64 @test_mul128(i64 %Multiplier, i64 %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct)
// CHECK-X64-LABEL: define dso_local i64 @test_mul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct)
// CHECK-X64: = sext i64 %Multiplier to i128
// CHECK-X64: = sext i64 %Multiplicand to i128
// CHECK-X64: = mul nsw i128 %
@ -134,7 +134,7 @@ unsigned __int64 test_umul128(unsigned __int64 Multiplier,
unsigned __int64 *HighProduct) {
return _umul128(Multiplier, Multiplicand, HighProduct);
}
// CHECK-X64-LABEL: define dso_local i64 @test_umul128(i64 %Multiplier, i64 %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct)
// CHECK-X64-LABEL: define dso_local i64 @test_umul128(i64 noundef %Multiplier, i64 noundef %Multiplicand, i64*{{[a-z_ ]*}}%HighProduct)
// CHECK-X64: = zext i64 %Multiplier to i128
// CHECK-X64: = zext i64 %Multiplicand to i128
// CHECK-X64: = mul nuw i128 %
@ -145,7 +145,7 @@ unsigned __int64 test__shiftleft128(unsigned __int64 l, unsigned __int64 h,
unsigned char d) {
return __shiftleft128(l, h, d);
}
// CHECK-X64-LABEL: define dso_local i64 @test__shiftleft128(i64 %l, i64 %h, i8 %d)
// CHECK-X64-LABEL: define dso_local i64 @test__shiftleft128(i64 noundef %l, i64 noundef %h, i8 noundef %d)
// CHECK-X64: = zext i8 %{{.*}} to i64
// CHECK-X64: = tail call i64 @llvm.fshl.i64(i64 %h, i64 %l, i64 %{{.*}})
// CHECK-X64: ret i64 %
@ -154,7 +154,7 @@ unsigned __int64 test__shiftright128(unsigned __int64 l, unsigned __int64 h,
unsigned char d) {
return __shiftright128(l, h, d);
}
// CHECK-X64-LABEL: define dso_local i64 @test__shiftright128(i64 %l, i64 %h, i8 %d)
// CHECK-X64-LABEL: define dso_local i64 @test__shiftright128(i64 noundef %l, i64 noundef %h, i8 noundef %d)
// CHECK-X64: = zext i8 %{{.*}} to i64
// CHECK-X64: = tail call i64 @llvm.fshr.i64(i64 %h, i64 %l, i64 %{{.*}})
// CHECK-X64: ret i64 %

8
clang/test/CodeGen/X86/strictfp_builtins.c
View File

@ -17,7 +17,7 @@ int printf(const char *, ...);
// CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) [[ATTR4:#.*]]
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* noundef getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* noundef [[TMP0]], i32 noundef [[TMP1]]) [[ATTR4:#.*]]
// CHECK-NEXT: ret void
//
void p(char *str, int x) {
@ -35,7 +35,7 @@ void p(char *str, int x) {
// CHECK-NEXT: [[SHL1:%.*]] = shl i80 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp eq i80 [[SHL1]], -18446744073709551616
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isinf(long double ld) {
@ -53,7 +53,7 @@ void test_long_double_isinf(long double ld) {
// CHECK-NEXT: [[SHL1:%.*]] = shl i80 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp ult i80 [[SHL1]], -18446744073709551616
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isfinite(long double ld) {
@ -72,7 +72,7 @@ void test_long_double_isfinite(long double ld) {
// CHECK-NEXT: [[TMP1:%.*]] = sub i80 604453686435277732577280, [[ABS]]
// CHECK-NEXT: [[ISNAN:%.*]] = lshr i80 [[TMP1]], 79
// CHECK-NEXT: [[RES:%.*]] = trunc i80 [[ISNAN]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isnan(long double ld) {

36
clang/test/CodeGen/X86/x86-atomic-long_double.c
View File

@ -39,7 +39,7 @@ long double testinc(_Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]]
@ -54,7 +54,7 @@ long double testinc(_Atomic long double *addr) {
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]]
@ -101,7 +101,7 @@ long double testdec(_Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5)
// CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]]
@ -116,7 +116,7 @@ long double testdec(_Atomic long double *addr) {
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]]
@ -170,7 +170,7 @@ long double testcompassign(_Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]]
@ -185,14 +185,14 @@ long double testcompassign(_Atomic long double *addr) {
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]]
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4
// CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[VOID_GET_ADDR:%.+]] = bitcast x86_fp80* [[GET_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_GET_ADDR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_GET_ADDR]], i32 noundef 5)
// CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[GET_ADDR]], align 4
// CHECK32: ret x86_fp80 [[RET_VAL]]
return *addr;
@ -217,7 +217,7 @@ long double testassign(_Atomic long double *addr) {
// CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4
// CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8*
// CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5)
// CHECK32: call void @__atomic_store(i32 noundef 12, i8* noundef [[ADDR_VOID]], i8* noundef [[STORE_TEMP_VOID_PTR]], i32 noundef 5)
*addr = 115;
// CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8
// CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128*
@ -229,7 +229,7 @@ long double testassign(_Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4
// CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[VOID_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_LD_TEMP]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_LD_TEMP]], i32 noundef 5)
// CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 4
// CHECK32: ret x86_fp80 [[RET_VAL]]
@ -274,7 +274,7 @@ long double test_volatile_inc(volatile _Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]]
@ -289,7 +289,7 @@ long double test_volatile_inc(volatile _Atomic long double *addr) {
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]]
@ -335,7 +335,7 @@ long double test_volatile_dec(volatile _Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5)
// CHECK32: [[ORIG_LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]]
@ -350,7 +350,7 @@ long double test_volatile_dec(volatile _Atomic long double *addr) {
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]]
@ -402,7 +402,7 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** [[ADDR_ADDR]], align 4
// CHECK32: [[VOID_PTR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[TEMP_LD_PTR:%.+]] = bitcast x86_fp80* [[TEMP_LD_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_PTR]], i8* [[TEMP_LD_PTR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_PTR]], i8* noundef [[TEMP_LD_PTR]], i32 noundef 5)
// CHECK32: [[LD_VALUE:%.+]] = load x86_fp80, x86_fp80* [[TEMP_LD_ADDR]], align 4
// CHECK32: br label %[[ATOMIC_OP:.+]]
// CHECK32: [[ATOMIC_OP]]
@ -417,14 +417,14 @@ long double test_volatile_compassign(volatile _Atomic long double *addr) {
// CHECK32: [[OBJ:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[EXPECTED:%.+]] = bitcast x86_fp80* [[OLD_VALUE_ADDR]] to i8*
// CHECK32: [[DESIRED:%.+]] = bitcast x86_fp80* [[DESIRED_VALUE_ADDR]] to i8*
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 12, i8* [[OBJ]], i8* [[EXPECTED]], i8* [[DESIRED]], i32 5, i32 5)
// CHECK32: [[FAIL_SUCCESS:%.+]] = call zeroext i1 @__atomic_compare_exchange(i32 noundef 12, i8* noundef [[OBJ]], i8* noundef [[EXPECTED]], i8* noundef [[DESIRED]], i32 noundef 5, i32 noundef 5)
// CHECK32: [[LD_VALUE]] = load x86_fp80, x86_fp80* [[OLD_VALUE_ADDR]], align 4
// CHECK32: br i1 [[FAIL_SUCCESS]], label %[[ATOMIC_CONT:.+]], label %[[ATOMIC_OP]]
// CHECK32: [[ATOMIC_CONT]]
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4
// CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[VOID_GET_ADDR:%.+]] = bitcast x86_fp80* [[GET_ADDR:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_GET_ADDR]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_GET_ADDR]], i32 noundef 5)
// CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[GET_ADDR]], align 4
// CHECK32: ret x86_fp80 [[RET_VAL]]
return *addr;
@ -449,7 +449,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
// CHECK32: store x86_fp80 {{.+}}, x86_fp80* [[STORE_TEMP_PTR]], align 4
// CHECK32: [[ADDR_VOID:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[STORE_TEMP_VOID_PTR:%.+]] = bitcast x86_fp80* [[STORE_TEMP_PTR]] to i8*
// CHECK32: call void @__atomic_store(i32 12, i8* [[ADDR_VOID]], i8* [[STORE_TEMP_VOID_PTR]], i32 5)
// CHECK32: call void @__atomic_store(i32 noundef 12, i8* noundef [[ADDR_VOID]], i8* noundef [[STORE_TEMP_VOID_PTR]], i32 noundef 5)
*addr = 115;
// CHECK: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 8
// CHECK: [[ADDR_INT:%.+]] = bitcast x86_fp80* [[ADDR]] to i128*
@ -461,7 +461,7 @@ long double test_volatile_assign(volatile _Atomic long double *addr) {
// CHECK32: [[ADDR:%.+]] = load x86_fp80*, x86_fp80** %{{.+}}, align 4
// CHECK32: [[VOID_ADDR:%.+]] = bitcast x86_fp80* [[ADDR]] to i8*
// CHECK32: [[VOID_LD_TEMP:%.+]] = bitcast x86_fp80* [[LD_TEMP:%.+]] to i8*
// CHECK32: call void @__atomic_load(i32 12, i8* [[VOID_ADDR]], i8* [[VOID_LD_TEMP]], i32 5)
// CHECK32: call void @__atomic_load(i32 noundef 12, i8* noundef [[VOID_ADDR]], i8* noundef [[VOID_LD_TEMP]], i32 noundef 5)
// CHECK32: [[RET_VAL:%.+]] = load x86_fp80, x86_fp80* [[LD_TEMP]], align 4
// CHECK32: ret x86_fp80 [[RET_VAL]]

12
clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c
View File

@ -4,38 +4,38 @@ typedef long long __m128i __attribute__ ((vector_size (16)));
typedef long long __m256i __attribute__ ((vector_size (32)));
typedef long long __m512i __attribute__ ((vector_size (64)));
// CHECK: define{{.*}} <2 x i64> @testXMMout(<2 x i64>* %p) #0
// CHECK: define{{.*}} <2 x i64> @testXMMout(<2 x i64>* noundef %p) #0
__m128i testXMMout(__m128i *p) {
__m128i xmm0;
__asm__("vmovdqu %1, %0" :"=v"(xmm0) : "m"(*(__m128i*)p));
return xmm0;
}
// CHECK: define{{.*}} <4 x i64> @testYMMout(<4 x i64>* %p) #1
// CHECK: define{{.*}} <4 x i64> @testYMMout(<4 x i64>* noundef %p) #1
__m256i testYMMout(__m256i *p) {
__m256i ymm0;
__asm__("vmovdqu %1, %0" :"=v"(ymm0) : "m"(*(__m256i*)p));
return ymm0;
}
// CHECK: define{{.*}} <8 x i64> @testZMMout(<8 x i64>* %p) #2
// CHECK: define{{.*}} <8 x i64> @testZMMout(<8 x i64>* noundef %p) #2
__m512i testZMMout(__m512i *p) {
__m512i zmm0;
__asm__("vmovdqu64 %1, %0" :"=v"(zmm0) : "m"(*(__m512i*)p));
return zmm0;
}
// CHECK: define{{.*}} void @testXMMin(<2 x i64> %xmm0, <2 x i64>* %p) #0
// CHECK: define{{.*}} void @testXMMin(<2 x i64> noundef %xmm0, <2 x i64>* noundef %p) #0
void testXMMin(__m128i xmm0, __m128i *p) {
__asm__("vmovdqu %0, %1" : : "v"(xmm0), "m"(*(__m128i*)p));
}
// CHECK: define{{.*}} void @testYMMin(<4 x i64> %ymm0, <4 x i64>* %p) #1
// CHECK: define{{.*}} void @testYMMin(<4 x i64> noundef %ymm0, <4 x i64>* noundef %p) #1
void testYMMin(__m256i ymm0, __m256i *p) {
__asm__("vmovdqu %0, %1" : : "v"(ymm0), "m"(*(__m256i*)p));
}
// CHECK: define{{.*}} void @testZMMin(<8 x i64> %zmm0, <8 x i64>* %p) #2
// CHECK: define{{.*}} void @testZMMin(<8 x i64> noundef %zmm0, <8 x i64>* noundef %p) #2
void testZMMin(__m512i zmm0, __m512i *p) {
__asm__("vmovdqu64 %0, %1" : : "v"(zmm0), "m"(*(__m512i*)p));
}

6
clang/test/CodeGen/X86/x86-long-double.cpp
View File

@ -51,6 +51,6 @@ int size = sizeof(x);
long double foo(long double d) { return d; }
// FP64: double @_Z3fooe(double %d)
// FP80: x86_fp80 @_Z3fooe(x86_fp80 %d)
// FP128: fp128 @_Z3foog(fp128 %d)
// FP64: double @_Z3fooe(double noundef %d)
// FP80: x86_fp80 @_Z3fooe(x86_fp80 noundef %d)
// FP128: fp128 @_Z3foog(fp128 noundef %d)

4
clang/test/CodeGen/X86/x86-soft-float.c
View File

@ -1,6 +1,6 @@
// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o - | FileCheck %s -check-prefix=HARD
// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft -emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT
// HARD: define{{.*}} void @f1(float %a)
// SOFT: define{{.*}} void @f1(float inreg %a)
// HARD: define{{.*}} void @f1(float noundef %a)
// SOFT: define{{.*}} void @f1(float inreg noundef %a)
void f1(float a) {}

22
clang/test/CodeGen/X86/x86-vec-i128.c
View File

@ -23,8 +23,8 @@ typedef unsigned long long v16u64 __attribute__((vector_size(16)));
typedef unsigned __int128 v16u128 __attribute__((vector_size(16)));
v16u64 test_v16u128(v16u64 a, v16u128 b) {
// CLANG10ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> %{{.*}}, <2 x i64> %{{.*}})
// CLANG9ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> %{{.*}}, <1 x i128> %{{.*}})
// CLANG10ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> noundef %{{.*}}, <2 x i64> noundef %{{.*}})
// CLANG9ABI128: define{{.*}} <2 x i64> @test_v16u128(<2 x i64> noundef %{{.*}}, <1 x i128> noundef %{{.*}})
return a + (v16u64)b;
}
@ -32,10 +32,10 @@ typedef unsigned long long v32u64 __attribute__((vector_size(32)));
typedef unsigned __int128 v32u128 __attribute__((vector_size(32)));
v32u64 test_v32u128(v32u64 a, v32u128 b) {
// MEM256ALIGN16: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* byval(<4 x i64>) align 16 %{{.*}}, <2 x i128>* byval(<2 x i128>) align 16 %{{.*}})
// MEM256ALIGN32: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* byval(<4 x i64>) align 32 %{{.*}}, <2 x i128>* byval(<2 x i128>) align 32 %{{.*}})
// CLANG10ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> %{{.*}}, <2 x i128>* byval(<2 x i128>) align 32 %{{.*}})
// CLANG9ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> %{{.*}}, <2 x i128> %{{.*}})
// MEM256ALIGN16: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* noundef byval(<4 x i64>) align 16 %{{.*}}, <2 x i128>* noundef byval(<2 x i128>) align 16 %{{.*}})
// MEM256ALIGN32: define{{.*}} <4 x i64> @test_v32u128(<4 x i64>* noundef byval(<4 x i64>) align 32 %{{.*}}, <2 x i128>* noundef byval(<2 x i128>) align 32 %{{.*}})
// CLANG10ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> noundef %{{.*}}, <2 x i128>* noundef byval(<2 x i128>) align 32 %{{.*}})
// CLANG9ABI256: define{{.*}} <4 x i64> @test_v32u128(<4 x i64> noundef %{{.*}}, <2 x i128> noundef %{{.*}})
return a + (v32u64)b;
}
@ -43,10 +43,10 @@ typedef unsigned long long v64u64 __attribute__((vector_size(64)));
typedef unsigned __int128 v64u128 __attribute__((vector_size(64)));
v64u64 test_v64u128(v64u64 a, v64u128 b) {
// MEM512ALIGN16: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* byval(<8 x i64>) align 16 %{{.*}}, <4 x i128>* byval(<4 x i128>) align 16 %{{.*}})
// MEM512ALIGN32: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* byval(<8 x i64>) align 32 %{{.*}}, <4 x i128>* byval(<4 x i128>) align 32 %{{.*}})
// MEM512ALIGN64: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* byval(<8 x i64>) align 64 %{{.*}}, <4 x i128>* byval(<4 x i128>) align 64 %{{.*}})
// CLANG10ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> %{{.*}}, <4 x i128>* byval(<4 x i128>) align 64 %{{.*}})
// CLANG9ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> %{{.*}}, <4 x i128> %{{.*}})
// MEM512ALIGN16: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* noundef byval(<8 x i64>) align 16 %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 16 %{{.*}})
// MEM512ALIGN32: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* noundef byval(<8 x i64>) align 32 %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 32 %{{.*}})
// MEM512ALIGN64: define{{.*}} <8 x i64> @test_v64u128(<8 x i64>* noundef byval(<8 x i64>) align 64 %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 64 %{{.*}})
// CLANG10ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> noundef %{{.*}}, <4 x i128>* noundef byval(<4 x i128>) align 64 %{{.*}})
// CLANG9ABI512: define{{.*}} <8 x i64> @test_v64u128(<8 x i64> noundef %{{.*}}, <4 x i128> noundef %{{.*}})
return a + (v64u64)b;
}

60
clang/test/CodeGen/X86/x86_32-arguments-darwin.c
View File

@ -30,10 +30,10 @@ long double f5(void) {
return 0;
}
// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, i8* noundef %a4)
void f6(char a0, short a1, int a2, long long a3, void *a4) {}
// CHECK-LABEL: define{{.*}} void @f7(i32 %a0)
// CHECK-LABEL: define{{.*}} void @f7(i32 noundef %a0)
typedef enum { A, B, C } e7;
void f7(e7 a0) {}
@ -52,7 +52,7 @@ void f8_2(struct s8 a0) {}
// FIXME: llvm-gcc expands this, this may have some value for the
// backend in terms of optimization but doesn't change the ABI.
// CHECK-LABEL: define{{.*}} void @f9_2(%struct.s9* byval(%struct.s9) align 4 %a0)
// CHECK-LABEL: define{{.*}} void @f9_2(%struct.s9* noundef byval(%struct.s9) align 4 %a0)
struct s9 {
int a : 17;
int b;
@ -153,7 +153,7 @@ struct s37 { float c[1][1]; } f37(void) { while (1) {} }
// CHECK-LABEL: define{{.*}} void @f38(%struct.s38* noalias sret(%struct.s38) align 2 %agg.result)
struct s38 { char a[3]; short b; } f38(void) { while (1) {} }
// CHECK-LABEL: define{{.*}} void @f39(%struct.s39* byval(%struct.s39) align 16 %x)
// CHECK-LABEL: define{{.*}} void @f39(%struct.s39* noundef byval(%struct.s39) align 16 %x)
typedef int v39 __attribute((vector_size(16)));
struct s39 { v39 x; };
void f39(struct s39 x) {}
@ -179,10 +179,10 @@ struct s44 { vvbp f0; } f44(void) { }
// CHECK-LABEL: define{{.*}} i64 @f45()
struct s45 { vvbp f0; int f1; } f45(void) { }
// CHECK-LABEL: define{{.*}} void @f46(i32 %a0)
// CHECK-LABEL: define{{.*}} void @f46(i32 noundef %a0)
void f46(enum e40 a0) { }
// CHECK-LABEL: define{{.*}} void @f47(void ()* %a1)
// CHECK-LABEL: define{{.*}} void @f47(void ()* noundef %a1)
void f47(vvbp a1) { }
// CHECK-LABEL: define{{.*}} void @f48(i32 %a0.0)
@ -201,13 +201,13 @@ void f50(struct s50 a0) { }
struct s51 { vvbp f0; int f1; };
void f51(struct s51 a0) { }
// CHECK-LABEL: define{{.*}} void @f52(%struct.s52* byval(%struct.s52) align 4 %0)
// CHECK-LABEL: define{{.*}} void @f52(%struct.s52* noundef byval(%struct.s52) align 4 %0)
struct s52 {
long double a;
};
void f52(struct s52 x) {}
// CHECK-LABEL: define{{.*}} void @f53(%struct.s53* byval(%struct.s53) align 4 %0)
// CHECK-LABEL: define{{.*}} void @f53(%struct.s53* noundef byval(%struct.s53) align 4 %0)
struct __attribute__((aligned(32))) s53 {
int x;
int y;
@ -216,34 +216,34 @@ void f53(struct s53 x) {}
typedef unsigned short v2i16 __attribute__((__vector_size__(4)));
// CHECK-LABEL: define{{.*}} i32 @f54(i32 %arg.coerce)
// CHECK-LABEL: define{{.*}} i32 @f54(i32 noundef %arg.coerce)
// rdar://8359483
v2i16 f54(v2i16 arg) { return arg+arg; }
typedef int v4i32 __attribute__((__vector_size__(16)));
// CHECK-LABEL: define{{.*}} <2 x i64> @f55(<4 x i32> %arg)
// CHECK-LABEL: define{{.*}} <2 x i64> @f55(<4 x i32> noundef %arg)
// PR8029
v4i32 f55(v4i32 arg) { return arg+arg; }
// CHECK-LABEL: define{{.*}} void @f56(
// CHECK: i8 signext %a0, %struct.s56_0* byval(%struct.s56_0) align 4 %a1,
// CHECK: i64 %a2.coerce, %struct.s56_1* byval(%struct.s56_1) align 4 %0,
// CHECK: i64 %a4.coerce, %struct.s56_2* byval(%struct.s56_2) align 4 %1,
// CHECK: <4 x i32> %a6, %struct.s56_3* byval(%struct.s56_3) align 16 %a7,
// CHECK: <2 x double> %a8, %struct.s56_4* byval(%struct.s56_4) align 16 %a9,
// CHECK: <8 x i32> %a10, %struct.s56_5* byval(%struct.s56_5) align 4 %2,
// CHECK: <4 x double> %a12, %struct.s56_6* byval(%struct.s56_6) align 4 %3)
// CHECK: i8 noundef signext %a0, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %a1,
// CHECK: i64 noundef %a2.coerce, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %0,
// CHECK: i64 noundef %a4.coerce, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %1,
// CHECK: <4 x i32> noundef %a6, %struct.s56_3* noundef byval(%struct.s56_3) align 16 %a7,
// CHECK: <2 x double> noundef %a8, %struct.s56_4* noundef byval(%struct.s56_4) align 16 %a9,
// CHECK: <8 x i32> noundef %a10, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %2,
// CHECK: <4 x double> noundef %a12, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %3)
// CHECK: call void (i32, ...) @f56_0(i32 1,
// CHECK: i32 %{{[^ ]*}}, %struct.s56_0* byval(%struct.s56_0) align 4 %{{[^ ]*}},
// CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval(%struct.s56_1) align 4 %{{[^ ]*}},
// CHECK: i64 %{{[^ ]*}}, %struct.s56_2* byval(%struct.s56_2) align 4 %{{[^ ]*}},
// CHECK: <4 x i32> %{{[^ ]*}}, %struct.s56_3* byval(%struct.s56_3) align 16 %{{[^ ]*}},
// CHECK: <2 x double> %{{[^ ]*}}, %struct.s56_4* byval(%struct.s56_4) align 16 %{{[^ ]*}},
// CHECK: <8 x i32> {{[^ ]*}}, %struct.s56_5* byval(%struct.s56_5) align 4 %{{[^ ]*}},
// CHECK: <4 x double> {{[^ ]*}}, %struct.s56_6* byval(%struct.s56_6) align 4 %{{[^ ]*}})
// CHECK: call void (i32, ...) @f56_0(i32 noundef 1,
// CHECK: i32 noundef %{{[^ ]*}}, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %{{[^ ]*}},
// CHECK: i64 noundef %{{[^ ]*}}, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %{{[^ ]*}},
// CHECK: i64 noundef %{{[^ ]*}}, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %{{[^ ]*}},
// CHECK: <4 x i32> noundef %{{[^ ]*}}, %struct.s56_3* noundef byval(%struct.s56_3) align 16 %{{[^ ]*}},
// CHECK: <2 x double> noundef %{{[^ ]*}}, %struct.s56_4* noundef byval(%struct.s56_4) align 16 %{{[^ ]*}},
// CHECK: <8 x i32> noundef {{[^ ]*}}, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %{{[^ ]*}},
// CHECK: <4 x double> noundef {{[^ ]*}}, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %{{[^ ]*}})
// CHECK: }
//
// <rdar://problem/7964854> [i386] clang misaligns long double in structures
@ -289,16 +289,16 @@ void f58(union u58 x) {}
struct s59 { float x __attribute((aligned(8))); };
struct s59 f59() { while (1) {} }
// CHECK-LABEL: define{{.*}} void @f60(%struct.s60* byval(%struct.s60) align 4 %0, i32 %y)
// CHECK-LABEL: define{{.*}} void @f60(%struct.s60* noundef byval(%struct.s60) align 4 %0, i32 noundef %y)
struct s60 { int x __attribute((aligned(8))); };
void f60(struct s60 x, int y) {}
// CHECK-LABEL: define{{.*}} void @f61(i32 %x, %struct.s61* byval(%struct.s61) align 16 %y)
// CHECK-LABEL: define{{.*}} void @f61(i32 noundef %x, %struct.s61* noundef byval(%struct.s61) align 16 %y)
typedef int T61 __attribute((vector_size(16)));
struct s61 { T61 x; int y; };
void f61(int x, struct s61 y) {}
// CHECK-LABEL: define{{.*}} void @f62(i32 %x, %struct.s62* byval(%struct.s62) align 4 %0)
// CHECK-LABEL: define{{.*}} void @f62(i32 noundef %x, %struct.s62* noundef byval(%struct.s62) align 4 %0)
typedef int T62 __attribute((vector_size(16)));
struct s62 { T62 x; int y; } __attribute((packed, aligned(8)));
void f62(int x, struct s62 y) {}
@ -317,7 +317,7 @@ int f63(int i, ...) {
return s.y;
}
// CHECK-LABEL: define{{.*}} void @f64(%struct.s64* byval(%struct.s64) align 4 %x)
// CHECK-LABEL: define{{.*}} void @f64(%struct.s64* noundef byval(%struct.s64) align 4 %x)
struct s64 { signed char a[0]; signed char b[]; };
void f64(struct s64 x) {}
@ -341,4 +341,4 @@ T66 f66(int i, ...) {
// PR14453
struct s67 { _Complex unsigned short int a; };
void f67(struct s67 x) {}
// CHECK-LABEL: define{{.*}} void @f67(%struct.s67* byval(%struct.s67) align 4 %x)
// CHECK-LABEL: define{{.*}} void @f67(%struct.s67* noundef byval(%struct.s67) align 4 %x)

24
clang/test/CodeGen/X86/x86_32-arguments-iamcu.c
View File

@ -1,18 +1,18 @@
// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o - %s | FileCheck %s
// CHECK-LABEL: define{{.*}} void @ints(i32 %a, i32 %b, i32 %c, i32 %d)
// CHECK-LABEL: define{{.*}} void @ints(i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d)
void ints(int a, int b, int c, int d) {}
// CHECK-LABEL: define{{.*}} void @floats(float %a, float %b, float %c, float %d)
// CHECK-LABEL: define{{.*}} void @floats(float noundef %a, float noundef %b, float noundef %c, float noundef %d)
void floats(float a, float b, float c, float d) {}
// CHECK-LABEL: define{{.*}} void @mixed(i32 %a, float %b, i32 %c, float %d)
// CHECK-LABEL: define{{.*}} void @mixed(i32 noundef %a, float noundef %b, i32 noundef %c, float noundef %d)
void mixed(int a, float b, int c, float d) {}
// CHECK-LABEL: define{{.*}} void @doubles(double %d1, double %d2)
// CHECK-LABEL: define{{.*}} void @doubles(double noundef %d1, double noundef %d2)
void doubles(double d1, double d2) {}
// CHECK-LABEL: define{{.*}} void @mixedDoubles(i32 %a, double %d1)
// CHECK-LABEL: define{{.*}} void @mixedDoubles(i32 noundef %a, double noundef %d1)
void mixedDoubles(int a, double d1) {}
typedef struct st3_t {
@ -37,16 +37,16 @@ typedef struct st12_t {
// CHECK-LABEL: define{{.*}} void @smallStructs(i32 %st1.coerce, i32 %st2.coerce, i32 %st3.coerce)
void smallStructs(st4_t st1, st4_t st2, st4_t st3) {}
// CHECK-LABEL: define{{.*}} void @paddedStruct(i32 %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0)
// CHECK-LABEL: define{{.*}} void @paddedStruct(i32 noundef %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0)
void paddedStruct(int i1, st5_t st, st4_t st4) {}
// CHECK-LABEL: define{{.*}} void @largeStructBegin(%struct.st12_t* byval(%struct.st12_t) align 4 %st)
// CHECK-LABEL: define{{.*}} void @largeStructBegin(%struct.st12_t* noundef byval(%struct.st12_t) align 4 %st)
void largeStructBegin(st12_t st) {}
// CHECK-LABEL: define{{.*}} void @largeStructMiddle(i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %st, i32 %i2, i32 %i3)
// CHECK-LABEL: define{{.*}} void @largeStructMiddle(i32 noundef %i1, %struct.st12_t* noundef byval(%struct.st12_t) align 4 %st, i32 noundef %i2, i32 noundef %i3)
void largeStructMiddle(int i1, st12_t st, int i2, int i3) {}
// CHECK-LABEL: define{{.*}} void @largeStructEnd(i32 %i1, i32 %i2, i32 %i3, i32 %st.0, i32 %st.1, i32 %st.2)
// CHECK-LABEL: define{{.*}} void @largeStructEnd(i32 noundef %i1, i32 noundef %i2, i32 noundef %i3, i32 %st.0, i32 %st.1, i32 %st.2)
void largeStructEnd(int i1, int i2, int i3, st12_t st) {}
// CHECK-LABEL: define{{.*}} i24 @retNonPow2Struct(i32 %r.coerce)
@ -58,12 +58,12 @@ st4_t retSmallStruct(st4_t r) { return r; }
// CHECK-LABEL: define{{.*}} i64 @retPaddedStruct(i32 %r.coerce0, i32 %r.coerce1)
st5_t retPaddedStruct(st5_t r) { return r; }
// CHECK-LABEL: define{{.*}} void @retLargeStruct(%struct.st12_t* noalias sret(%struct.st12_t) align 4 %agg.result, i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %r)
// CHECK-LABEL: define{{.*}} void @retLargeStruct(%struct.st12_t* noalias sret(%struct.st12_t) align 4 %agg.result, i32 noundef %i1, %struct.st12_t* noundef byval(%struct.st12_t) align 4 %r)
st12_t retLargeStruct(int i1, st12_t r) { return r; }
// CHECK-LABEL: define{{.*}} i32 @varArgs(i32 %i1, ...)
// CHECK-LABEL: define{{.*}} i32 @varArgs(i32 noundef %i1, ...)
int varArgs(int i1, ...) { return i1; }
// CHECK-LABEL: define{{.*}} double @longDoubleArg(double %ld1)
// CHECK-LABEL: define{{.*}} double @longDoubleArg(double noundef %ld1)
long double longDoubleArg(long double ld1) { return ld1; }

30
clang/test/CodeGen/X86/x86_32-arguments-linux.c
View File

@ -2,22 +2,22 @@
// RUN: FileCheck < %t %s
// CHECK-LABEL: define{{.*}} void @f56(
// CHECK: i8 signext %a0, %struct.s56_0* byval(%struct.s56_0) align 4 %a1,
// CHECK: i64 %a2.coerce, %struct.s56_1* byval(%struct.s56_1) align 4 %0,
// CHECK: <1 x double> %a4, %struct.s56_2* byval(%struct.s56_2) align 4 %1,
// CHECK: <4 x i32> %a6, %struct.s56_3* byval(%struct.s56_3) align 4 %2,
// CHECK: <2 x double> %a8, %struct.s56_4* byval(%struct.s56_4) align 4 %3,
// CHECK: <8 x i32> %a10, %struct.s56_5* byval(%struct.s56_5) align 4 %4,
// CHECK: <4 x double> %a12, %struct.s56_6* byval(%struct.s56_6) align 4 %5)
// CHECK: i8 noundef signext %a0, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %a1,
// CHECK: i64 noundef %a2.coerce, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %0,
// CHECK: <1 x double> noundef %a4, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %1,
// CHECK: <4 x i32> noundef %a6, %struct.s56_3* noundef byval(%struct.s56_3) align 4 %2,
// CHECK: <2 x double> noundef %a8, %struct.s56_4* noundef byval(%struct.s56_4) align 4 %3,
// CHECK: <8 x i32> noundef %a10, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %4,
// CHECK: <4 x double> noundef %a12, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %5)
// CHECK: call void (i32, ...) @f56_0(i32 1,
// CHECK: i32 %{{.*}}, %struct.s56_0* byval(%struct.s56_0) align 4 %{{[^ ]*}},
// CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval(%struct.s56_1) align 4 %{{[^ ]*}},
// CHECK: <1 x double> %{{[^ ]*}}, %struct.s56_2* byval(%struct.s56_2) align 4 %{{[^ ]*}},
// CHECK: <4 x i32> %{{[^ ]*}}, %struct.s56_3* byval(%struct.s56_3) align 4 %{{[^ ]*}},
// CHECK: <2 x double> %{{[^ ]*}}, %struct.s56_4* byval(%struct.s56_4) align 4 %{{[^ ]*}},
// CHECK: <8 x i32> %{{[^ ]*}}, %struct.s56_5* byval(%struct.s56_5) align 4 %{{[^ ]*}},
// CHECK: <4 x double> %{{[^ ]*}}, %struct.s56_6* byval(%struct.s56_6) align 4 %{{[^ ]*}})
// CHECK: call void (i32, ...) @f56_0(i32 noundef 1,
// CHECK: i32 noundef %{{.*}}, %struct.s56_0* noundef byval(%struct.s56_0) align 4 %{{[^ ]*}},
// CHECK: i64 noundef %{{[^ ]*}}, %struct.s56_1* noundef byval(%struct.s56_1) align 4 %{{[^ ]*}},
// CHECK: <1 x double> noundef %{{[^ ]*}}, %struct.s56_2* noundef byval(%struct.s56_2) align 4 %{{[^ ]*}},
// CHECK: <4 x i32> noundef %{{[^ ]*}}, %struct.s56_3* noundef byval(%struct.s56_3) align 4 %{{[^ ]*}},
// CHECK: <2 x double> noundef %{{[^ ]*}}, %struct.s56_4* noundef byval(%struct.s56_4) align 4 %{{[^ ]*}},
// CHECK: <8 x i32> noundef %{{[^ ]*}}, %struct.s56_5* noundef byval(%struct.s56_5) align 4 %{{[^ ]*}},
// CHECK: <4 x double> noundef %{{[^ ]*}}, %struct.s56_6* noundef byval(%struct.s56_6) align 4 %{{[^ ]*}})
// CHECK: }
//
// <rdar://problem/7964854> [i386] clang misaligns long double in structures

4
clang/test/CodeGen/X86/x86_32-arguments-nommx.c
View File

@ -3,9 +3,9 @@
// no-mmx should put mmx into memory
typedef int __attribute__((vector_size (8))) i32v2;
int a(i32v2 x) { return x[0]; }
// CHECK-LABEL: define{{.*}} i32 @a(i64 %x.coerce)
// CHECK-LABEL: define{{.*}} i32 @a(i64 noundef %x.coerce)
// but SSE2 vectors should still go into an SSE2 register
typedef int __attribute__((vector_size (16))) i32v4;
int b(i32v4 x) { return x[0]; }
// CHECK-LABEL: define{{.*}} i32 @b(<4 x i32> %x)
// CHECK-LABEL: define{{.*}} i32 @b(<4 x i32> noundef %x)

2
clang/test/CodeGen/X86/x86_32-arguments-realign.c
View File

@ -1,7 +1,7 @@
// RUN: %clang_cc1 -w -fblocks -triple i386-apple-darwin9 -emit-llvm -o %t %s
// RUN: FileCheck < %t %s
// CHECK-LABEL: define{{.*}} void @f0(%struct.s0* byval(%struct.s0) align 4 %0)
// CHECK-LABEL: define{{.*}} void @f0(%struct.s0* noundef byval(%struct.s0) align 4 %0)
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 16 %{{.*}}, i8* align 4 %{{.*}}, i32 16, i1 false)
// CHECK: }
struct s0 { long double a; };

12
clang/test/CodeGen/X86/x86_32-arguments-win32.c
View File

@ -72,10 +72,10 @@ void receive_vec_512(__m512 x, __m512 y, __m512 z, __m512 w, __m512 q) {
void receive_vec_1024(__m1024 x, __m1024 y, __m1024 z, __m1024 w, __m1024 q) {
gv1024 = x + y + z + w + q;
}
// CHECK-LABEL: define dso_local void @receive_vec_128(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* %0, <4 x float>* %1)
// CHECK-LABEL: define dso_local void @receive_vec_256(<8 x float> inreg %x, <8 x float> inreg %y, <8 x float> inreg %z, <8 x float>* %0, <8 x float>* %1)
// CHECK-LABEL: define dso_local void @receive_vec_512(<16 x float> inreg %x, <16 x float> inreg %y, <16 x float> inreg %z, <16 x float>* %0, <16 x float>* %1)
// CHECK-LABEL: define dso_local void @receive_vec_1024(<32 x float>* %0, <32 x float>* %1, <32 x float>* %2, <32 x float>* %3, <32 x float>* %4)
// CHECK-LABEL: define dso_local void @receive_vec_128(<4 x float> inreg noundef %x, <4 x float> inreg noundef %y, <4 x float> inreg noundef %z, <4 x float>* noundef %0, <4 x float>* noundef %1)
// CHECK-LABEL: define dso_local void @receive_vec_256(<8 x float> inreg noundef %x, <8 x float> inreg noundef %y, <8 x float> inreg noundef %z, <8 x float>* noundef %0, <8 x float>* noundef %1)
// CHECK-LABEL: define dso_local void @receive_vec_512(<16 x float> inreg noundef %x, <16 x float> inreg noundef %y, <16 x float> inreg noundef %z, <16 x float>* noundef %0, <16 x float>* noundef %1)
// CHECK-LABEL: define dso_local void @receive_vec_1024(<32 x float>* noundef %0, <32 x float>* noundef %1, <32 x float>* noundef %2, <32 x float>* noundef %3, <32 x float>* noundef %4)
void pass_vec_128() {
__m128 z = {0};
@ -83,10 +83,10 @@ void pass_vec_128() {
}
// CHECK-LABEL: define dso_local void @pass_vec_128()
// CHECK: call void @receive_vec_128(<4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float>* %{{[^,)]*}}, <4 x float>* %{{[^,)]*}})
// CHECK: call void @receive_vec_128(<4 x float> inreg noundef %{{[^,)]*}}, <4 x float> inreg noundef %{{[^,)]*}}, <4 x float> inreg noundef %{{[^,)]*}}, <4 x float>* noundef %{{[^,)]*}}, <4 x float>* noundef %{{[^,)]*}})
void __fastcall fastcall_indirect_vec(__m128 x, __m128 y, __m128 z, __m128 w, int edx, __m128 q) {
gv128 = x + y + z + w + q;
}
// CHECK-LABEL: define dso_local x86_fastcallcc void @"\01@fastcall_indirect_vec@84"(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* inreg %0, i32 inreg %edx, <4 x float>* %1)
// CHECK-LABEL: define dso_local x86_fastcallcc void @"\01@fastcall_indirect_vec@84"(<4 x float> inreg noundef %x, <4 x float> inreg noundef %y, <4 x float> inreg noundef %z, <4 x float>* inreg noundef %0, i32 inreg noundef %edx, <4 x float>* noundef %1)

6
clang/test/CodeGen/X86/x86_64-arguments-nacl.c
View File

@ -30,7 +30,7 @@ long double f5(void) {
return 0;
}
// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, i8* noundef %a4)
void f6(char a0, short a1, int a2, long long a3, void *a4) {
}
@ -61,14 +61,14 @@ void f12_1(struct s12 a0) {}
// Check that sret parameter is accounted for when checking available integer
// registers.
// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)
// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, {{.*}}* noundef byval({{.*}}) align 8 %e, i32 noundef %f)
struct s13_0 { long long f0[3]; };
struct s13_1 { long long f0[2]; };
struct s13_0 f13(int a, int b, int c, int d,
struct s13_1 e, int f) { while (1) {} }
// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* noundef byval(%struct.s20) align 32 %x)
struct __attribute__((aligned(32))) s20 {
int x;
int y;

12
clang/test/CodeGen/X86/x86_64-arguments-win32.c
View File

@ -3,25 +3,25 @@
// To be ABI compatible with code generated by MSVC, there shouldn't be any
// sign/zero extensions on types smaller than 64bit.
// CHECK-LABEL: define dso_local void @f1(i8 %a)
// CHECK-LABEL: define dso_local void @f1(i8 noundef %a)
void f1(char a) {}
// CHECK-LABEL: define dso_local void @f2(i8 %a)
// CHECK-LABEL: define dso_local void @f2(i8 noundef %a)
void f2(unsigned char a) {}
// CHECK-LABEL: define dso_local void @f3(i16 %a)
// CHECK-LABEL: define dso_local void @f3(i16 noundef %a)
void f3(short a) {}
// CHECK-LABEL: define dso_local void @f4(i16 %a)
// CHECK-LABEL: define dso_local void @f4(i16 noundef %a)
void f4(unsigned short a) {}
// For ABI compatibility with ICC, _Complex should be passed/returned
// as if it were a struct with two elements.
// CHECK-LABEL: define dso_local void @f5(i64 %a.coerce)
// CHECK-LABEL: define dso_local void @f5(i64 noundef %a.coerce)
void f5(_Complex float a) {}
// CHECK-LABEL: define dso_local void @f6({ double, double }* %a)
// CHECK-LABEL: define dso_local void @f6({ double, double }* noundef %a)
void f6(_Complex double a) {}
// CHECK-LABEL: define dso_local i64 @f7()

82
clang/test/CodeGen/X86/x86_64-arguments.c
View File

@ -36,11 +36,11 @@ long double f5(void) {
return 0;
}
// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, i8* noundef %a4)
void f6(char a0, short a1, int a2, long long a3, void *a4) {
}
// CHECK-LABEL: define{{.*}} void @f7(i32 %a0)
// CHECK-LABEL: define{{.*}} void @f7(i32 noundef %a0)
typedef enum { A, B, C } e7;
void f7(e7 a0) {
}
@ -48,7 +48,7 @@ void f7(e7 a0) {
// Test merging/passing of upper eightbyte with X87 class.
//
// CHECK-LABEL: define{{.*}} void @f8_1(%union.u8* noalias sret(%union.u8) align 16 %agg.result)
// CHECK-LABEL: define{{.*}} void @f8_2(%union.u8* byval(%union.u8) align 16 %a0)
// CHECK-LABEL: define{{.*}} void @f8_2(%union.u8* noundef byval(%union.u8) align 16 %a0)
union u8 {
long double a;
int b;
@ -74,43 +74,43 @@ void f12_1(struct s12 a0) {}
// Check that sret parameter is accounted for when checking available integer
// registers.
// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)
// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, {{.*}}* noundef byval({{.*}}) align 8 %e, i32 noundef %f)
struct s13_0 { long long f0[3]; };
struct s13_1 { long long f0[2]; };
struct s13_0 f13(int a, int b, int c, int d,
struct s13_1 e, int f) { while (1) {} }
// CHECK: define{{.*}} void @f14({{.*}}, i8 signext %X)
// CHECK: define{{.*}} void @f14({{.*}}, i8 noundef signext %X)
void f14(int a, int b, int c, int d, int e, int f, char X) {}
// CHECK: define{{.*}} void @f15({{.*}}, i8* %X)
// CHECK: define{{.*}} void @f15({{.*}}, i8* noundef %X)
void f15(int a, int b, int c, int d, int e, int f, void *X) {}
// CHECK: define{{.*}} void @f16({{.*}}, float %X)
// CHECK: define{{.*}} void @f16({{.*}}, float noundef %X)
void f16(float a, float b, float c, float d, float e, float f, float g, float h,
float X) {}
// CHECK: define{{.*}} void @f17({{.*}}, x86_fp80 %X)
// CHECK: define{{.*}} void @f17({{.*}}, x86_fp80 noundef %X)
void f17(float a, float b, float c, float d, float e, float f, float g, float h,
long double X) {}
// Check for valid coercion. The struct should be passed/returned as i32, not
// as i64 for better code quality.
// rdar://8135035
// CHECK-LABEL: define{{.*}} void @f18(i32 %a, i32 %f18_arg1.coerce)
// CHECK-LABEL: define{{.*}} void @f18(i32 noundef %a, i32 %f18_arg1.coerce)
struct f18_s0 { int f0; };
void f18(int a, struct f18_s0 f18_arg1) { while (1) {} }
// Check byval alignment.
// CHECK-LABEL: define{{.*}} void @f19(%struct.s19* byval(%struct.s19) align 16 %x)
// CHECK-LABEL: define{{.*}} void @f19(%struct.s19* noundef byval(%struct.s19) align 16 %x)
struct s19 {
long double a;
};
void f19(struct s19 x) {}
// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* noundef byval(%struct.s20) align 32 %x)
struct __attribute__((aligned(32))) s20 {
int x;
int y;
@ -144,7 +144,7 @@ struct f23S {
void f23(int A, struct f23S B) {
// CHECK-LABEL: define{{.*}} void @f23(i32 %A, i64 %B.coerce0, i32 %B.coerce1)
// CHECK-LABEL: define{{.*}} void @f23(i32 noundef %A, i64 %B.coerce0, i32 %B.coerce1)
}
struct f24s { long a; int b; };
@ -152,13 +152,13 @@ struct f24s { long a; int b; };
struct f23S f24(struct f23S *X, struct f24s *P2) {
return *X;
// CHECK: define{{.*}} { i64, i32 } @f24(%struct.f23S* %X, %struct.f24s* %P2)
// CHECK: define{{.*}} { i64, i32 } @f24(%struct.f23S* noundef %X, %struct.f24s* noundef %P2)
}
// rdar://8248065
typedef float v4f32 __attribute__((__vector_size__(16)));
v4f32 f25(v4f32 X) {
// CHECK-LABEL: define{{.*}} <4 x float> @f25(<4 x float> %X)
// CHECK-LABEL: define{{.*}} <4 x float> @f25(<4 x float> noundef %X)
// CHECK-NOT: alloca
// CHECK: alloca <4 x float>
// CHECK-NOT: alloca
@ -174,7 +174,7 @@ struct foo26 {
};
struct foo26 f26(struct foo26 *P) {
// CHECK: define{{.*}} { i32*, float* } @f26(%struct.foo26* %P)
// CHECK: define{{.*}} { i32*, float* } @f26(%struct.foo26* noundef %P)
return *P;
}
@ -246,7 +246,7 @@ float f31(struct f31foo X) {
_Complex float f32(_Complex float A, _Complex float B) {
// rdar://6379669
// CHECK-LABEL: define{{.*}} <2 x float> @f32(<2 x float> %A.coerce, <2 x float> %B.coerce)
// CHECK-LABEL: define{{.*}} <2 x float> @f32(<2 x float> noundef %A.coerce, <2 x float> noundef %B.coerce)
return A+B;
}
@ -261,17 +261,17 @@ void f33(va_list X) {
typedef unsigned long long v1i64 __attribute__((__vector_size__(8)));
// rdar://8359248
// CHECK-LABEL: define{{.*}} double @f34(double %arg.coerce)
// CHECK-LABEL: define{{.*}} double @f34(double noundef %arg.coerce)
v1i64 f34(v1i64 arg) { return arg; }
// rdar://8358475
// CHECK-LABEL: define{{.*}} double @f35(double %arg.coerce)
// CHECK-LABEL: define{{.*}} double @f35(double noundef %arg.coerce)
typedef unsigned long v1i64_2 __attribute__((__vector_size__(8)));
v1i64_2 f35(v1i64_2 arg) { return arg+arg; }
// rdar://9122143
// CHECK: declare void @func(%struct._str* byval(%struct._str) align 16)
// CHECK: declare void @func(%struct._str* noundef byval(%struct._str) align 16)
typedef struct _str {
union {
long double a;
@ -286,14 +286,14 @@ void f9122143()
func(ss);
}
// CHECK-LABEL: define{{.*}} double @f36(double %arg.coerce)
// CHECK-LABEL: define{{.*}} double @f36(double noundef %arg.coerce)
typedef unsigned v2i32 __attribute((__vector_size__(8)));
v2i32 f36(v2i32 arg) { return arg; }
// AVX: declare void @f38(<8 x float>)
// AVX: declare void @f37(<8 x float>)
// SSE: declare void @f38(%struct.s256* byval(%struct.s256) align 32)
// SSE: declare void @f37(<8 x float>* byval(<8 x float>) align 32)
// AVX: declare void @f37(<8 x float> noundef)
// SSE: declare void @f38(%struct.s256* noundef byval(%struct.s256) align 32)
// SSE: declare void @f37(<8 x float>* noundef byval(<8 x float>) align 32)
typedef float __m256 __attribute__ ((__vector_size__ (32)));
typedef struct {
__m256 m;
@ -309,7 +309,7 @@ void f39() { f38(x38); f37(x37); }
// The two next tests make sure that the struct below is passed
// in the same way regardless of avx being used
// CHECK: declare void @func40(%struct.t128* byval(%struct.t128) align 16)
// CHECK: declare void @func40(%struct.t128* noundef byval(%struct.t128) align 16)
typedef float __m128 __attribute__ ((__vector_size__ (16)));
typedef struct t128 {
__m128 m;
@ -321,7 +321,7 @@ void func41(two128 s) {
func40(s);
}
// CHECK: declare void @func42(%struct.t128_2* byval(%struct.t128_2) align 16)
// CHECK: declare void @func42(%struct.t128_2* noundef byval(%struct.t128_2) align 16)
typedef struct xxx {
__m128 array[2];
} Atwo128;
@ -350,7 +350,7 @@ int f44(int i, ...) {
}
// Text that vec3 returns the correct LLVM IR type.
// AVX-LABEL: define{{.*}} i32 @foo(<3 x i64> %X)
// AVX-LABEL: define{{.*}} i32 @foo(<3 x i64> noundef %X)
typedef long long3 __attribute((ext_vector_type(3)));
int foo(long3 X)
{
@ -368,7 +368,7 @@ void test45() { f45(x45); }
// Make sure we use byval to pass 64-bit vectors in memory; the LLVM call
// lowering can't handle this case correctly because it runs after legalization.
// CHECK: @test46
// CHECK: call void @f46({{.*}}<2 x float>* byval(<2 x float>) align 8 {{.*}}, <2 x float>* byval(<2 x float>) align 8 {{.*}})
// CHECK: call void @f46({{.*}}<2 x float>* noundef byval(<2 x float>) align 8 {{.*}}, <2 x float>* noundef byval(<2 x float>) align 8 {{.*}})
typedef float v46 __attribute((vector_size(8)));
void f46(v46,v46,v46,v46,v46,v46,v46,v46,v46,v46);
void test46() { v46 x = {1,2}; f46(x,x,x,x,x,x,x,x,x,x); }
@ -409,7 +409,7 @@ void test49(double d, double e) {
// CHECK-LABEL: define{{.*}} void @test49(
// CHECK: [[T0:%.*]] = load double, double*
// CHECK-NEXT: [[T1:%.*]] = load double, double*
// CHECK-NEXT: call void (double, ...) @test49_helper(double [[T0]], double [[T1]])
// CHECK-NEXT: call void (double, ...) @test49_helper(double noundef [[T0]], double noundef [[T1]])
void test50_helper();
void test50(double d, double e) {
@ -418,7 +418,7 @@ void test50(double d, double e) {
// CHECK-LABEL: define{{.*}} void @test50(
// CHECK: [[T0:%.*]] = load double, double*
// CHECK-NEXT: [[T1:%.*]] = load double, double*
// CHECK-NEXT: call void (double, double, ...) bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double [[T0]], double [[T1]])
// CHECK-NEXT: call void (double, double, ...) bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double noundef [[T0]], double noundef [[T1]])
struct test51_s { __uint128_t intval; };
void test51(struct test51_s *s, __builtin_va_list argList) {
@ -444,7 +444,7 @@ __m256 x52;
void test52() {
test52_helper(0, x52, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i);
}
// AVX: @test52_helper(i32 0, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
// AVX: @test52_helper(i32 noundef 0, <8 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}})
void test53(__m256 *m, __builtin_va_list argList) {
*m = __builtin_va_arg(argList, __m256);
@ -459,8 +459,8 @@ void test54() {
test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i);
test54_helper(x54, x54, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0i);
}
// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
// AVX: @test54_helper(<8 x float> {{%[a-zA-Z0-9]+}}, <8 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval({ double, double }) align 8 {{%[^)]+}})
// AVX: @test54_helper(<8 x float> noundef {{%[a-zA-Z0-9]+}}, <8 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}})
// AVX: @test54_helper(<8 x float> noundef {{%[a-zA-Z0-9]+}}, <8 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, { double, double }* noundef byval({ double, double }) align 8 {{%[^)]+}})
typedef float __m512 __attribute__ ((__vector_size__ (64)));
typedef struct {
@ -474,20 +474,20 @@ __m512 x56;
// as per https://github.com/hjl-tools/x86-psABI/commit/30f9c9 3.2.3p2 Rule 1
//
// AVX512: declare void @f55(<16 x float>)
// NO-AVX512: declare void @f55(%struct.s512* byval(%struct.s512) align 64)
// NO-AVX512: declare void @f55(%struct.s512* noundef byval(%struct.s512) align 64)
void f55(s512 x);
// __m512 has type SSE/SSEUP on AVX512.
//
// AVX512: declare void @f56(<16 x float>)
// NO-AVX512: declare void @f56(<16 x float>* byval(<16 x float>) align 64)
// AVX512: declare void @f56(<16 x float> noundef)
// NO-AVX512: declare void @f56(<16 x float>* noundef byval(<16 x float>) align 64)
void f56(__m512 x);
void f57() { f55(x55); f56(x56); }
// Like for __m128 on AVX, check that the struct below is passed
// in the same way regardless of AVX512 being used.
//
// CHECK: declare void @f58(%struct.t256* byval(%struct.t256) align 32)
// CHECK: declare void @f58(%struct.t256* noundef byval(%struct.t256) align 32)
typedef struct t256 {
__m256 m;
__m256 n;
@ -498,7 +498,7 @@ void f59(two256 s) {
f58(s);
}
// CHECK: declare void @f60(%struct.sat256* byval(%struct.sat256) align 32)
// CHECK: declare void @f60(%struct.sat256* noundef byval(%struct.sat256) align 32)
typedef struct at256 {
__m256 array[2];
} Atwo256;
@ -511,7 +511,7 @@ void f61(SAtwo256 s) {
f60(s);
}
// AVX512: @f62_helper(i32 0, <16 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
// AVX512: @f62_helper(i32 noundef 0, <16 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}})
void f62_helper(int, ...);
__m512 x62;
void f62() {
@ -528,8 +528,8 @@ void f63(__m512 *m, __builtin_va_list argList) {
*m = __builtin_va_arg(argList, __m512);
}
// AVX512: @f64_helper(<16 x float> {{%[a-zA-Z0-9]+}}, <16 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double {{%[a-zA-Z0-9]+}}, double {{%[a-zA-Z0-9]+}})
// AVX512: @f64_helper(<16 x float> {{%[a-zA-Z0-9]+}}, <16 x float> {{%[a-zA-Z0-9]+}}, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, { double, double }* byval({ double, double }) align 8 {{%[^)]+}})
// AVX512: @f64_helper(<16 x float> noundef {{%[a-zA-Z0-9]+}}, <16 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef {{%[a-zA-Z0-9]+}}, double noundef {{%[a-zA-Z0-9]+}})
// AVX512: @f64_helper(<16 x float> noundef {{%[a-zA-Z0-9]+}}, <16 x float> noundef {{%[a-zA-Z0-9]+}}, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, double noundef 1.000000e+00, { double, double }* noundef byval({ double, double }) align 8 {{%[^)]+}})
void f64_helper(__m512, ...);
__m512 x64;
void f64() {
@ -541,7 +541,7 @@ struct t65 {
__m256 m;
int : 0;
};
// SSE-LABEL: @f65(%struct.t65* byval(%struct.t65) align 32 %{{[^,)]+}})
// SSE-LABEL: @f65(%struct.t65* noundef byval(%struct.t65) align 32 %{{[^,)]+}})
// AVX: @f65(<8 x float> %{{[^,)]+}})
void f65(struct t65 a0) {
}

36
clang/test/CodeGen/X86/x86_64-longdouble.c
View File

@ -20,16 +20,16 @@ long double _Complex dataLDC = {1.0L, 1.0L};
long double TestLD(long double x) {
return x * x;
// ANDROID: define{{.*}} fp128 @TestLD(fp128 %x)
// GNU: define{{.*}} x86_fp80 @TestLD(x86_fp80 %x)
// NACL: define{{.*}} double @TestLD(double %x)
// ANDROID: define{{.*}} fp128 @TestLD(fp128 noundef %x)
// GNU: define{{.*}} x86_fp80 @TestLD(x86_fp80 noundef %x)
// NACL: define{{.*}} double @TestLD(double noundef %x)
}
long double _Complex TestLDC(long double _Complex x) {
return x * x;
// ANDROID: define{{.*}} void @TestLDC({ fp128, fp128 }* {{.*}}, { fp128, fp128 }* {{.*}} %x)
// GNU: define{{.*}} { x86_fp80, x86_fp80 } @TestLDC({ x86_fp80, x86_fp80 }* {{.*}} %x)
// NACL: define{{.*}} { double, double } @TestLDC(double %x{{.*}}, double %x{{.*}})
// NACL: define{{.*}} { double, double } @TestLDC(double noundef %x{{.*}}, double noundef %x{{.*}})
}
typedef __builtin_va_list va_list;
@ -94,30 +94,30 @@ void TestVarArg(const char *s, ...);
void TestPassVarInt(int x) {
TestVarArg("A", x);
// CHECK: define{{.*}} void @TestPassVarInt(i32 %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, i32 %x)
// CHECK: define{{.*}} void @TestPassVarInt(i32 noundef %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, i32 noundef %x)
}
void TestPassVarFloat(float x) {
TestVarArg("A", x);
// CHECK: define{{.*}} void @TestPassVarFloat(float %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double %
// CHECK: define{{.*}} void @TestPassVarFloat(float noundef %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %
}
void TestPassVarDouble(double x) {
TestVarArg("A", x);
// CHECK: define{{.*}} void @TestPassVarDouble(double %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double %x
// CHECK: define{{.*}} void @TestPassVarDouble(double noundef %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %x
}
void TestPassVarLD(long double x) {
TestVarArg("A", x);
// ANDROID: define{{.*}} void @TestPassVarLD(fp128 %x)
// ANDROID: call {{.*}} @TestVarArg(i8* {{.*}}, fp128 %x
// GNU: define{{.*}} void @TestPassVarLD(x86_fp80 %x)
// GNU: call {{.*}} @TestVarArg(i8* {{.*}}, x86_fp80 %x
// NACL: define{{.*}} void @TestPassVarLD(double %x)
// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double %x
// ANDROID: define{{.*}} void @TestPassVarLD(fp128 noundef %x)
// ANDROID: call {{.*}} @TestVarArg(i8* {{.*}}, fp128 noundef %x
// GNU: define{{.*}} void @TestPassVarLD(x86_fp80 noundef %x)
// GNU: call {{.*}} @TestVarArg(i8* {{.*}}, x86_fp80 noundef %x
// NACL: define{{.*}} void @TestPassVarLD(double noundef %x)
// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %x
}
void TestPassVarLDC(long double _Complex x) {
@ -130,6 +130,6 @@ void TestPassVarLDC(long double _Complex x) {
// GNU: store x86_fp80 %{{.*}}, x86_fp80* %
// GNU-NEXT: store x86_fp80 %{{.*}}, x86_fp80* %
// GNU-NEXT: call {{.*}} @TestVarArg(i8* {{.*}}, { x86_fp80, x86_fp80 }* {{.*}} %
// NACL: define{{.*}} void @TestPassVarLDC(double %x{{.*}}, double %x{{.*}})
// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double %x{{.*}}, double %x{{.*}})
// NACL: define{{.*}} void @TestPassVarLDC(double noundef %x{{.*}}, double noundef %x{{.*}})
// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double noundef %x{{.*}}, double noundef %x{{.*}})
}

56
clang/test/CodeGen/aapcs-align.cpp
View File

@ -19,10 +19,10 @@ void g0() {
f0m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g0
// CHECK: call void @f0(i32 1, [2 x i32] [i32 6, i32 7]
// CHECK: call void @f0m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i32] [i32 6, i32 7]
// CHECK: declare void @f0(i32, [2 x i32])
// CHECK: declare void @f0m(i32, i32, i32, i32, i32, [2 x i32])
// CHECK: call void @f0(i32 noundef 1, [2 x i32] [i32 6, i32 7]
// CHECK: call void @f0m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i32] [i32 6, i32 7]
// CHECK: declare void @f0(i32 noundef, [2 x i32])
// CHECK: declare void @f0m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i32])
// Aligned struct, passed according to its natural alignment.
struct __attribute__((aligned(8))) S8 {
@ -37,10 +37,10 @@ void g1() {
f1m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g1
// CHECK: call void @f1(i32 1, [2 x i32] [i32 6, i32 7]
// CHECK: call void @f1m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i32] [i32 6, i32 7]
// CHECK: declare void @f1(i32, [2 x i32])
// CHECK: declare void @f1m(i32, i32, i32, i32, i32, [2 x i32])
// CHECK: call void @f1(i32 noundef 1, [2 x i32] [i32 6, i32 7]
// CHECK: call void @f1m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i32] [i32 6, i32 7]
// CHECK: declare void @f1(i32 noundef, [2 x i32])
// CHECK: declare void @f1m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i32])
// Aligned struct, passed according to its natural alignment.
struct alignas(16) S16 {
@ -56,10 +56,10 @@ void g2() {
f2m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g2
// CHECK: call void @f2(i32 1, [4 x i32] [i32 6, i32 7
// CHECK: call void @f2m(i32 1, i32 2, i32 3, i32 4, i32 5, [4 x i32] [i32 6, i32 7
// CHECK: declare void @f2(i32, [4 x i32])
// CHECK: declare void @f2m(i32, i32, i32, i32, i32, [4 x i32])
// CHECK: call void @f2(i32 noundef 1, [4 x i32] [i32 6, i32 7
// CHECK: call void @f2m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [4 x i32] [i32 6, i32 7
// CHECK: declare void @f2(i32 noundef, [4 x i32])
// CHECK: declare void @f2m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [4 x i32])
// Increased natural alignment.
struct SF8 {
@ -75,10 +75,10 @@ void g3() {
f3m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g3
// CHECK: call void @f3(i32 1, [1 x i64] [i64 30064771078]
// CHECK: call void @f3m(i32 1, i32 2, i32 3, i32 4, i32 5, [1 x i64] [i64 30064771078]
// CHECK: declare void @f3(i32, [1 x i64])
// CHECK: declare void @f3m(i32, i32, i32, i32, i32, [1 x i64])
// CHECK: call void @f3(i32 noundef 1, [1 x i64] [i64 30064771078]
// CHECK: call void @f3m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [1 x i64] [i64 30064771078]
// CHECK: declare void @f3(i32 noundef, [1 x i64])
// CHECK: declare void @f3m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [1 x i64])
// Increased natural alignment, capped to 8 though.
struct SF16 {
@ -95,10 +95,10 @@ void g4() {
f4m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g4
// CHECK: call void @f4(i32 1, %struct.SF16* nonnull byval(%struct.SF16) align 8
// CHECK: call void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, %struct.SF16* nonnull byval(%struct.SF16) align 8
// CHECK: declare void @f4(i32, %struct.SF16* byval(%struct.SF16) align 8)
// CHECK: declare void @f4m(i32, i32, i32, i32, i32, %struct.SF16* byval(%struct.SF16) align 8)
// CHECK: call void @f4(i32 noundef 1, %struct.SF16* noundef nonnull byval(%struct.SF16) align 8
// CHECK: call void @f4m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, %struct.SF16* noundef nonnull byval(%struct.SF16) align 8
// CHECK: declare void @f4(i32 noundef, %struct.SF16* noundef byval(%struct.SF16) align 8)
// CHECK: declare void @f4m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, %struct.SF16* noundef byval(%struct.SF16) align 8)
// Packed structure.
struct __attribute__((packed)) P {
@ -114,10 +114,10 @@ void g5() {
f5m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g5
// CHECK: call void @f5(i32 1, [3 x i32] [i32 6, i32 7, i32 0])
// CHECK: call void @f5m(i32 1, i32 2, i32 3, i32 4, i32 5, [3 x i32] [i32 6, i32 7, i32 0])
// CHECK: declare void @f5(i32, [3 x i32])
// CHECK: declare void @f5m(i32, i32, i32, i32, i32, [3 x i32])
// CHECK: call void @f5(i32 noundef 1, [3 x i32] [i32 6, i32 7, i32 0])
// CHECK: call void @f5m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [3 x i32] [i32 6, i32 7, i32 0])
// CHECK: declare void @f5(i32 noundef, [3 x i32])
// CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [3 x i32])
// Packed and aligned, alignement causes padding at the end.
@ -134,8 +134,8 @@ void g6() {
f6m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g6
// CHECK: call void @f6(i32 1, [4 x i32] [i32 6, i32 7, i32 0, i32 undef])
// CHECK: call void @f6m(i32 1, i32 2, i32 3, i32 4, i32 5, [4 x i32] [i32 6, i32 7, i32 0, i32 undef])
// CHECK: declare void @f6(i32, [4 x i32])
// CHECK: declare void @f6m(i32, i32, i32, i32, i32, [4 x i32])
// CHECK: call void @f6(i32 noundef 1, [4 x i32] [i32 6, i32 7, i32 0, i32 undef])
// CHECK: call void @f6m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [4 x i32] [i32 6, i32 7, i32 0, i32 undef])
// CHECK: declare void @f6(i32 noundef, [4 x i32])
// CHECK: declare void @f6m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [4 x i32])
}

34
clang/test/CodeGen/aapcs64-align.cpp
View File

@ -18,10 +18,10 @@ void g0() {
f0m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g0
// CHECK: call void @f0(i64 1, [2 x i64] [i64 6, i64 7]
// CHECK: call void @f0(i64 noundef 1, [2 x i64] [i64 6, i64 7]
// CHECK: call void @f0m{{.*}}[2 x i64] [i64 6, i64 7]
// CHECK: declare void @f0(i64, [2 x i64])
// CHECK: declare void @f0m(i64, i64, i64, i64, i64, [2 x i64])
// CHECK: declare void @f0(i64 noundef, [2 x i64])
// CHECK: declare void @f0m(i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, [2 x i64])
// Aligned struct, passed according to its natural alignment.
struct __attribute__((aligned(16))) S16 {
@ -38,8 +38,8 @@ void g1() {
// CHECK: define{{.*}} void @g1
// CHECK: call void @f1{{.*}}[2 x i64] [i64 6, i64 7]
// CHECK: call void @f1m{{.*}}[2 x i64] [i64 6, i64 7]
// CHECK: declare void @f1(i64, [2 x i64])
// CHECK: declare void @f1m(i64, i64, i64, i64, i64, [2 x i64])
// CHECK: declare void @f1(i64 noundef, [2 x i64])
// CHECK: declare void @f1m(i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, [2 x i64])
// Increased natural alignment.
struct SF16 {
@ -55,10 +55,10 @@ void g3() {
f3m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g3
// CHECK: call void @f3(i64 1, i128 129127208515966861318)
// CHECK: call void @f3m(i64 1, i64 2, i64 3, i64 4, i64 5, i128 129127208515966861318)
// CHECK: declare void @f3(i64, i128)
// CHECK: declare void @f3m(i64, i64, i64, i64, i64, i128)
// CHECK: call void @f3(i64 noundef 1, i128 129127208515966861318)
// CHECK: call void @f3m(i64 noundef 1, i64 noundef 2, i64 noundef 3, i64 noundef 4, i64 noundef 5, i128 129127208515966861318)
// CHECK: declare void @f3(i64 noundef, i128)
// CHECK: declare void @f3m(i64 noundef, i64 noundef, i64 noundef, i64 noundef, i64 noundef, i128)
// Packed structure.
@ -75,10 +75,10 @@ void g4() {
f4m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g4()
// CHECK: call void @f4(i32 1, [2 x i64] [i64 30064771078, i64 0])
// CHECK: void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i64] [i64 30064771078, i64 0])
// CHECK: declare void @f4(i32, [2 x i64])
// CHECK: declare void @f4m(i32, i32, i32, i32, i32, [2 x i64])
// CHECK: call void @f4(i32 noundef 1, [2 x i64] [i64 30064771078, i64 0])
// CHECK: void @f4m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i64] [i64 30064771078, i64 0])
// CHECK: declare void @f4(i32 noundef, [2 x i64])
// CHECK: declare void @f4m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i64])
// Packed structure, overaligned, same as above.
@ -95,9 +95,9 @@ void f5m(int, int, int, int, int, P16);
f5m(1, 2, 3, 4, 5, s);
}
// CHECK: define{{.*}} void @g5()
// CHECK: call void @f5(i32 1, [2 x i64] [i64 30064771078, i64 0])
// CHECK: void @f5m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i64] [i64 30064771078, i64 0])
// CHECK: declare void @f5(i32, [2 x i64])
// CHECK: declare void @f5m(i32, i32, i32, i32, i32, [2 x i64])
// CHECK: call void @f5(i32 noundef 1, [2 x i64] [i64 30064771078, i64 0])
// CHECK: void @f5m(i32 noundef 1, i32 noundef 2, i32 noundef 3, i32 noundef 4, i32 noundef 5, [2 x i64] [i64 30064771078, i64 0])
// CHECK: declare void @f5(i32 noundef, [2 x i64])
// CHECK: declare void @f5m(i32 noundef, i32 noundef, i32 noundef, i32 noundef, i32 noundef, [2 x i64])
}

18
clang/test/CodeGen/aarch64-args.cpp
View File

@ -15,9 +15,9 @@
struct Empty {};
// CHECK: define{{.*}} i32 @empty_arg(i32 %a)
// CHECK-GNU-C: define{{.*}} i32 @empty_arg(i32 %a)
// CHECK-GNU-CXX: define{{.*}} i32 @empty_arg(i8 %e.coerce, i32 %a)
// CHECK: define{{.*}} i32 @empty_arg(i32 noundef %a)
// CHECK-GNU-C: define{{.*}} i32 @empty_arg(i32 noundef %a)
// CHECK-GNU-CXX: define{{.*}} i32 @empty_arg(i8 %e.coerce, i32 noundef %a)
EXTERNC int empty_arg(struct Empty e, int a) {
return a;
}
@ -38,9 +38,9 @@ struct SuperEmpty {
int arr[0];
};
// CHECK: define{{.*}} i32 @super_empty_arg(i32 %a)
// CHECK-GNU-C: define{{.*}} i32 @super_empty_arg(i32 %a)
// CHECK-GNU-CXX: define{{.*}} i32 @super_empty_arg(i32 %a)
// CHECK: define{{.*}} i32 @super_empty_arg(i32 noundef %a)
// CHECK-GNU-C: define{{.*}} i32 @super_empty_arg(i32 noundef %a)
// CHECK-GNU-CXX: define{{.*}} i32 @super_empty_arg(i32 noundef %a)
EXTERNC int super_empty_arg(struct SuperEmpty e, int a) {
return a;
}
@ -51,9 +51,9 @@ struct SortOfEmpty {
struct SuperEmpty e;
};
// CHECK: define{{.*}} i32 @sort_of_empty_arg(i32 %a)
// CHECK-GNU-C: define{{.*}} i32 @sort_of_empty_arg(i32 %a)
// CHECK-GNU-CXX: define{{.*}} i32 @sort_of_empty_arg(i8 %e.coerce, i32 %a)
// CHECK: define{{.*}} i32 @sort_of_empty_arg(i32 noundef %a)
// CHECK-GNU-C: define{{.*}} i32 @sort_of_empty_arg(i32 noundef %a)
// CHECK-GNU-CXX: define{{.*}} i32 @sort_of_empty_arg(i8 %e.coerce, i32 noundef %a)
EXTERNC int sort_of_empty_arg(struct Empty e, int a) {
return a;
}

8
clang/test/CodeGen/aarch64-byval-temp.c
View File

@ -32,12 +32,12 @@ void example() {
// CHECK-O0-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8*
// CHECK-O0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false)
// Finally, call using a pointer to the temporary stack space.
// CHECK-O0-NEXT: call void @pass_large(%struct.large* %[[byvaltemp]])
// CHECK-O0-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp]])
// Now, do the same for the second call, using the second temporary alloca.
// CHECK-O0-NEXT: %[[src:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp1]] to i8*
// CHECK-O0-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8*
// CHECK-O0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false)
// CHECK-O0-NEXT: call void @pass_large(%struct.large* %[[byvaltemp1]])
// CHECK-O0-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp1]])
// CHECK-O0-NEXT: ret void
//
// At O3, we should have lifetime markers to help the optimizer re-use the temporary allocas.
@ -67,7 +67,7 @@ void example() {
// CHECK-O3-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8*
// CHECK-O3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false)
// Finally, call using a pointer to the temporary stack space.
// CHECK-O3-NEXT: call void @pass_large(%struct.large* %[[byvaltemp]])
// CHECK-O3-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp]])
//
// The lifetime of the temporary used to pass a pointer to the struct ends here.
// CHECK-O3-NEXT: %[[bitcastbyvaltemp:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp]] to i8*
@ -79,7 +79,7 @@ void example() {
// CHECK-O3-NEXT: %[[src:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp1]] to i8*
// CHECK-O3-NEXT: %[[dst:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[l]] to i8*
// CHECK-O3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[src]], i8* align 8 %[[dst]], i64 64, i1 false)
// CHECK-O3-NEXT: call void @pass_large(%struct.large* %[[byvaltemp1]])
// CHECK-O3-NEXT: call void @pass_large(%struct.large* noundef %[[byvaltemp1]])
// CHECK-O3-NEXT: %[[bitcastbyvaltemp:[0-9A-Za-z-]+]] = bitcast %struct.large* %[[byvaltemp1]] to i8*
// CHECK-O3-NEXT: call void @llvm.lifetime.end.p0i8(i64 64, i8* %[[bitcastbyvaltemp]])
//

160
clang/test/CodeGen/aarch64-neon-3v.c
View File

@ -4,343 +4,343 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <8 x i8> %a, %b
// CHECK: ret <8 x i8> [[AND_I]]
int8x8_t test_vand_s8(int8x8_t a, int8x8_t b) {
return vand_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <16 x i8> %a, %b
// CHECK: ret <16 x i8> [[AND_I]]
int8x16_t test_vandq_s8(int8x16_t a, int8x16_t b) {
return vandq_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <4 x i16> %a, %b
// CHECK: ret <4 x i16> [[AND_I]]
int16x4_t test_vand_s16(int16x4_t a, int16x4_t b) {
return vand_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <8 x i16> %a, %b
// CHECK: ret <8 x i16> [[AND_I]]
int16x8_t test_vandq_s16(int16x8_t a, int16x8_t b) {
return vandq_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <2 x i32> %a, %b
// CHECK: ret <2 x i32> [[AND_I]]
int32x2_t test_vand_s32(int32x2_t a, int32x2_t b) {
return vand_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <4 x i32> %a, %b
// CHECK: ret <4 x i32> [[AND_I]]
int32x4_t test_vandq_s32(int32x4_t a, int32x4_t b) {
return vandq_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <1 x i64> %a, %b
// CHECK: ret <1 x i64> [[AND_I]]
int64x1_t test_vand_s64(int64x1_t a, int64x1_t b) {
return vand_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <2 x i64> %a, %b
// CHECK: ret <2 x i64> [[AND_I]]
int64x2_t test_vandq_s64(int64x2_t a, int64x2_t b) {
return vandq_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vand_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <8 x i8> %a, %b
// CHECK: ret <8 x i8> [[AND_I]]
uint8x8_t test_vand_u8(uint8x8_t a, uint8x8_t b) {
return vand_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vandq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <16 x i8> %a, %b
// CHECK: ret <16 x i8> [[AND_I]]
uint8x16_t test_vandq_u8(uint8x16_t a, uint8x16_t b) {
return vandq_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vand_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <4 x i16> %a, %b
// CHECK: ret <4 x i16> [[AND_I]]
uint16x4_t test_vand_u16(uint16x4_t a, uint16x4_t b) {
return vand_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vandq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <8 x i16> %a, %b
// CHECK: ret <8 x i16> [[AND_I]]
uint16x8_t test_vandq_u16(uint16x8_t a, uint16x8_t b) {
return vandq_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vand_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <2 x i32> %a, %b
// CHECK: ret <2 x i32> [[AND_I]]
uint32x2_t test_vand_u32(uint32x2_t a, uint32x2_t b) {
return vand_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vandq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <4 x i32> %a, %b
// CHECK: ret <4 x i32> [[AND_I]]
uint32x4_t test_vandq_u32(uint32x4_t a, uint32x4_t b) {
return vandq_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vand_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[AND_I:%.*]] = and <1 x i64> %a, %b
// CHECK: ret <1 x i64> [[AND_I]]
uint64x1_t test_vand_u64(uint64x1_t a, uint64x1_t b) {
return vand_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vandq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[AND_I:%.*]] = and <2 x i64> %a, %b
// CHECK: ret <2 x i64> [[AND_I]]
uint64x2_t test_vandq_u64(uint64x2_t a, uint64x2_t b) {
return vandq_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <8 x i8> %a, %b
// CHECK: ret <8 x i8> [[OR_I]]
int8x8_t test_vorr_s8(int8x8_t a, int8x8_t b) {
return vorr_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <16 x i8> %a, %b
// CHECK: ret <16 x i8> [[OR_I]]
int8x16_t test_vorrq_s8(int8x16_t a, int8x16_t b) {
return vorrq_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <4 x i16> %a, %b
// CHECK: ret <4 x i16> [[OR_I]]
int16x4_t test_vorr_s16(int16x4_t a, int16x4_t b) {
return vorr_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <8 x i16> %a, %b
// CHECK: ret <8 x i16> [[OR_I]]
int16x8_t test_vorrq_s16(int16x8_t a, int16x8_t b) {
return vorrq_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <2 x i32> %a, %b
// CHECK: ret <2 x i32> [[OR_I]]
int32x2_t test_vorr_s32(int32x2_t a, int32x2_t b) {
return vorr_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <4 x i32> %a, %b
// CHECK: ret <4 x i32> [[OR_I]]
int32x4_t test_vorrq_s32(int32x4_t a, int32x4_t b) {
return vorrq_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <1 x i64> %a, %b
// CHECK: ret <1 x i64> [[OR_I]]
int64x1_t test_vorr_s64(int64x1_t a, int64x1_t b) {
return vorr_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <2 x i64> %a, %b
// CHECK: ret <2 x i64> [[OR_I]]
int64x2_t test_vorrq_s64(int64x2_t a, int64x2_t b) {
return vorrq_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorr_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <8 x i8> %a, %b
// CHECK: ret <8 x i8> [[OR_I]]
uint8x8_t test_vorr_u8(uint8x8_t a, uint8x8_t b) {
return vorr_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vorrq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <16 x i8> %a, %b
// CHECK: ret <16 x i8> [[OR_I]]
uint8x16_t test_vorrq_u8(uint8x16_t a, uint8x16_t b) {
return vorrq_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorr_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <4 x i16> %a, %b
// CHECK: ret <4 x i16> [[OR_I]]
uint16x4_t test_vorr_u16(uint16x4_t a, uint16x4_t b) {
return vorr_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vorrq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <8 x i16> %a, %b
// CHECK: ret <8 x i16> [[OR_I]]
uint16x8_t test_vorrq_u16(uint16x8_t a, uint16x8_t b) {
return vorrq_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorr_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <2 x i32> %a, %b
// CHECK: ret <2 x i32> [[OR_I]]
uint32x2_t test_vorr_u32(uint32x2_t a, uint32x2_t b) {
return vorr_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vorrq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <4 x i32> %a, %b
// CHECK: ret <4 x i32> [[OR_I]]
uint32x4_t test_vorrq_u32(uint32x4_t a, uint32x4_t b) {
return vorrq_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorr_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[OR_I:%.*]] = or <1 x i64> %a, %b
// CHECK: ret <1 x i64> [[OR_I]]
uint64x1_t test_vorr_u64(uint64x1_t a, uint64x1_t b) {
return vorr_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vorrq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[OR_I:%.*]] = or <2 x i64> %a, %b
// CHECK: ret <2 x i64> [[OR_I]]
uint64x2_t test_vorrq_u64(uint64x2_t a, uint64x2_t b) {
return vorrq_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <8 x i8> %a, %b
// CHECK: ret <8 x i8> [[XOR_I]]
int8x8_t test_veor_s8(int8x8_t a, int8x8_t b) {
return veor_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <16 x i8> %a, %b
// CHECK: ret <16 x i8> [[XOR_I]]
int8x16_t test_veorq_s8(int8x16_t a, int8x16_t b) {
return veorq_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <4 x i16> %a, %b
// CHECK: ret <4 x i16> [[XOR_I]]
int16x4_t test_veor_s16(int16x4_t a, int16x4_t b) {
return veor_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <8 x i16> %a, %b
// CHECK: ret <8 x i16> [[XOR_I]]
int16x8_t test_veorq_s16(int16x8_t a, int16x8_t b) {
return veorq_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <2 x i32> %a, %b
// CHECK: ret <2 x i32> [[XOR_I]]
int32x2_t test_veor_s32(int32x2_t a, int32x2_t b) {
return veor_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <4 x i32> %a, %b
// CHECK: ret <4 x i32> [[XOR_I]]
int32x4_t test_veorq_s32(int32x4_t a, int32x4_t b) {
return veorq_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <1 x i64> %a, %b
// CHECK: ret <1 x i64> [[XOR_I]]
int64x1_t test_veor_s64(int64x1_t a, int64x1_t b) {
return veor_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <2 x i64> %a, %b
// CHECK: ret <2 x i64> [[XOR_I]]
int64x2_t test_veorq_s64(int64x2_t a, int64x2_t b) {
return veorq_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_veor_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <8 x i8> %a, %b
// CHECK: ret <8 x i8> [[XOR_I]]
uint8x8_t test_veor_u8(uint8x8_t a, uint8x8_t b) {
return veor_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_veorq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <16 x i8> %a, %b
// CHECK: ret <16 x i8> [[XOR_I]]
uint8x16_t test_veorq_u8(uint8x16_t a, uint8x16_t b) {
return veorq_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_veor_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <4 x i16> %a, %b
// CHECK: ret <4 x i16> [[XOR_I]]
uint16x4_t test_veor_u16(uint16x4_t a, uint16x4_t b) {
return veor_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_veorq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <8 x i16> %a, %b
// CHECK: ret <8 x i16> [[XOR_I]]
uint16x8_t test_veorq_u16(uint16x8_t a, uint16x8_t b) {
return veorq_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_veor_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <2 x i32> %a, %b
// CHECK: ret <2 x i32> [[XOR_I]]
uint32x2_t test_veor_u32(uint32x2_t a, uint32x2_t b) {
return veor_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_veorq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <4 x i32> %a, %b
// CHECK: ret <4 x i32> [[XOR_I]]
uint32x4_t test_veorq_u32(uint32x4_t a, uint32x4_t b) {
return veorq_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_veor_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[XOR_I:%.*]] = xor <1 x i64> %a, %b
// CHECK: ret <1 x i64> [[XOR_I]]
uint64x1_t test_veor_u64(uint64x1_t a, uint64x1_t b) {
return veor_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_veorq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[XOR_I:%.*]] = xor <2 x i64> %a, %b
// CHECK: ret <2 x i64> [[XOR_I]]
uint64x2_t test_veorq_u64(uint64x2_t a, uint64x2_t b) {
return veorq_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[AND_I:%.*]] = and <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[AND_I]]
@ -348,7 +348,7 @@ int8x8_t test_vbic_s8(int8x8_t a, int8x8_t b) {
return vbic_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[AND_I:%.*]] = and <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[AND_I]]
@ -356,7 +356,7 @@ int8x16_t test_vbicq_s8(int8x16_t a, int8x16_t b) {
return vbicq_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[AND_I:%.*]] = and <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[AND_I]]
@ -364,7 +364,7 @@ int16x4_t test_vbic_s16(int16x4_t a, int16x4_t b) {
return vbic_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[AND_I:%.*]] = and <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[AND_I]]
@ -372,7 +372,7 @@ int16x8_t test_vbicq_s16(int16x8_t a, int16x8_t b) {
return vbicq_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[AND_I:%.*]] = and <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[AND_I]]
@ -380,7 +380,7 @@ int32x2_t test_vbic_s32(int32x2_t a, int32x2_t b) {
return vbic_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[AND_I:%.*]] = and <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[AND_I]]
@ -388,7 +388,7 @@ int32x4_t test_vbicq_s32(int32x4_t a, int32x4_t b) {
return vbicq_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[AND_I:%.*]] = and <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[AND_I]]
@ -396,7 +396,7 @@ int64x1_t test_vbic_s64(int64x1_t a, int64x1_t b) {
return vbic_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[AND_I:%.*]] = and <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[AND_I]]
@ -404,7 +404,7 @@ int64x2_t test_vbicq_s64(int64x2_t a, int64x2_t b) {
return vbicq_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[AND_I:%.*]] = and <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[AND_I]]
@ -412,7 +412,7 @@ uint8x8_t test_vbic_u8(uint8x8_t a, uint8x8_t b) {
return vbic_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[AND_I:%.*]] = and <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[AND_I]]
@ -420,7 +420,7 @@ uint8x16_t test_vbicq_u8(uint8x16_t a, uint8x16_t b) {
return vbicq_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[AND_I:%.*]] = and <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[AND_I]]
@ -428,7 +428,7 @@ uint16x4_t test_vbic_u16(uint16x4_t a, uint16x4_t b) {
return vbic_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[AND_I:%.*]] = and <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[AND_I]]
@ -436,7 +436,7 @@ uint16x8_t test_vbicq_u16(uint16x8_t a, uint16x8_t b) {
return vbicq_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[AND_I:%.*]] = and <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[AND_I]]
@ -444,7 +444,7 @@ uint32x2_t test_vbic_u32(uint32x2_t a, uint32x2_t b) {
return vbic_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[AND_I:%.*]] = and <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[AND_I]]
@ -452,7 +452,7 @@ uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b) {
return vbicq_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[AND_I:%.*]] = and <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[AND_I]]
@ -460,7 +460,7 @@ uint64x1_t test_vbic_u64(uint64x1_t a, uint64x1_t b) {
return vbic_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[AND_I:%.*]] = and <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[AND_I]]
@ -468,7 +468,7 @@ uint64x2_t test_vbicq_u64(uint64x2_t a, uint64x2_t b) {
return vbicq_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[OR_I:%.*]] = or <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[OR_I]]
@ -476,7 +476,7 @@ int8x8_t test_vorn_s8(int8x8_t a, int8x8_t b) {
return vorn_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[OR_I:%.*]] = or <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[OR_I]]
@ -484,7 +484,7 @@ int8x16_t test_vornq_s8(int8x16_t a, int8x16_t b) {
return vornq_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[OR_I:%.*]] = or <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[OR_I]]
@ -492,7 +492,7 @@ int16x4_t test_vorn_s16(int16x4_t a, int16x4_t b) {
return vorn_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[OR_I:%.*]] = or <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[OR_I]]
@ -500,7 +500,7 @@ int16x8_t test_vornq_s16(int16x8_t a, int16x8_t b) {
return vornq_s16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[OR_I:%.*]] = or <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[OR_I]]
@ -508,7 +508,7 @@ int32x2_t test_vorn_s32(int32x2_t a, int32x2_t b) {
return vorn_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[OR_I:%.*]] = or <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[OR_I]]
@ -516,7 +516,7 @@ int32x4_t test_vornq_s32(int32x4_t a, int32x4_t b) {
return vornq_s32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[OR_I:%.*]] = or <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[OR_I]]
@ -524,7 +524,7 @@ int64x1_t test_vorn_s64(int64x1_t a, int64x1_t b) {
return vorn_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[OR_I:%.*]] = or <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[OR_I]]
@ -532,7 +532,7 @@ int64x2_t test_vornq_s64(int64x2_t a, int64x2_t b) {
return vornq_s64(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[OR_I:%.*]] = or <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[OR_I]]
@ -540,7 +540,7 @@ uint8x8_t test_vorn_u8(uint8x8_t a, uint8x8_t b) {
return vorn_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[OR_I:%.*]] = or <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[OR_I]]
@ -548,7 +548,7 @@ uint8x16_t test_vornq_u8(uint8x16_t a, uint8x16_t b) {
return vornq_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[OR_I:%.*]] = or <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[OR_I]]
@ -556,7 +556,7 @@ uint16x4_t test_vorn_u16(uint16x4_t a, uint16x4_t b) {
return vorn_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[OR_I:%.*]] = or <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[OR_I]]
@ -564,7 +564,7 @@ uint16x8_t test_vornq_u16(uint16x8_t a, uint16x8_t b) {
return vornq_u16(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[OR_I:%.*]] = or <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[OR_I]]
@ -572,7 +572,7 @@ uint32x2_t test_vorn_u32(uint32x2_t a, uint32x2_t b) {
return vorn_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[OR_I:%.*]] = or <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[OR_I]]
@ -580,7 +580,7 @@ uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b) {
return vornq_u32(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[OR_I:%.*]] = or <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[OR_I]]
@ -588,7 +588,7 @@ uint64x1_t test_vorn_u64(uint64x1_t a, uint64x1_t b) {
return vorn_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[OR_I:%.*]] = or <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[OR_I]]

88
clang/test/CodeGen/aarch64-neon-across.c
View File

@ -5,7 +5,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_s8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_s8(<8 x i8> noundef %a) #0 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
// CHECK: ret i16 [[TMP0]]
@ -13,14 +13,14 @@ int16_t test_vaddlv_s8(int8x8_t a) {
return vaddlv_s8(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_s16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_s16(<4 x i16> noundef %a) #0 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %a) #3
// CHECK: ret i32 [[VADDLV_I]]
int32_t test_vaddlv_s16(int16x4_t a) {
return vaddlv_s16(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_u8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddlv_u8(<8 x i8> noundef %a) #0 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
// CHECK: ret i16 [[TMP0]]
@ -28,14 +28,14 @@ uint16_t test_vaddlv_u8(uint8x8_t a) {
return vaddlv_u8(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_u16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vaddlv_u16(<4 x i16> noundef %a) #0 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16> %a) #3
// CHECK: ret i32 [[VADDLV_I]]
uint32_t test_vaddlv_u16(uint16x4_t a) {
return vaddlv_u16(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
// CHECK: ret i16 [[TMP0]]
@ -43,21 +43,21 @@ int16_t test_vaddlvq_s8(int8x16_t a) {
return vaddlvq_s8(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> %a) #3
// CHECK: ret i32 [[VADDLV_I]]
int32_t test_vaddlvq_s16(int16x8_t a) {
return vaddlvq_s16(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[VADDLVQ_S32_I:%.*]] = call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %a) #3
// CHECK: ret i64 [[VADDLVQ_S32_I]]
int64_t test_vaddlvq_s32(int32x4_t a) {
return vaddlvq_s32(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddlvq_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDLV_I]] to i16
// CHECK: ret i16 [[TMP0]]
@ -65,21 +65,21 @@ uint16_t test_vaddlvq_u8(uint8x16_t a) {
return vaddlvq_u8(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vaddlvq_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[VADDLV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16> %a) #3
// CHECK: ret i32 [[VADDLV_I]]
uint32_t test_vaddlvq_u16(uint16x8_t a) {
return vaddlvq_u16(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vaddlvq_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[VADDLVQ_U32_I:%.*]] = call i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32> %a) #3
// CHECK: ret i64 [[VADDLVQ_U32_I]]
uint64_t test_vaddlvq_u32(uint32x4_t a) {
return vaddlvq_u32(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_s8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_s8(<8 x i8> noundef %a) #0 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -87,7 +87,7 @@ int8_t test_vmaxv_s8(int8x8_t a) {
return vmaxv_s8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_s16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_s16(<4 x i16> noundef %a) #0 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -95,7 +95,7 @@ int16_t test_vmaxv_s16(int16x4_t a) {
return vmaxv_s16(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_u8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vmaxv_u8(<8 x i8> noundef %a) #0 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -103,7 +103,7 @@ uint8_t test_vmaxv_u8(uint8x8_t a) {
return vmaxv_u8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_u16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vmaxv_u16(<4 x i16> noundef %a) #0 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -111,7 +111,7 @@ uint16_t test_vmaxv_u16(uint16x4_t a) {
return vmaxv_u16(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -119,7 +119,7 @@ int8_t test_vmaxvq_s8(int8x16_t a) {
return vmaxvq_s8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -127,14 +127,14 @@ int16_t test_vmaxvq_s16(int16x8_t a) {
return vmaxvq_s16(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[VMAXVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a) #3
// CHECK: ret i32 [[VMAXVQ_S32_I]]
int32_t test_vmaxvq_s32(int32x4_t a) {
return vmaxvq_s32(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vmaxvq_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMAXV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -142,7 +142,7 @@ uint8_t test_vmaxvq_u8(uint8x16_t a) {
return vmaxvq_u8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vmaxvq_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[VMAXV_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMAXV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -150,14 +150,14 @@ uint16_t test_vmaxvq_u16(uint16x8_t a) {
return vmaxvq_u16(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vmaxvq_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[VMAXVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a) #3
// CHECK: ret i32 [[VMAXVQ_U32_I]]
uint32_t test_vmaxvq_u32(uint32x4_t a) {
return vmaxvq_u32(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vminv_s8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vminv_s8(<8 x i8> noundef %a) #0 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -165,7 +165,7 @@ int8_t test_vminv_s8(int8x8_t a) {
return vminv_s8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vminv_s16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vminv_s16(<4 x i16> noundef %a) #0 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -173,7 +173,7 @@ int16_t test_vminv_s16(int16x4_t a) {
return vminv_s16(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vminv_u8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vminv_u8(<8 x i8> noundef %a) #0 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -181,7 +181,7 @@ uint8_t test_vminv_u8(uint8x8_t a) {
return vminv_u8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vminv_u16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vminv_u16(<4 x i16> noundef %a) #0 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -189,7 +189,7 @@ uint16_t test_vminv_u16(uint16x4_t a) {
return vminv_u16(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vminvq_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vminvq_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -197,7 +197,7 @@ int8_t test_vminvq_s8(int8x16_t a) {
return vminvq_s8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vminvq_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vminvq_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -205,14 +205,14 @@ int16_t test_vminvq_s16(int16x8_t a) {
return vminvq_s16(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vminvq_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vminvq_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[VMINVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a) #3
// CHECK: ret i32 [[VMINVQ_S32_I]]
int32_t test_vminvq_s32(int32x4_t a) {
return vminvq_s32(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vminvq_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vminvq_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VMINV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -220,7 +220,7 @@ uint8_t test_vminvq_u8(uint8x16_t a) {
return vminvq_u8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vminvq_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vminvq_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[VMINV_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VMINV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -228,14 +228,14 @@ uint16_t test_vminvq_u16(uint16x8_t a) {
return vminvq_u16(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vminvq_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vminvq_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[VMINVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a) #3
// CHECK: ret i32 [[VMINVQ_U32_I]]
uint32_t test_vminvq_u32(uint32x4_t a) {
return vminvq_u32(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vaddv_s8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vaddv_s8(<8 x i8> noundef %a) #0 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -243,7 +243,7 @@ int8_t test_vaddv_s8(int8x8_t a) {
return vaddv_s8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddv_s16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddv_s16(<4 x i16> noundef %a) #0 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -251,7 +251,7 @@ int16_t test_vaddv_s16(int16x4_t a) {
return vaddv_s16(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vaddv_u8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vaddv_u8(<8 x i8> noundef %a) #0 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -259,7 +259,7 @@ uint8_t test_vaddv_u8(uint8x8_t a) {
return vaddv_u8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddv_u16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddv_u16(<4 x i16> noundef %a) #0 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -267,7 +267,7 @@ uint16_t test_vaddv_u16(uint16x4_t a) {
return vaddv_u16(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -275,7 +275,7 @@ int8_t test_vaddvq_s8(int8x16_t a) {
return vaddvq_s8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -283,14 +283,14 @@ int16_t test_vaddvq_s16(int16x8_t a) {
return vaddvq_s16(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[VADDVQ_S32_I:%.*]] = call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a) #3
// CHECK: ret i32 [[VADDVQ_S32_I]]
int32_t test_vaddvq_s32(int32x4_t a) {
return vaddvq_s32(a);
}
// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vaddvq_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a) #3
// CHECK: [[TMP0:%.*]] = trunc i32 [[VADDV_I]] to i8
// CHECK: ret i8 [[TMP0]]
@ -298,7 +298,7 @@ uint8_t test_vaddvq_u8(uint8x16_t a) {
return vaddvq_u8(a);
}
// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vaddvq_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[VADDV_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a) #3
// CHECK: [[TMP2:%.*]] = trunc i32 [[VADDV_I]] to i16
// CHECK: ret i16 [[TMP2]]
@ -306,35 +306,35 @@ uint16_t test_vaddvq_u16(uint16x8_t a) {
return vaddvq_u16(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vaddvq_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[VADDVQ_U32_I:%.*]] = call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a) #3
// CHECK: ret i32 [[VADDVQ_U32_I]]
uint32_t test_vaddvq_u32(uint32x4_t a) {
return vaddvq_u32(a);
}
// CHECK-LABEL: define{{.*}} float @test_vmaxvq_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vmaxvq_f32(<4 x float> noundef %a) #1 {
// CHECK: [[VMAXVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %a) #3
// CHECK: ret float [[VMAXVQ_F32_I]]
float32_t test_vmaxvq_f32(float32x4_t a) {
return vmaxvq_f32(a);
}
// CHECK-LABEL: define{{.*}} float @test_vminvq_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vminvq_f32(<4 x float> noundef %a) #1 {
// CHECK: [[VMINVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %a) #3
// CHECK: ret float [[VMINVQ_F32_I]]
float32_t test_vminvq_f32(float32x4_t a) {
return vminvq_f32(a);
}
// CHECK-LABEL: define{{.*}} float @test_vmaxnmvq_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vmaxnmvq_f32(<4 x float> noundef %a) #1 {
// CHECK: [[VMAXNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %a) #3
// CHECK: ret float [[VMAXNMVQ_F32_I]]
float32_t test_vmaxnmvq_f32(float32x4_t a) {
return vmaxnmvq_f32(a);
}
// CHECK-LABEL: define{{.*}} float @test_vminnmvq_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vminnmvq_f32(<4 x float> noundef %a) #1 {
// CHECK: [[VMINNMVQ_F32_I:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %a) #3
// CHECK: ret float [[VMINNMVQ_F32_I]]
float32_t test_vminnmvq_f32(float32x4_t a) {

24
clang/test/CodeGen/aarch64-neon-dot-product.c
View File

@ -8,35 +8,35 @@
#include <arm_neon.h>
uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: ret <2 x i32> [[RESULT]]
return vdot_u32(a, b, c);
}
uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: ret <4 x i32> [[RESULT]]
return vdotq_u32(a, b, c);
}
int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: ret <2 x i32> [[RESULT]]
return vdot_s32(a, b, c);
}
int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: ret <4 x i32> [[RESULT]]
return vdotq_s32(a, b, c);
}
uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
@ -46,7 +46,7 @@ uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
}
uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
@ -56,7 +56,7 @@ uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
}
uint32x2_t test_vdot_laneq_u32(uint32x2_t a, uint8x8_t b, uint8x16_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
@ -66,7 +66,7 @@ uint32x2_t test_vdot_laneq_u32(uint32x2_t a, uint8x8_t b, uint8x16_t c) {
}
uint32x4_t test_vdotq_laneq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
@ -76,7 +76,7 @@ uint32x4_t test_vdotq_laneq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
}
int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
@ -86,7 +86,7 @@ int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
}
int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
@ -96,7 +96,7 @@ int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
}
int32x2_t test_vdot_laneq_s32(int32x2_t a, int8x8_t b, int8x16_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
@ -106,7 +106,7 @@ int32x2_t test_vdot_laneq_s32(int32x2_t a, int8x8_t b, int8x16_t c) {
}
int32x4_t test_vdotq_laneq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>

48
clang/test/CodeGen/aarch64-neon-extract.c
View File

@ -5,14 +5,14 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
// CHECK: ret <8 x i8> [[VEXT]]
int8x8_t test_vext_s8(int8x8_t a, int8x8_t b) {
return vext_s8(a, b, 2);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
@ -23,7 +23,7 @@ int16x4_t test_vext_s16(int16x4_t a, int16x4_t b) {
return vext_s16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
@ -34,7 +34,7 @@ int32x2_t test_vext_s32(int32x2_t a, int32x2_t b) {
return vext_s32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
@ -45,14 +45,14 @@ int64x1_t test_vext_s64(int64x1_t a, int64x1_t b) {
return vext_s64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
// CHECK: ret <16 x i8> [[VEXT]]
int8x16_t test_vextq_s8(int8x16_t a, int8x16_t b) {
return vextq_s8(a, b, 2);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
@ -63,7 +63,7 @@ int16x8_t test_vextq_s16(int16x8_t a, int16x8_t b) {
return vextq_s16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
@ -74,7 +74,7 @@ int32x4_t test_vextq_s32(int32x4_t a, int32x4_t b) {
return vextq_s32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
@ -85,14 +85,14 @@ int64x2_t test_vextq_s64(int64x2_t a, int64x2_t b) {
return vextq_s64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
// CHECK: ret <8 x i8> [[VEXT]]
uint8x8_t test_vext_u8(uint8x8_t a, uint8x8_t b) {
return vext_u8(a, b, 2);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
@ -103,7 +103,7 @@ uint16x4_t test_vext_u16(uint16x4_t a, uint16x4_t b) {
return vext_u16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
@ -114,7 +114,7 @@ uint32x2_t test_vext_u32(uint32x2_t a, uint32x2_t b) {
return vext_u32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
@ -125,14 +125,14 @@ uint64x1_t test_vext_u64(uint64x1_t a, uint64x1_t b) {
return vext_u64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
// CHECK: ret <16 x i8> [[VEXT]]
uint8x16_t test_vextq_u8(uint8x16_t a, uint8x16_t b) {
return vextq_u8(a, b, 2);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
@ -143,7 +143,7 @@ uint16x8_t test_vextq_u16(uint16x8_t a, uint16x8_t b) {
return vextq_u16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
@ -154,7 +154,7 @@ uint32x4_t test_vextq_u32(uint32x4_t a, uint32x4_t b) {
return vextq_u32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
@ -165,7 +165,7 @@ uint64x2_t test_vextq_u64(uint64x2_t a, uint64x2_t b) {
return vextq_u64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vext_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
@ -176,7 +176,7 @@ float32x2_t test_vext_f32(float32x2_t a, float32x2_t b) {
return vext_f32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vext_f64(<1 x double> noundef %a, <1 x double> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
@ -187,7 +187,7 @@ float64x1_t test_vext_f64(float64x1_t a, float64x1_t b) {
return vext_f64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vextq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
@ -198,7 +198,7 @@ float32x4_t test_vextq_f32(float32x4_t a, float32x4_t b) {
return vextq_f32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vextq_f64(<2 x double> noundef %a, <2 x double> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
@ -209,14 +209,14 @@ float64x2_t test_vextq_f64(float64x2_t a, float64x2_t b) {
return vextq_f64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
// CHECK: ret <8 x i8> [[VEXT]]
poly8x8_t test_vext_p8(poly8x8_t a, poly8x8_t b) {
return vext_p8(a, b, 2);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_p16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
@ -227,14 +227,14 @@ poly16x4_t test_vext_p16(poly16x4_t a, poly16x4_t b) {
return vext_p16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
// CHECK: ret <16 x i8> [[VEXT]]
poly8x16_t test_vextq_p8(poly8x16_t a, poly8x16_t b) {
return vextq_p8(a, b, 2);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_p16(<8 x i16> noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>

42
clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
View File

@ -5,147 +5,147 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} float @test_vcvtxd_f32_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} float @test_vcvtxd_f32_f64(double noundef %a) #0 {
// CHECK: [[VCVTXD_F32_F64_I:%.*]] = call float @llvm.aarch64.sisd.fcvtxn(double %a) #2
// CHECK: ret float [[VCVTXD_F32_F64_I]]
float32_t test_vcvtxd_f32_f64(float64_t a) {
return (float32_t)vcvtxd_f32_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_s32_f32(float noundef %a) #0 {
// CHECK: [[VCVTAS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTAS_S32_F32_I]]
int32_t test_vcvtas_s32_f32(float32_t a) {
return (int32_t)vcvtas_s32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_test_vcvtad_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_test_vcvtad_s64_f64(double noundef %a) #0 {
// CHECK: [[VCVTAD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTAD_S64_F64_I]]
int64_t test_test_vcvtad_s64_f64(float64_t a) {
return (int64_t)vcvtad_s64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_u32_f32(float noundef %a) #0 {
// CHECK: [[VCVTAS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTAS_U32_F32_I]]
uint32_t test_vcvtas_u32_f32(float32_t a) {
return (uint32_t)vcvtas_u32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtad_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtad_u64_f64(double noundef %a) #0 {
// CHECK: [[VCVTAD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTAD_U64_F64_I]]
uint64_t test_vcvtad_u64_f64(float64_t a) {
return (uint64_t)vcvtad_u64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_s32_f32(float noundef %a) #0 {
// CHECK: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTMS_S32_F32_I]]
int32_t test_vcvtms_s32_f32(float32_t a) {
return (int32_t)vcvtms_s32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_s64_f64(double noundef %a) #0 {
// CHECK: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTMD_S64_F64_I]]
int64_t test_vcvtmd_s64_f64(float64_t a) {
return (int64_t)vcvtmd_s64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_u32_f32(float noundef %a) #0 {
// CHECK: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTMS_U32_F32_I]]
uint32_t test_vcvtms_u32_f32(float32_t a) {
return (uint32_t)vcvtms_u32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_u64_f64(double noundef %a) #0 {
// CHECK: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTMD_U64_F64_I]]
uint64_t test_vcvtmd_u64_f64(float64_t a) {
return (uint64_t)vcvtmd_u64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_s32_f32(float noundef %a) #0 {
// CHECK: [[VCVTNS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTNS_S32_F32_I]]
int32_t test_vcvtns_s32_f32(float32_t a) {
return (int32_t)vcvtns_s32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_s64_f64(double noundef %a) #0 {
// CHECK: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTND_S64_F64_I]]
int64_t test_vcvtnd_s64_f64(float64_t a) {
return (int64_t)vcvtnd_s64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_u32_f32(float noundef %a) #0 {
// CHECK: [[VCVTNS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTNS_U32_F32_I]]
uint32_t test_vcvtns_u32_f32(float32_t a) {
return (uint32_t)vcvtns_u32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_u64_f64(double noundef %a) #0 {
// CHECK: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTND_U64_F64_I]]
uint64_t test_vcvtnd_u64_f64(float64_t a) {
return (uint64_t)vcvtnd_u64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_s32_f32(float noundef %a) #0 {
// CHECK: [[VCVTPS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTPS_S32_F32_I]]
int32_t test_vcvtps_s32_f32(float32_t a) {
return (int32_t)vcvtps_s32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_s64_f64(double noundef %a) #0 {
// CHECK: [[VCVTPD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTPD_S64_F64_I]]
int64_t test_vcvtpd_s64_f64(float64_t a) {
return (int64_t)vcvtpd_s64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_u32_f32(float noundef %a) #0 {
// CHECK: [[VCVTPS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTPS_U32_F32_I]]
uint32_t test_vcvtps_u32_f32(float32_t a) {
return (uint32_t)vcvtps_u32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_u64_f64(double noundef %a) #0 {
// CHECK: [[VCVTPD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTPD_U64_F64_I]]
uint64_t test_vcvtpd_u64_f64(float64_t a) {
return (uint64_t)vcvtpd_u64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvts_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvts_s32_f32(float noundef %a) #0 {
// CHECK: [[TMP0:%.*]] = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
// CHECK: ret i32 [[TMP0]]
int32_t test_vcvts_s32_f32(float32_t a) {
return (int32_t)vcvts_s32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_s64_f64(double noundef %a) #0 {
// CHECK: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %a)
// CHECK: ret i64 [[TMP0]]
int64_t test_vcvtd_s64_f64(float64_t a) {
return (int64_t)vcvtd_s64_f64(a);
}
// CHECK-LABEL: define{{.*}} i32 @test_vcvts_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvts_u32_f32(float noundef %a) #0 {
// CHECK: [[TMP0:%.*]] = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %a)
// CHECK: ret i32 [[TMP0]]
uint32_t test_vcvts_u32_f32(float32_t a) {
return (uint32_t)vcvts_u32_f32(a);
}
// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_u64_f64(double noundef %a) #0 {
// CHECK: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %a)
// CHECK: ret i64 [[TMP0]]
uint64_t test_vcvtd_u64_f64(float64_t a) {

44
clang/test/CodeGen/aarch64-neon-fma.c
View File

@ -4,7 +4,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]]
@ -14,7 +14,7 @@ float32x2_t test_vmla_n_f32(float32x2_t a, float32x2_t b, float32_t c) {
return vmla_n_f32(a, b, c);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2
@ -26,7 +26,7 @@ float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {
return vmlaq_n_f32(a, b, c);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %c) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2
@ -38,7 +38,7 @@ float32x4_t test_vmlsq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {
return vmlsq_n_f32(a, b, c);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %c) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]]
@ -48,7 +48,7 @@ float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) {
return vmls_n_f32(a, b, c);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer
@ -59,7 +59,7 @@ float32x2_t test_vmla_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmla_lane_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer
@ -70,7 +70,7 @@ float32x4_t test_vmlaq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlaq_lane_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer
@ -81,7 +81,7 @@ float32x2_t test_vmla_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmla_laneq_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer
@ -92,7 +92,7 @@ float32x4_t test_vmlaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v)
return vmlaq_laneq_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer
@ -103,7 +103,7 @@ float32x2_t test_vmls_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmls_lane_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer
@ -114,7 +114,7 @@ float32x4_t test_vmlsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlsq_lane_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32_0(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer
@ -125,7 +125,7 @@ float32x2_t test_vmls_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmls_laneq_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer
@ -136,7 +136,7 @@ float32x4_t test_vmlsq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v)
return vmlsq_laneq_f32(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> <i32 1, i32 1>
@ -147,7 +147,7 @@ float32x2_t test_vmla_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmla_lane_f32(a, b, v, 1);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@ -158,7 +158,7 @@ float32x4_t test_vmlaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlaq_lane_f32(a, b, v, 1);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> <i32 3, i32 3>
@ -169,7 +169,7 @@ float32x2_t test_vmla_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmla_laneq_f32(a, b, v, 3);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
@ -180,7 +180,7 @@ float32x4_t test_vmlaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
return vmlaq_laneq_f32(a, b, v, 3);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32(<2 x float> noundef %a, <2 x float> noundef %b, <2 x float> noundef %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> <i32 1, i32 1>
@ -191,7 +191,7 @@ float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmls_lane_f32(a, b, v, 1);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32(<4 x float> noundef %a, <4 x float> noundef %b, <2 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@ -202,7 +202,7 @@ float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
float32x4_t test_vmlsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlsq_lane_f32(a, b, v, 1);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32(<2 x float> noundef %a, <2 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> <i32 3, i32 3>
@ -213,7 +213,7 @@ float32x2_t test_vmls_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmls_laneq_f32(a, b, v, 3);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
@ -224,7 +224,7 @@ float32x4_t test_vmlsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
return vmlsq_laneq_f32(a, b, v, 3);
}
// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmaq_n_f64(<2 x double> noundef %a, <2 x double> noundef %b, double noundef %c) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> [[VECINIT1_I]], <2 x double> %a)
@ -233,7 +233,7 @@ float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
return vfmaq_n_f64(a, b, c);
}
// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmsq_n_f64(<2 x double> noundef %a, <2 x double> noundef %b, double noundef %c) #1 {
// CHECK: [[SUB_I:%.*]] = fneg <2 x double> %b
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1

540
clang/test/CodeGen/aarch64-neon-ldst-one.c
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File diff suppressed because it is too large Load Diff

48
clang/test/CodeGen/aarch64-neon-scalar-copy.c
View File

@ -5,7 +5,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> %a) #0 {
// CHECK-LABEL: define{{.*}} float @test_vdups_lane_f32(<2 x float> noundef %a) #0 {
// CHECK: [[VDUPS_LANE:%.*]] = extractelement <2 x float> %a, i32 1
// CHECK: ret float [[VDUPS_LANE]]
float32_t test_vdups_lane_f32(float32x2_t a) {
@ -13,7 +13,7 @@ float32_t test_vdups_lane_f32(float32x2_t a) {
}
// CHECK-LABEL: define{{.*}} double @test_vdupd_lane_f64(<1 x double> %a) #0 {
// CHECK-LABEL: define{{.*}} double @test_vdupd_lane_f64(<1 x double> noundef %a) #0 {
// CHECK: [[VDUPD_LANE:%.*]] = extractelement <1 x double> %a, i32 0
// CHECK: ret double [[VDUPD_LANE]]
float64_t test_vdupd_lane_f64(float64x1_t a) {
@ -21,7 +21,7 @@ float64_t test_vdupd_lane_f64(float64x1_t a) {
}
// CHECK-LABEL: define{{.*}} float @test_vdups_laneq_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vdups_laneq_f32(<4 x float> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3
// CHECK: ret float [[VGETQ_LANE]]
float32_t test_vdups_laneq_f32(float32x4_t a) {
@ -29,7 +29,7 @@ float32_t test_vdups_laneq_f32(float32x4_t a) {
}
// CHECK-LABEL: define{{.*}} double @test_vdupd_laneq_f64(<2 x double> %a) #1 {
// CHECK-LABEL: define{{.*}} double @test_vdupd_laneq_f64(<2 x double> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %a, i32 1
// CHECK: ret double [[VGETQ_LANE]]
float64_t test_vdupd_laneq_f64(float64x2_t a) {
@ -37,7 +37,7 @@ float64_t test_vdupd_laneq_f64(float64x2_t a) {
}
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_s8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_s8(<8 x i8> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
// CHECK: ret i8 [[VGET_LANE]]
int8_t test_vdupb_lane_s8(int8x8_t a) {
@ -45,7 +45,7 @@ int8_t test_vdupb_lane_s8(int8x8_t a) {
}
// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_s16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_s16(<4 x i16> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
// CHECK: ret i16 [[VGET_LANE]]
int16_t test_vduph_lane_s16(int16x4_t a) {
@ -53,7 +53,7 @@ int16_t test_vduph_lane_s16(int16x4_t a) {
}
// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_s32(<2 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_s32(<2 x i32> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
// CHECK: ret i32 [[VGET_LANE]]
int32_t test_vdups_lane_s32(int32x2_t a) {
@ -61,7 +61,7 @@ int32_t test_vdups_lane_s32(int32x2_t a) {
}
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_s64(<1 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_s64(<1 x i64> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
// CHECK: ret i64 [[VGET_LANE]]
int64_t test_vdupd_lane_s64(int64x1_t a) {
@ -69,7 +69,7 @@ int64_t test_vdupd_lane_s64(int64x1_t a) {
}
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_u8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_u8(<8 x i8> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
// CHECK: ret i8 [[VGET_LANE]]
uint8_t test_vdupb_lane_u8(uint8x8_t a) {
@ -77,7 +77,7 @@ uint8_t test_vdupb_lane_u8(uint8x8_t a) {
}
// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_u16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_u16(<4 x i16> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
// CHECK: ret i16 [[VGET_LANE]]
uint16_t test_vduph_lane_u16(uint16x4_t a) {
@ -85,7 +85,7 @@ uint16_t test_vduph_lane_u16(uint16x4_t a) {
}
// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_u32(<2 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vdups_lane_u32(<2 x i32> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
// CHECK: ret i32 [[VGET_LANE]]
uint32_t test_vdups_lane_u32(uint32x2_t a) {
@ -93,14 +93,14 @@ uint32_t test_vdups_lane_u32(uint32x2_t a) {
}
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_u64(<1 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_lane_u64(<1 x i64> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
// CHECK: ret i64 [[VGET_LANE]]
uint64_t test_vdupd_lane_u64(uint64x1_t a) {
return vdupd_lane_u64(a, 0);
}
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
// CHECK: ret i8 [[VGETQ_LANE]]
int8_t test_vdupb_laneq_s8(int8x16_t a) {
@ -108,7 +108,7 @@ int8_t test_vdupb_laneq_s8(int8x16_t a) {
}
// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
// CHECK: ret i16 [[VGETQ_LANE]]
int16_t test_vduph_laneq_s16(int16x8_t a) {
@ -116,7 +116,7 @@ int16_t test_vduph_laneq_s16(int16x8_t a) {
}
// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
// CHECK: ret i32 [[VGETQ_LANE]]
int32_t test_vdups_laneq_s32(int32x4_t a) {
@ -124,7 +124,7 @@ int32_t test_vdups_laneq_s32(int32x4_t a) {
}
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_s64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_s64(<2 x i64> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
// CHECK: ret i64 [[VGETQ_LANE]]
int64_t test_vdupd_laneq_s64(int64x2_t a) {
@ -132,7 +132,7 @@ int64_t test_vdupd_laneq_s64(int64x2_t a) {
}
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
// CHECK: ret i8 [[VGETQ_LANE]]
uint8_t test_vdupb_laneq_u8(uint8x16_t a) {
@ -140,7 +140,7 @@ uint8_t test_vdupb_laneq_u8(uint8x16_t a) {
}
// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
// CHECK: ret i16 [[VGETQ_LANE]]
uint16_t test_vduph_laneq_u16(uint16x8_t a) {
@ -148,7 +148,7 @@ uint16_t test_vduph_laneq_u16(uint16x8_t a) {
}
// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vdups_laneq_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
// CHECK: ret i32 [[VGETQ_LANE]]
uint32_t test_vdups_laneq_u32(uint32x4_t a) {
@ -156,35 +156,35 @@ uint32_t test_vdups_laneq_u32(uint32x4_t a) {
}
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_u64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vdupd_laneq_u64(<2 x i64> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
// CHECK: ret i64 [[VGETQ_LANE]]
uint64_t test_vdupd_laneq_u64(uint64x2_t a) {
return vdupd_laneq_u64(a, 1);
}
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_p8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_lane_p8(<8 x i8> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
// CHECK: ret i8 [[VGET_LANE]]
poly8_t test_vdupb_lane_p8(poly8x8_t a) {
return vdupb_lane_p8(a, 7);
}
// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_p16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vduph_lane_p16(<4 x i16> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
// CHECK: ret i16 [[VGET_LANE]]
poly16_t test_vduph_lane_p16(poly16x4_t a) {
return vduph_lane_p16(a, 3);
}
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_p8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vdupb_laneq_p8(<16 x i8> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
// CHECK: ret i8 [[VGETQ_LANE]]
poly8_t test_vdupb_laneq_p8(poly8x16_t a) {
return vdupb_laneq_p8(a, 15);
}
// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_p16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vduph_laneq_p16(<8 x i16> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
// CHECK: ret i16 [[VGETQ_LANE]]
poly16_t test_vduph_laneq_p16(poly16x8_t a) {

80
clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c
View File

@ -6,7 +6,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} float @test_vmuls_lane_f32(float %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} float @test_vmuls_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %b, i32 1
// CHECK: [[MUL:%.*]] = fmul float %a, [[VGET_LANE]]
// CHECK: ret float [[MUL]]
@ -14,7 +14,7 @@ float32_t test_vmuls_lane_f32(float32_t a, float32x2_t b) {
return vmuls_lane_f32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} double @test_vmuld_lane_f64(double %a, <1 x double> %b) #0 {
// CHECK-LABEL: define{{.*}} double @test_vmuld_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %b, i32 0
// CHECK: [[MUL:%.*]] = fmul double %a, [[VGET_LANE]]
// CHECK: ret double [[MUL]]
@ -22,7 +22,7 @@ float64_t test_vmuld_lane_f64(float64_t a, float64x1_t b) {
return vmuld_lane_f64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} float @test_vmuls_laneq_f32(float %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} float @test_vmuls_laneq_f32(float noundef %a, <4 x float> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %b, i32 3
// CHECK: [[MUL:%.*]] = fmul float %a, [[VGETQ_LANE]]
// CHECK: ret float [[MUL]]
@ -30,7 +30,7 @@ float32_t test_vmuls_laneq_f32(float32_t a, float32x4_t b) {
return vmuls_laneq_f32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} double @test_vmuld_laneq_f64(double %a, <2 x double> %b) #1 {
// CHECK-LABEL: define{{.*}} double @test_vmuld_laneq_f64(double noundef %a, <2 x double> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 1
// CHECK: [[MUL:%.*]] = fmul double %a, [[VGETQ_LANE]]
// CHECK: ret double [[MUL]]
@ -38,7 +38,7 @@ float64_t test_vmuld_laneq_f64(float64_t a, float64x2_t b) {
return vmuld_laneq_f64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmul_n_f64(<1 x double> %a, double %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmul_n_f64(<1 x double> noundef %a, double noundef %b) #0 {
// CHECK: [[TMP2:%.*]] = bitcast <1 x double> %a to double
// CHECK: [[TMP3:%.*]] = fmul double [[TMP2]], %b
// CHECK: [[TMP4:%.*]] = bitcast double [[TMP3]] to <1 x double>
@ -47,7 +47,7 @@ float64x1_t test_vmul_n_f64(float64x1_t a, float64_t b) {
return vmul_n_f64(a, b);
}
// CHECK-LABEL: define{{.*}} float @test_vmulxs_lane_f32(float %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} float @test_vmulxs_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %b, i32 1
// CHECK: [[VMULXS_F32_I:%.*]] = call float @llvm.aarch64.neon.fmulx.f32(float %a, float [[VGET_LANE]])
// CHECK: ret float [[VMULXS_F32_I]]
@ -55,7 +55,7 @@ float32_t test_vmulxs_lane_f32(float32_t a, float32x2_t b) {
return vmulxs_lane_f32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} float @test_vmulxs_laneq_f32(float %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} float @test_vmulxs_laneq_f32(float noundef %a, <4 x float> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %b, i32 3
// CHECK: [[VMULXS_F32_I:%.*]] = call float @llvm.aarch64.neon.fmulx.f32(float %a, float [[VGETQ_LANE]])
// CHECK: ret float [[VMULXS_F32_I]]
@ -63,7 +63,7 @@ float32_t test_vmulxs_laneq_f32(float32_t a, float32x4_t b) {
return vmulxs_laneq_f32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} double @test_vmulxd_lane_f64(double %a, <1 x double> %b) #0 {
// CHECK-LABEL: define{{.*}} double @test_vmulxd_lane_f64(double noundef %a, <1 x double> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %b, i32 0
// CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double %a, double [[VGET_LANE]])
// CHECK: ret double [[VMULXD_F64_I]]
@ -71,7 +71,7 @@ float64_t test_vmulxd_lane_f64(float64_t a, float64x1_t b) {
return vmulxd_lane_f64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} double @test_vmulxd_laneq_f64(double %a, <2 x double> %b) #1 {
// CHECK-LABEL: define{{.*}} double @test_vmulxd_laneq_f64(double noundef %a, <2 x double> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 1
// CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double %a, double [[VGETQ_LANE]])
// CHECK: ret double [[VMULXD_F64_I]]
@ -79,7 +79,7 @@ float64_t test_vmulxd_laneq_f64(float64_t a, float64x2_t b) {
return vmulxd_laneq_f64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_lane_f64(<1 x double> %a, <1 x double> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %a, i32 0
// CHECK: [[VGET_LANE6:%.*]] = extractelement <1 x double> %b, i32 0
// CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double [[VGET_LANE]], double [[VGET_LANE6]])
@ -90,7 +90,7 @@ float64x1_t test_vmulx_lane_f64(float64x1_t a, float64x1_t b) {
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_0(<1 x double> %a, <2 x double> %b) #1 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_0(<1 x double> noundef %a, <2 x double> noundef %b) #1 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %a, i32 0
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 0
// CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double [[VGET_LANE]], double [[VGETQ_LANE]])
@ -100,7 +100,7 @@ float64x1_t test_vmulx_laneq_f64_0(float64x1_t a, float64x2_t b) {
return vmulx_laneq_f64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_1(<1 x double> %a, <2 x double> %b) #1 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vmulx_laneq_f64_1(<1 x double> noundef %a, <2 x double> noundef %b) #1 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x double> %a, i32 0
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x double> %b, i32 1
// CHECK: [[VMULXD_F64_I:%.*]] = call double @llvm.aarch64.neon.fmulx.f64(double [[VGET_LANE]], double [[VGETQ_LANE]])
@ -111,7 +111,7 @@ float64x1_t test_vmulx_laneq_f64_1(float64x1_t a, float64x2_t b) {
}
// CHECK-LABEL: define{{.*}} float @test_vfmas_lane_f32(float %a, float %b, <2 x float> %c) #0 {
// CHECK-LABEL: define{{.*}} float @test_vfmas_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
// CHECK: [[EXTRACT:%.*]] = extractelement <2 x float> %c, i32 1
// CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float %b, float [[EXTRACT]], float %a)
// CHECK: ret float [[TMP2]]
@ -119,7 +119,7 @@ float32_t test_vfmas_lane_f32(float32_t a, float32_t b, float32x2_t c) {
return vfmas_lane_f32(a, b, c, 1);
}
// CHECK-LABEL: define{{.*}} double @test_vfmad_lane_f64(double %a, double %b, <1 x double> %c) #0 {
// CHECK-LABEL: define{{.*}} double @test_vfmad_lane_f64(double noundef %a, double noundef %b, <1 x double> noundef %c) #0 {
// CHECK: [[EXTRACT:%.*]] = extractelement <1 x double> %c, i32 0
// CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double %b, double [[EXTRACT]], double %a)
// CHECK: ret double [[TMP2]]
@ -127,7 +127,7 @@ float64_t test_vfmad_lane_f64(float64_t a, float64_t b, float64x1_t c) {
return vfmad_lane_f64(a, b, c, 0);
}
// CHECK-LABEL: define{{.*}} double @test_vfmad_laneq_f64(double %a, double %b, <2 x double> %c) #1 {
// CHECK-LABEL: define{{.*}} double @test_vfmad_laneq_f64(double noundef %a, double noundef %b, <2 x double> noundef %c) #1 {
// CHECK: [[EXTRACT:%.*]] = extractelement <2 x double> %c, i32 1
// CHECK: [[TMP2:%.*]] = call double @llvm.fma.f64(double %b, double [[EXTRACT]], double %a)
// CHECK: ret double [[TMP2]]
@ -135,7 +135,7 @@ float64_t test_vfmad_laneq_f64(float64_t a, float64_t b, float64x2_t c) {
return vfmad_laneq_f64(a, b, c, 1);
}
// CHECK-LABEL: define{{.*}} float @test_vfmss_lane_f32(float %a, float %b, <2 x float> %c) #0 {
// CHECK-LABEL: define{{.*}} float @test_vfmss_lane_f32(float noundef %a, float noundef %b, <2 x float> noundef %c) #0 {
// CHECK: [[SUB:%.*]] = fneg float %b
// CHECK: [[EXTRACT:%.*]] = extractelement <2 x float> %c, i32 1
// CHECK: [[TMP2:%.*]] = call float @llvm.fma.f32(float [[SUB]], float [[EXTRACT]], float %a)
@ -144,7 +144,7 @@ float32_t test_vfmss_lane_f32(float32_t a, float32_t b, float32x2_t c) {
return vfmss_lane_f32(a, b, c, 1);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_lane_f64(<1 x double> %a, <1 x double> %b, <1 x double> %v) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <1 x double> %v to <8 x i8>
@ -158,7 +158,7 @@ float64x1_t test_vfma_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) {
return vfma_lane_f64(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_lane_f64(<1 x double> %a, <1 x double> %b, <1 x double> %v) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_lane_f64(<1 x double> noundef %a, <1 x double> noundef %b, <1 x double> noundef %v) #0 {
// CHECK: [[SUB:%.*]] = fneg <1 x double> %b
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8>
@ -173,7 +173,7 @@ float64x1_t test_vfms_lane_f64(float64x1_t a, float64x1_t b, float64x1_t v) {
return vfms_lane_f64(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_laneq_f64(<1 x double> %a, <1 x double> %b, <2 x double> %v) #1 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfma_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <2 x double> %v to <16 x i8>
@ -188,7 +188,7 @@ float64x1_t test_vfma_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) {
return vfma_laneq_f64(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_laneq_f64(<1 x double> %a, <1 x double> %b, <2 x double> %v) #1 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vfms_laneq_f64(<1 x double> noundef %a, <1 x double> noundef %b, <2 x double> noundef %v) #1 {
// CHECK: [[SUB:%.*]] = fneg <1 x double> %b
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x double> [[SUB]] to <8 x i8>
@ -204,7 +204,7 @@ float64x1_t test_vfms_laneq_f64(float64x1_t a, float64x1_t b, float64x2_t v) {
return vfms_laneq_f64(a, b, v, 0);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_lane_s16(i16 %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %b, i32 3
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i64 0
@ -215,7 +215,7 @@ int32_t test_vqdmullh_lane_s16(int16_t a, int16x4_t b) {
return vqdmullh_lane_s16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_lane_s32(i32 %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %b, i32 1
// CHECK: [[VQDMULLS_S32_I:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %a, i32 [[VGET_LANE]])
// CHECK: ret i64 [[VQDMULLS_S32_I]]
@ -223,7 +223,7 @@ int64_t test_vqdmulls_lane_s32(int32_t a, int32x2_t b) {
return vqdmulls_lane_s32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_laneq_s16(i16 %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmullh_laneq_s16(i16 noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %b, i32 7
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGETQ_LANE]], i64 0
@ -234,7 +234,7 @@ int32_t test_vqdmullh_laneq_s16(int16_t a, int16x8_t b) {
return vqdmullh_laneq_s16(a, b, 7);
}
// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_laneq_s32(i32 %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vqdmulls_laneq_s32(i32 noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %b, i32 3
// CHECK: [[VQDMULLS_S32_I:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %a, i32 [[VGETQ_LANE]])
// CHECK: ret i64 [[VQDMULLS_S32_I]]
@ -242,7 +242,7 @@ int64_t test_vqdmulls_laneq_s32(int32_t a, int32x4_t b) {
return vqdmulls_laneq_s32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_lane_s16(i16 %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %b, i32 3
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i64 0
@ -253,7 +253,7 @@ int16_t test_vqdmulhh_lane_s16(int16_t a, int16x4_t b) {
return vqdmulhh_lane_s16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_lane_s32(i32 %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %b, i32 1
// CHECK: [[VQDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %a, i32 [[VGET_LANE]])
// CHECK: ret i32 [[VQDMULHS_S32_I]]
@ -262,7 +262,7 @@ int32_t test_vqdmulhs_lane_s32(int32_t a, int32x2_t b) {
}
// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_laneq_s16(i16 %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vqdmulhh_laneq_s16(i16 noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %b, i32 7
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGETQ_LANE]], i64 0
@ -274,7 +274,7 @@ int16_t test_vqdmulhh_laneq_s16(int16_t a, int16x8_t b) {
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_laneq_s32(i32 %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmulhs_laneq_s32(i32 noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %b, i32 3
// CHECK: [[VQDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %a, i32 [[VGETQ_LANE]])
// CHECK: ret i32 [[VQDMULHS_S32_I]]
@ -282,7 +282,7 @@ int32_t test_vqdmulhs_laneq_s32(int32_t a, int32x4_t b) {
return vqdmulhs_laneq_s32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_lane_s16(i16 %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %b, i32 3
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i64 0
@ -293,7 +293,7 @@ int16_t test_vqrdmulhh_lane_s16(int16_t a, int16x4_t b) {
return vqrdmulhh_lane_s16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_lane_s32(i32 %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %b, i32 1
// CHECK: [[VQRDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %a, i32 [[VGET_LANE]])
// CHECK: ret i32 [[VQRDMULHS_S32_I]]
@ -302,7 +302,7 @@ int32_t test_vqrdmulhs_lane_s32(int32_t a, int32x2_t b) {
}
// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_laneq_s16(i16 %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vqrdmulhh_laneq_s16(i16 noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %b, i32 7
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %a, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[VGETQ_LANE]], i64 0
@ -314,7 +314,7 @@ int16_t test_vqrdmulhh_laneq_s16(int16_t a, int16x8_t b) {
}
// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_laneq_s32(i32 %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vqrdmulhs_laneq_s32(i32 noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %b, i32 3
// CHECK: [[VQRDMULHS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %a, i32 [[VGETQ_LANE]])
// CHECK: ret i32 [[VQRDMULHS_S32_I]]
@ -322,7 +322,7 @@ int32_t test_vqrdmulhs_laneq_s32(int32_t a, int32x4_t b) {
return vqrdmulhs_laneq_s32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_lane_s16(i32 %a, i16 %b, <4 x i16> %c) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_lane_s16(i32 noundef %a, i16 noundef %b, <4 x i16> noundef %c) #0 {
// CHECK: [[LANE:%.*]] = extractelement <4 x i16> %c, i32 3
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0
@ -334,7 +334,7 @@ int32_t test_vqdmlalh_lane_s16(int32_t a, int16_t b, int16x4_t c) {
return vqdmlalh_lane_s16(a, b, c, 3);
}
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_lane_s32(i64 %a, i32 %b, <2 x i32> %c) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_lane_s32(i64 noundef %a, i32 noundef %b, <2 x i32> noundef %c) #0 {
// CHECK: [[LANE:%.*]] = extractelement <2 x i32> %c, i32 1
// CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]])
// CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %a, i64 [[VQDMLXL]])
@ -343,7 +343,7 @@ int64_t test_vqdmlals_lane_s32(int64_t a, int32_t b, int32x2_t c) {
return vqdmlals_lane_s32(a, b, c, 1);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_laneq_s16(i32 %a, i16 %b, <8 x i16> %c) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlalh_laneq_s16(i32 noundef %a, i16 noundef %b, <8 x i16> noundef %c) #1 {
// CHECK: [[LANE:%.*]] = extractelement <8 x i16> %c, i32 7
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0
@ -355,7 +355,7 @@ int32_t test_vqdmlalh_laneq_s16(int32_t a, int16_t b, int16x8_t c) {
return vqdmlalh_laneq_s16(a, b, c, 7);
}
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_laneq_s32(i64 %a, i32 %b, <4 x i32> %c) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlals_laneq_s32(i64 noundef %a, i32 noundef %b, <4 x i32> noundef %c) #1 {
// CHECK: [[LANE:%.*]] = extractelement <4 x i32> %c, i32 3
// CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]])
// CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %a, i64 [[VQDMLXL]])
@ -364,7 +364,7 @@ int64_t test_vqdmlals_laneq_s32(int64_t a, int32_t b, int32x4_t c) {
return vqdmlals_laneq_s32(a, b, c, 3);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_lane_s16(i32 %a, i16 %b, <4 x i16> %c) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_lane_s16(i32 noundef %a, i16 noundef %b, <4 x i16> noundef %c) #0 {
// CHECK: [[LANE:%.*]] = extractelement <4 x i16> %c, i32 3
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0
@ -376,7 +376,7 @@ int32_t test_vqdmlslh_lane_s16(int32_t a, int16_t b, int16x4_t c) {
return vqdmlslh_lane_s16(a, b, c, 3);
}
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_lane_s32(i64 %a, i32 %b, <2 x i32> %c) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_lane_s32(i64 noundef %a, i32 noundef %b, <2 x i32> noundef %c) #0 {
// CHECK: [[LANE:%.*]] = extractelement <2 x i32> %c, i32 1
// CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]])
// CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %a, i64 [[VQDMLXL]])
@ -385,7 +385,7 @@ int64_t test_vqdmlsls_lane_s32(int64_t a, int32_t b, int32x2_t c) {
return vqdmlsls_lane_s32(a, b, c, 1);
}
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_laneq_s16(i32 %a, i16 %b, <8 x i16> %c) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vqdmlslh_laneq_s16(i32 noundef %a, i16 noundef %b, <8 x i16> noundef %c) #1 {
// CHECK: [[LANE:%.*]] = extractelement <8 x i16> %c, i32 7
// CHECK: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 %b, i64 0
// CHECK: [[TMP3:%.*]] = insertelement <4 x i16> undef, i16 [[LANE]], i64 0
@ -397,7 +397,7 @@ int32_t test_vqdmlslh_laneq_s16(int32_t a, int16_t b, int16x8_t c) {
return vqdmlslh_laneq_s16(a, b, c, 7);
}
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_laneq_s32(i64 %a, i32 %b, <4 x i32> %c) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vqdmlsls_laneq_s32(i64 noundef %a, i32 noundef %b, <4 x i32> noundef %c) #1 {
// CHECK: [[LANE:%.*]] = extractelement <4 x i32> %c, i32 3
// CHECK: [[VQDMLXL:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %b, i32 [[LANE]])
// CHECK: [[VQDMLXL1:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %a, i64 [[VQDMLXL]])

144
clang/test/CodeGen/aarch64-neon-tbl.c
View File

@ -5,7 +5,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL11_I]]
@ -13,14 +13,14 @@ int8x8_t test_vtbl1_s8(int8x8_t a, int8x8_t b) {
return vtbl1_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_s8(<16 x i8> %a, <8 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_s8(<16 x i8> noundef %a, <8 x i8> noundef %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL1_I]]
int8x8_t test_vqtbl1_s8(int8x16_t a, uint8x8_t b) {
return vqtbl1_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_s8([2 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x8x2_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.int8x8x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[A]], i32 0, i32 0
@ -42,7 +42,7 @@ int8x8_t test_vtbl2_s8(int8x8x2_t a, int8x8_t b) {
return vtbl2_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_s8([2 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[A]], i32 0, i32 0
@ -63,7 +63,7 @@ int8x8_t test_vqtbl2_s8(int8x16x2_t a, uint8x8_t b) {
return vqtbl2_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_s8([3 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x8x3_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.int8x8x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[A]], i32 0, i32 0
@ -89,7 +89,7 @@ int8x8_t test_vtbl3_s8(int8x8x3_t a, int8x8_t b) {
return vtbl3_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_s8([3 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[A]], i32 0, i32 0
@ -113,7 +113,7 @@ int8x8_t test_vqtbl3_s8(int8x16x3_t a, uint8x8_t b) {
return vqtbl3_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_s8([4 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x8x4_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.int8x8x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[A]], i32 0, i32 0
@ -142,7 +142,7 @@ int8x8_t test_vtbl4_s8(int8x8x4_t a, int8x8_t b) {
return vtbl4_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_s8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_s8([4 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[A]], i32 0, i32 0
@ -169,14 +169,14 @@ int8x8_t test_vqtbl4_s8(int8x16x4_t a, uint8x8_t b) {
return vqtbl4_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %a, <16 x i8> %b) #3
// CHECK: ret <16 x i8> [[VTBL1_I]]
int8x16_t test_vqtbl1q_s8(int8x16_t a, int8x16_t b) {
return vqtbl1q_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_s8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_s8([2 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[A]], i32 0, i32 0
@ -197,7 +197,7 @@ int8x16_t test_vqtbl2q_s8(int8x16x2_t a, int8x16_t b) {
return vqtbl2q_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_s8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_s8([3 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[A]], i32 0, i32 0
@ -221,7 +221,7 @@ int8x16_t test_vqtbl3q_s8(int8x16x3_t a, int8x16_t b) {
return vqtbl3q_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_s8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_s8([4 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[A]], i32 0, i32 0
@ -248,7 +248,7 @@ int8x16_t test_vqtbl4q_s8(int8x16x4_t a, int8x16_t b) {
return vqtbl4q_s8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_s8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_s8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
// CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %c) #3
// CHECK: [[TMP0:%.*]] = icmp uge <8 x i8> %c, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
@ -262,7 +262,7 @@ int8x8_t test_vtbx1_s8(int8x8_t a, int8x8_t b, int8x8_t c) {
return vtbx1_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_s8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_s8(<8 x i8> noundef %a, [2 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x8x2_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.int8x8x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x2_t, %struct.int8x8x2_t* [[B]], i32 0, i32 0
@ -284,7 +284,7 @@ int8x8_t test_vtbx2_s8(int8x8_t a, int8x8x2_t b, int8x8_t c) {
return vtbx2_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_s8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_s8(<8 x i8> noundef %a, [3 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x8x3_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.int8x8x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x3_t, %struct.int8x8x3_t* [[B]], i32 0, i32 0
@ -316,7 +316,7 @@ int8x8_t test_vtbx3_s8(int8x8_t a, int8x8x3_t b, int8x8_t c) {
return vtbx3_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_s8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_s8(<8 x i8> noundef %a, [4 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x8x4_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.int8x8x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x8x4_t, %struct.int8x8x4_t* [[B]], i32 0, i32 0
@ -345,14 +345,14 @@ int8x8_t test_vtbx4_s8(int8x8_t a, int8x8x4_t b, int8x8_t c) {
return vtbx4_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_s8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_s8(<8 x i8> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3
// CHECK: ret <8 x i8> [[VTBX1_I]]
int8x8_t test_vqtbx1_s8(int8x8_t a, int8x16_t b, uint8x8_t c) {
return vqtbx1_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_s8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_s8(<8 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[B]], i32 0, i32 0
@ -373,7 +373,7 @@ int8x8_t test_vqtbx2_s8(int8x8_t a, int8x16x2_t b, uint8x8_t c) {
return vqtbx2_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_s8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_s8(<8 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[B]], i32 0, i32 0
@ -397,7 +397,7 @@ int8x8_t test_vqtbx3_s8(int8x8_t a, int8x16x3_t b, uint8x8_t c) {
return vqtbx3_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_s8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_s8(<8 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[B]], i32 0, i32 0
@ -424,14 +424,14 @@ int8x8_t test_vqtbx4_s8(int8x8_t a, int8x16x4_t b, uint8x8_t c) {
return vqtbx4_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_s8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_s8(<16 x i8> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3
// CHECK: ret <16 x i8> [[VTBX1_I]]
int8x16_t test_vqtbx1q_s8(int8x16_t a, int8x16_t b, uint8x16_t c) {
return vqtbx1q_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_s8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_s8(<16 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.int8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x2_t, %struct.int8x16x2_t* [[B]], i32 0, i32 0
@ -452,7 +452,7 @@ int8x16_t test_vqtbx2q_s8(int8x16_t a, int8x16x2_t b, int8x16_t c) {
return vqtbx2q_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_s8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_s8(<16 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.int8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x3_t, %struct.int8x16x3_t* [[B]], i32 0, i32 0
@ -476,7 +476,7 @@ int8x16_t test_vqtbx3q_s8(int8x16_t a, int8x16x3_t b, int8x16_t c) {
return vqtbx3q_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_s8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_s8(<16 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.int8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.int8x16x4_t, %struct.int8x16x4_t* [[B]], i32 0, i32 0
@ -503,7 +503,7 @@ int8x16_t test_vqtbx4q_s8(int8x16_t a, int8x16x4_t b, int8x16_t c) {
return vqtbx4q_s8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL11_I]]
@ -511,14 +511,14 @@ uint8x8_t test_vtbl1_u8(uint8x8_t a, uint8x8_t b) {
return vtbl1_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_u8(<16 x i8> %a, <8 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_u8(<16 x i8> noundef %a, <8 x i8> noundef %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL1_I]]
uint8x8_t test_vqtbl1_u8(uint8x16_t a, uint8x8_t b) {
return vqtbl1_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_u8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_u8([2 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x8x2_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.uint8x8x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[A]], i32 0, i32 0
@ -540,7 +540,7 @@ uint8x8_t test_vtbl2_u8(uint8x8x2_t a, uint8x8_t b) {
return vtbl2_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_u8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_u8([2 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[A]], i32 0, i32 0
@ -561,7 +561,7 @@ uint8x8_t test_vqtbl2_u8(uint8x16x2_t a, uint8x8_t b) {
return vqtbl2_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_u8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_u8([3 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x8x3_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.uint8x8x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[A]], i32 0, i32 0
@ -587,7 +587,7 @@ uint8x8_t test_vtbl3_u8(uint8x8x3_t a, uint8x8_t b) {
return vtbl3_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_u8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_u8([3 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[A]], i32 0, i32 0
@ -611,7 +611,7 @@ uint8x8_t test_vqtbl3_u8(uint8x16x3_t a, uint8x8_t b) {
return vqtbl3_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_u8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_u8([4 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x8x4_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.uint8x8x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[A]], i32 0, i32 0
@ -640,7 +640,7 @@ uint8x8_t test_vtbl4_u8(uint8x8x4_t a, uint8x8_t b) {
return vtbl4_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_u8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_u8([4 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[A]], i32 0, i32 0
@ -667,14 +667,14 @@ uint8x8_t test_vqtbl4_u8(uint8x16x4_t a, uint8x8_t b) {
return vqtbl4_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %a, <16 x i8> %b) #3
// CHECK: ret <16 x i8> [[VTBL1_I]]
uint8x16_t test_vqtbl1q_u8(uint8x16_t a, uint8x16_t b) {
return vqtbl1q_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_u8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_u8([2 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[A]], i32 0, i32 0
@ -695,7 +695,7 @@ uint8x16_t test_vqtbl2q_u8(uint8x16x2_t a, uint8x16_t b) {
return vqtbl2q_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_u8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_u8([3 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[A]], i32 0, i32 0
@ -719,7 +719,7 @@ uint8x16_t test_vqtbl3q_u8(uint8x16x3_t a, uint8x16_t b) {
return vqtbl3q_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_u8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_u8([4 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[A]], i32 0, i32 0
@ -746,7 +746,7 @@ uint8x16_t test_vqtbl4q_u8(uint8x16x4_t a, uint8x16_t b) {
return vqtbl4q_u8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_u8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
// CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %c) #3
// CHECK: [[TMP0:%.*]] = icmp uge <8 x i8> %c, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
@ -760,7 +760,7 @@ uint8x8_t test_vtbx1_u8(uint8x8_t a, uint8x8_t b, uint8x8_t c) {
return vtbx1_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_u8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_u8(<8 x i8> noundef %a, [2 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x8x2_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.uint8x8x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x2_t, %struct.uint8x8x2_t* [[B]], i32 0, i32 0
@ -782,7 +782,7 @@ uint8x8_t test_vtbx2_u8(uint8x8_t a, uint8x8x2_t b, uint8x8_t c) {
return vtbx2_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_u8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_u8(<8 x i8> noundef %a, [3 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x8x3_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.uint8x8x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x3_t, %struct.uint8x8x3_t* [[B]], i32 0, i32 0
@ -814,7 +814,7 @@ uint8x8_t test_vtbx3_u8(uint8x8_t a, uint8x8x3_t b, uint8x8_t c) {
return vtbx3_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_u8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_u8(<8 x i8> noundef %a, [4 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x8x4_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.uint8x8x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x8x4_t, %struct.uint8x8x4_t* [[B]], i32 0, i32 0
@ -843,14 +843,14 @@ uint8x8_t test_vtbx4_u8(uint8x8_t a, uint8x8x4_t b, uint8x8_t c) {
return vtbx4_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_u8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_u8(<8 x i8> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3
// CHECK: ret <8 x i8> [[VTBX1_I]]
uint8x8_t test_vqtbx1_u8(uint8x8_t a, uint8x16_t b, uint8x8_t c) {
return vqtbx1_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_u8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_u8(<8 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[B]], i32 0, i32 0
@ -871,7 +871,7 @@ uint8x8_t test_vqtbx2_u8(uint8x8_t a, uint8x16x2_t b, uint8x8_t c) {
return vqtbx2_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_u8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_u8(<8 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[B]], i32 0, i32 0
@ -895,7 +895,7 @@ uint8x8_t test_vqtbx3_u8(uint8x8_t a, uint8x16x3_t b, uint8x8_t c) {
return vqtbx3_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_u8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_u8(<8 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[B]], i32 0, i32 0
@ -922,14 +922,14 @@ uint8x8_t test_vqtbx4_u8(uint8x8_t a, uint8x16x4_t b, uint8x8_t c) {
return vqtbx4_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_u8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_u8(<16 x i8> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3
// CHECK: ret <16 x i8> [[VTBX1_I]]
uint8x16_t test_vqtbx1q_u8(uint8x16_t a, uint8x16_t b, uint8x16_t c) {
return vqtbx1q_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_u8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_u8(<16 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.uint8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x2_t, %struct.uint8x16x2_t* [[B]], i32 0, i32 0
@ -950,7 +950,7 @@ uint8x16_t test_vqtbx2q_u8(uint8x16_t a, uint8x16x2_t b, uint8x16_t c) {
return vqtbx2q_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_u8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_u8(<16 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.uint8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x3_t, %struct.uint8x16x3_t* [[B]], i32 0, i32 0
@ -974,7 +974,7 @@ uint8x16_t test_vqtbx3q_u8(uint8x16_t a, uint8x16x3_t b, uint8x16_t c) {
return vqtbx3q_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_u8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_u8(<16 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.uint8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.uint8x16x4_t, %struct.uint8x16x4_t* [[B]], i32 0, i32 0
@ -1001,7 +1001,7 @@ uint8x16_t test_vqtbx4q_u8(uint8x16_t a, uint8x16x4_t b, uint8x16_t c) {
return vqtbx4q_u8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_p8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl1_p8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %a, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL11_I]]
@ -1009,14 +1009,14 @@ poly8x8_t test_vtbl1_p8(poly8x8_t a, uint8x8_t b) {
return vtbl1_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_p8(<16 x i8> %a, <8 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl1_p8(<16 x i8> noundef %a, <8 x i8> noundef %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> %a, <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL1_I]]
poly8x8_t test_vqtbl1_p8(poly8x16_t a, uint8x8_t b) {
return vqtbl1_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_p8([2 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl2_p8([2 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x8x2_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.poly8x8x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[A]], i32 0, i32 0
@ -1038,7 +1038,7 @@ poly8x8_t test_vtbl2_p8(poly8x8x2_t a, uint8x8_t b) {
return vtbl2_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_p8([2 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl2_p8([2 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[A]], i32 0, i32 0
@ -1059,7 +1059,7 @@ poly8x8_t test_vqtbl2_p8(poly8x16x2_t a, uint8x8_t b) {
return vqtbl2_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_p8([3 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl3_p8([3 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x8x3_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.poly8x8x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[A]], i32 0, i32 0
@ -1085,7 +1085,7 @@ poly8x8_t test_vtbl3_p8(poly8x8x3_t a, uint8x8_t b) {
return vtbl3_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_p8([3 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl3_p8([3 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[A]], i32 0, i32 0
@ -1109,7 +1109,7 @@ poly8x8_t test_vqtbl3_p8(poly8x16x3_t a, uint8x8_t b) {
return vqtbl3_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_p8([4 x <8 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbl4_p8([4 x <8 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x8x4_t, align 8
// CHECK: [[A:%.*]] = alloca %struct.poly8x8x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[A]], i32 0, i32 0
@ -1138,7 +1138,7 @@ poly8x8_t test_vtbl4_p8(poly8x8x4_t a, uint8x8_t b) {
return vtbl4_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_p8([4 x <16 x i8>] %a.coerce, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbl4_p8([4 x <16 x i8>] %a.coerce, <8 x i8> noundef %b) #0 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[A]], i32 0, i32 0
@ -1165,14 +1165,14 @@ poly8x8_t test_vqtbl4_p8(poly8x16x4_t a, uint8x8_t b) {
return vqtbl4_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_p8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl1q_p8(<16 x i8> noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> %a, <16 x i8> %b) #3
// CHECK: ret <16 x i8> [[VTBL1_I]]
poly8x16_t test_vqtbl1q_p8(poly8x16_t a, uint8x16_t b) {
return vqtbl1q_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_p8([2 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl2q_p8([2 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[A]], i32 0, i32 0
@ -1193,7 +1193,7 @@ poly8x16_t test_vqtbl2q_p8(poly8x16x2_t a, uint8x16_t b) {
return vqtbl2q_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_p8([3 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl3q_p8([3 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[A]], i32 0, i32 0
@ -1217,7 +1217,7 @@ poly8x16_t test_vqtbl3q_p8(poly8x16x3_t a, uint8x16_t b) {
return vqtbl3q_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_p8([4 x <16 x i8>] %a.coerce, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbl4q_p8([4 x <16 x i8>] %a.coerce, <16 x i8> noundef %b) #1 {
// CHECK: [[__P0_I:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[A:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[A]], i32 0, i32 0
@ -1244,7 +1244,7 @@ poly8x16_t test_vqtbl4q_p8(poly8x16x4_t a, uint8x16_t b) {
return vqtbl4q_p8(a, b);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_p8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx1_p8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) #0 {
// CHECK: [[VTBL1_I:%.*]] = shufflevector <8 x i8> %b, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> %c) #3
// CHECK: [[TMP0:%.*]] = icmp uge <8 x i8> %c, <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
@ -1258,7 +1258,7 @@ poly8x8_t test_vtbx1_p8(poly8x8_t a, poly8x8_t b, uint8x8_t c) {
return vtbx1_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_p8(<8 x i8> %a, [2 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx2_p8(<8 x i8> noundef %a, [2 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x8x2_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.poly8x8x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x2_t, %struct.poly8x8x2_t* [[B]], i32 0, i32 0
@ -1280,7 +1280,7 @@ poly8x8_t test_vtbx2_p8(poly8x8_t a, poly8x8x2_t b, uint8x8_t c) {
return vtbx2_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_p8(<8 x i8> %a, [3 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx3_p8(<8 x i8> noundef %a, [3 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x8x3_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.poly8x8x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x3_t, %struct.poly8x8x3_t* [[B]], i32 0, i32 0
@ -1312,7 +1312,7 @@ poly8x8_t test_vtbx3_p8(poly8x8_t a, poly8x8x3_t b, uint8x8_t c) {
return vtbx3_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_p8(<8 x i8> %a, [4 x <8 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vtbx4_p8(<8 x i8> noundef %a, [4 x <8 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x8x4_t, align 8
// CHECK: [[B:%.*]] = alloca %struct.poly8x8x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x8x4_t, %struct.poly8x8x4_t* [[B]], i32 0, i32 0
@ -1341,14 +1341,14 @@ poly8x8_t test_vtbx4_p8(poly8x8_t a, poly8x8x4_t b, uint8x8_t c) {
return vtbx4_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_p8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx1_p8(<8 x i8> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x i8> %a, <16 x i8> %b, <8 x i8> %c) #3
// CHECK: ret <8 x i8> [[VTBX1_I]]
poly8x8_t test_vqtbx1_p8(poly8x8_t a, uint8x16_t b, uint8x8_t c) {
return vqtbx1_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_p8(<8 x i8> %a, [2 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx2_p8(<8 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[B]], i32 0, i32 0
@ -1369,7 +1369,7 @@ poly8x8_t test_vqtbx2_p8(poly8x8_t a, poly8x16x2_t b, uint8x8_t c) {
return vqtbx2_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_p8(<8 x i8> %a, [3 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx3_p8(<8 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[B]], i32 0, i32 0
@ -1393,7 +1393,7 @@ poly8x8_t test_vqtbx3_p8(poly8x8_t a, poly8x16x3_t b, uint8x8_t c) {
return vqtbx3_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_p8(<8 x i8> %a, [4 x <16 x i8>] %b.coerce, <8 x i8> %c) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vqtbx4_p8(<8 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <8 x i8> noundef %c) #0 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[B]], i32 0, i32 0
@ -1420,14 +1420,14 @@ poly8x8_t test_vqtbx4_p8(poly8x8_t a, poly8x16x4_t b, uint8x8_t c) {
return vqtbx4_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_p8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx1q_p8(<16 x i8> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbx1.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) #3
// CHECK: ret <16 x i8> [[VTBX1_I]]
poly8x16_t test_vqtbx1q_p8(poly8x16_t a, uint8x16_t b, uint8x16_t c) {
return vqtbx1q_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_p8(<16 x i8> %a, [2 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx2q_p8(<16 x i8> noundef %a, [2 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.poly8x16x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x2_t, %struct.poly8x16x2_t* [[B]], i32 0, i32 0
@ -1448,7 +1448,7 @@ poly8x16_t test_vqtbx2q_p8(poly8x16_t a, poly8x16x2_t b, uint8x16_t c) {
return vqtbx2q_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_p8(<16 x i8> %a, [3 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx3q_p8(<16 x i8> noundef %a, [3 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.poly8x16x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x3_t, %struct.poly8x16x3_t* [[B]], i32 0, i32 0
@ -1472,7 +1472,7 @@ poly8x16_t test_vqtbx3q_p8(poly8x16_t a, poly8x16x3_t b, uint8x16_t c) {
return vqtbx3q_p8(a, b, c);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_p8(<16 x i8> %a, [4 x <16 x i8>] %b.coerce, <16 x i8> %c) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vqtbx4q_p8(<16 x i8> noundef %a, [4 x <16 x i8>] %b.coerce, <16 x i8> noundef %c) #1 {
// CHECK: [[__P1_I:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[B:%.*]] = alloca %struct.poly8x16x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly8x16x4_t, %struct.poly8x16x4_t* [[B]], i32 0, i32 0

28
clang/test/CodeGen/aarch64-neon-vcombine.c
View File

@ -4,98 +4,98 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_s8(<8 x i8> %low, <8 x i8> %high) #0 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_s8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: ret <16 x i8> [[SHUFFLE_I]]
int8x16_t test_vcombine_s8(int8x8_t low, int8x8_t high) {
return vcombine_s8(low, high);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_s16(<4 x i16> %low, <4 x i16> %high) #0 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_s16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x i16> [[SHUFFLE_I]]
int16x8_t test_vcombine_s16(int16x4_t low, int16x4_t high) {
return vcombine_s16(low, high);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_s32(<2 x i32> %low, <2 x i32> %high) #0 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_s32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> %low, <2 x i32> %high, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x i32> [[SHUFFLE_I]]
int32x4_t test_vcombine_s32(int32x2_t low, int32x2_t high) {
return vcombine_s32(low, high);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_s64(<1 x i64> %low, <1 x i64> %high) #0 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_s64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
int64x2_t test_vcombine_s64(int64x1_t low, int64x1_t high) {
return vcombine_s64(low, high);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_u8(<8 x i8> %low, <8 x i8> %high) #0 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_u8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: ret <16 x i8> [[SHUFFLE_I]]
uint8x16_t test_vcombine_u8(uint8x8_t low, uint8x8_t high) {
return vcombine_u8(low, high);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_u16(<4 x i16> %low, <4 x i16> %high) #0 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_u16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x i16> [[SHUFFLE_I]]
uint16x8_t test_vcombine_u16(uint16x4_t low, uint16x4_t high) {
return vcombine_u16(low, high);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_u32(<2 x i32> %low, <2 x i32> %high) #0 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vcombine_u32(<2 x i32> noundef %low, <2 x i32> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> %low, <2 x i32> %high, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x i32> [[SHUFFLE_I]]
uint32x4_t test_vcombine_u32(uint32x2_t low, uint32x2_t high) {
return vcombine_u32(low, high);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_u64(<1 x i64> %low, <1 x i64> %high) #0 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_u64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
uint64x2_t test_vcombine_u64(uint64x1_t low, uint64x1_t high) {
return vcombine_u64(low, high);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> %low, <1 x i64> %high) #0 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) {
return vcombine_p64(low, high);
}
// CHECK-LABEL: define{{.*}} <8 x half> @test_vcombine_f16(<4 x half> %low, <4 x half> %high) #0 {
// CHECK-LABEL: define{{.*}} <8 x half> @test_vcombine_f16(<4 x half> noundef %low, <4 x half> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x half> %low, <4 x half> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x half> [[SHUFFLE_I]]
float16x8_t test_vcombine_f16(float16x4_t low, float16x4_t high) {
return vcombine_f16(low, high);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vcombine_f32(<2 x float> %low, <2 x float> %high) #0 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vcombine_f32(<2 x float> noundef %low, <2 x float> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x float> %low, <2 x float> %high, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x float> [[SHUFFLE_I]]
float32x4_t test_vcombine_f32(float32x2_t low, float32x2_t high) {
return vcombine_f32(low, high);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_p8(<8 x i8> %low, <8 x i8> %high) #0 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vcombine_p8(<8 x i8> noundef %low, <8 x i8> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> %low, <8 x i8> %high, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: ret <16 x i8> [[SHUFFLE_I]]
poly8x16_t test_vcombine_p8(poly8x8_t low, poly8x8_t high) {
return vcombine_p8(low, high);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_p16(<4 x i16> %low, <4 x i16> %high) #0 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vcombine_p16(<4 x i16> noundef %low, <4 x i16> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> %low, <4 x i16> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x i16> [[SHUFFLE_I]]
poly16x8_t test_vcombine_p16(poly16x4_t low, poly16x4_t high) {
return vcombine_p16(low, high);
}
// CHECK-LABEL: define{{.*}} <2 x double> @test_vcombine_f64(<1 x double> %low, <1 x double> %high) #0 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vcombine_f64(<1 x double> noundef %low, <1 x double> noundef %high) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x double> %low, <1 x double> %high, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x double> [[SHUFFLE_I]]
float64x2_t test_vcombine_f64(float64x1_t low, float64x1_t high) {

56
clang/test/CodeGen/aarch64-neon-vget-hilo.c
View File

@ -6,196 +6,196 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_s8(<16 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_s8(<16 x i8> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: ret <8 x i8> [[SHUFFLE_I]]
int8x8_t test_vget_high_s8(int8x16_t a) {
return vget_high_s8(a);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_s16(<8 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_s16(<8 x i16> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <4 x i16> [[SHUFFLE_I]]
int16x4_t test_vget_high_s16(int16x8_t a) {
return vget_high_s16(a);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_s32(<4 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_s32(<4 x i32> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
// CHECK: ret <2 x i32> [[SHUFFLE_I]]
int32x2_t test_vget_high_s32(int32x4_t a) {
return vget_high_s32(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_s64(<2 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_s64(<2 x i64> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
// CHECK: ret <1 x i64> [[SHUFFLE_I]]
int64x1_t test_vget_high_s64(int64x2_t a) {
return vget_high_s64(a);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_u8(<16 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_u8(<16 x i8> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: ret <8 x i8> [[SHUFFLE_I]]
uint8x8_t test_vget_high_u8(uint8x16_t a) {
return vget_high_u8(a);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_u16(<8 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_u16(<8 x i16> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <4 x i16> [[SHUFFLE_I]]
uint16x4_t test_vget_high_u16(uint16x8_t a) {
return vget_high_u16(a);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_u32(<4 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_high_u32(<4 x i32> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
// CHECK: ret <2 x i32> [[SHUFFLE_I]]
uint32x2_t test_vget_high_u32(uint32x4_t a) {
return vget_high_u32(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_u64(<2 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_u64(<2 x i64> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
// CHECK: ret <1 x i64> [[SHUFFLE_I]]
uint64x1_t test_vget_high_u64(uint64x2_t a) {
return vget_high_u64(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_p64(<2 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_high_p64(<2 x i64> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
// CHECK: ret <1 x i64> [[SHUFFLE_I]]
poly64x1_t test_vget_high_p64(poly64x2_t a) {
return vget_high_p64(a);
}
// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_high_f16(<8 x half> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_high_f16(<8 x half> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <4 x half> [[SHUFFLE_I]]
float16x4_t test_vget_high_f16(float16x8_t a) {
return vget_high_f16(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_high_f32(<4 x float> %a) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_high_f32(<4 x float> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
float32x2_t test_vget_high_f32(float32x4_t a) {
return vget_high_f32(a);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_p8(<16 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_high_p8(<16 x i8> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: ret <8 x i8> [[SHUFFLE_I]]
poly8x8_t test_vget_high_p8(poly8x16_t a) {
return vget_high_p8(a);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_p16(<8 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_high_p16(<8 x i16> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <4 x i16> [[SHUFFLE_I]]
poly16x4_t test_vget_high_p16(poly16x8_t a) {
return vget_high_p16(a);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_high_f64(<2 x double> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_high_f64(<2 x double> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> <i32 1>
// CHECK: ret <1 x double> [[SHUFFLE_I]]
float64x1_t test_vget_high_f64(float64x2_t a) {
return vget_high_f64(a);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_s8(<16 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_s8(<16 x i8> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x i8> [[SHUFFLE_I]]
int8x8_t test_vget_low_s8(int8x16_t a) {
return vget_low_s8(a);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_s16(<8 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_s16(<8 x i16> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x i16> [[SHUFFLE_I]]
int16x4_t test_vget_low_s16(int16x8_t a) {
return vget_low_s16(a);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_s32(<4 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_s32(<4 x i32> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x i32> [[SHUFFLE_I]]
int32x2_t test_vget_low_s32(int32x4_t a) {
return vget_low_s32(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_s64(<2 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_s64(<2 x i64> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> zeroinitializer
// CHECK: ret <1 x i64> [[SHUFFLE_I]]
int64x1_t test_vget_low_s64(int64x2_t a) {
return vget_low_s64(a);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_u8(<16 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_u8(<16 x i8> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x i8> [[SHUFFLE_I]]
uint8x8_t test_vget_low_u8(uint8x16_t a) {
return vget_low_u8(a);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_u16(<8 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_u16(<8 x i16> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x i16> [[SHUFFLE_I]]
uint16x4_t test_vget_low_u16(uint16x8_t a) {
return vget_low_u16(a);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_u32(<4 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vget_low_u32(<4 x i32> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x i32> [[SHUFFLE_I]]
uint32x2_t test_vget_low_u32(uint32x4_t a) {
return vget_low_u32(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_u64(<2 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_u64(<2 x i64> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> zeroinitializer
// CHECK: ret <1 x i64> [[SHUFFLE_I]]
uint64x1_t test_vget_low_u64(uint64x2_t a) {
return vget_low_u64(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_p64(<2 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vget_low_p64(<2 x i64> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> zeroinitializer
// CHECK: ret <1 x i64> [[SHUFFLE_I]]
poly64x1_t test_vget_low_p64(poly64x2_t a) {
return vget_low_p64(a);
}
// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_low_f16(<8 x half> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x half> @test_vget_low_f16(<8 x half> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x half> [[SHUFFLE_I]]
float16x4_t test_vget_low_f16(float16x8_t a) {
return vget_low_f16(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_low_f32(<4 x float> %a) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vget_low_f32(<4 x float> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
float32x2_t test_vget_low_f32(float32x4_t a) {
return vget_low_f32(a);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_p8(<16 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vget_low_p8(<16 x i8> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK: ret <8 x i8> [[SHUFFLE_I]]
poly8x8_t test_vget_low_p8(poly8x16_t a) {
return vget_low_p8(a);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_p16(<8 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vget_low_p16(<8 x i16> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK: ret <4 x i16> [[SHUFFLE_I]]
poly16x4_t test_vget_low_p16(poly16x8_t a) {
return vget_low_p16(a);
}
// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_low_f64(<2 x double> %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vget_low_f64(<2 x double> noundef %a) #0 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x double> %a, <2 x double> %a, <1 x i32> zeroinitializer
// CHECK: ret <1 x double> [[SHUFFLE_I]]
float64x1_t test_vget_low_f64(float64x2_t a) {

96
clang/test/CodeGen/aarch64-neon-vget.c
View File

@ -6,70 +6,70 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_u8(<8 x i8> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
// CHECK: ret i8 [[VGET_LANE]]
uint8_t test_vget_lane_u8(uint8x8_t a) {
return vget_lane_u8(a, 7);
}
// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_u16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_u16(<4 x i16> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
// CHECK: ret i16 [[VGET_LANE]]
uint16_t test_vget_lane_u16(uint16x4_t a) {
return vget_lane_u16(a, 3);
}
// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_u32(<2 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_u32(<2 x i32> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
// CHECK: ret i32 [[VGET_LANE]]
uint32_t test_vget_lane_u32(uint32x2_t a) {
return vget_lane_u32(a, 1);
}
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_s8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_s8(<8 x i8> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
// CHECK: ret i8 [[VGET_LANE]]
int8_t test_vget_lane_s8(int8x8_t a) {
return vget_lane_s8(a, 7);
}
// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_s16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_s16(<4 x i16> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
// CHECK: ret i16 [[VGET_LANE]]
int16_t test_vget_lane_s16(int16x4_t a) {
return vget_lane_s16(a, 3);
}
// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_s32(<2 x i32> %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vget_lane_s32(<2 x i32> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x i32> %a, i32 1
// CHECK: ret i32 [[VGET_LANE]]
int32_t test_vget_lane_s32(int32x2_t a) {
return vget_lane_s32(a, 1);
}
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_p8(<8 x i8> %a) #0 {
// CHECK-LABEL: define{{.*}} i8 @test_vget_lane_p8(<8 x i8> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <8 x i8> %a, i32 7
// CHECK: ret i8 [[VGET_LANE]]
poly8_t test_vget_lane_p8(poly8x8_t a) {
return vget_lane_p8(a, 7);
}
// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_p16(<4 x i16> %a) #0 {
// CHECK-LABEL: define{{.*}} i16 @test_vget_lane_p16(<4 x i16> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <4 x i16> %a, i32 3
// CHECK: ret i16 [[VGET_LANE]]
poly16_t test_vget_lane_p16(poly16x4_t a) {
return vget_lane_p16(a, 3);
}
// CHECK-LABEL: define{{.*}} float @test_vget_lane_f32(<2 x float> %a) #0 {
// CHECK-LABEL: define{{.*}} float @test_vget_lane_f32(<2 x float> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <2 x float> %a, i32 1
// CHECK: ret float [[VGET_LANE]]
float32_t test_vget_lane_f32(float32x2_t a) {
return vget_lane_f32(a, 1);
}
// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> %a) #0 {
// CHECK-LABEL: define{{.*}} float @test_vget_lane_f16(<4 x half> noundef %a) #0 {
// CHECK: [[__REINT_242:%.*]] = alloca <4 x half>, align 8
// CHECK: [[__REINT1_242:%.*]] = alloca i16, align 2
// CHECK: store <4 x half> %a, <4 x half>* [[__REINT_242]], align 8
@ -85,70 +85,70 @@ float32_t test_vget_lane_f16(float16x4_t a) {
return vget_lane_f16(a, 1);
}
// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
// CHECK: ret i8 [[VGETQ_LANE]]
uint8_t test_vgetq_lane_u8(uint8x16_t a) {
return vgetq_lane_u8(a, 15);
}
// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
// CHECK: ret i16 [[VGETQ_LANE]]
uint16_t test_vgetq_lane_u16(uint16x8_t a) {
return vgetq_lane_u16(a, 7);
}
// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
// CHECK: ret i32 [[VGETQ_LANE]]
uint32_t test_vgetq_lane_u32(uint32x4_t a) {
return vgetq_lane_u32(a, 3);
}
// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
// CHECK: ret i8 [[VGETQ_LANE]]
int8_t test_vgetq_lane_s8(int8x16_t a) {
return vgetq_lane_s8(a, 15);
}
// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
// CHECK: ret i16 [[VGETQ_LANE]]
int16_t test_vgetq_lane_s16(int16x8_t a) {
return vgetq_lane_s16(a, 7);
}
// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i32 @test_vgetq_lane_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x i32> %a, i32 3
// CHECK: ret i32 [[VGETQ_LANE]]
int32_t test_vgetq_lane_s32(int32x4_t a) {
return vgetq_lane_s32(a, 3);
}
// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_p8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i8 @test_vgetq_lane_p8(<16 x i8> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <16 x i8> %a, i32 15
// CHECK: ret i8 [[VGETQ_LANE]]
poly8_t test_vgetq_lane_p8(poly8x16_t a) {
return vgetq_lane_p8(a, 15);
}
// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_p16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i16 @test_vgetq_lane_p16(<8 x i16> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <8 x i16> %a, i32 7
// CHECK: ret i16 [[VGETQ_LANE]]
poly16_t test_vgetq_lane_p16(poly16x8_t a) {
return vgetq_lane_p16(a, 7);
}
// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f32(<4 x float> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <4 x float> %a, i32 3
// CHECK: ret float [[VGETQ_LANE]]
float32_t test_vgetq_lane_f32(float32x4_t a) {
return vgetq_lane_f32(a, 3);
}
// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> %a) #1 {
// CHECK-LABEL: define{{.*}} float @test_vgetq_lane_f16(<8 x half> noundef %a) #1 {
// CHECK: [[__REINT_244:%.*]] = alloca <8 x half>, align 16
// CHECK: [[__REINT1_244:%.*]] = alloca i16, align 2
// CHECK: store <8 x half> %a, <8 x half>* [[__REINT_244]], align 16
@ -164,28 +164,28 @@ float32_t test_vgetq_lane_f16(float16x8_t a) {
return vgetq_lane_f16(a, 3);
}
// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_s64(<1 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_s64(<1 x i64> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
// CHECK: ret i64 [[VGET_LANE]]
int64_t test_vget_lane_s64(int64x1_t a) {
return vget_lane_s64(a, 0);
}
// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_u64(<1 x i64> %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_u64(<1 x i64> noundef %a) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %a, i32 0
// CHECK: ret i64 [[VGET_LANE]]
uint64_t test_vget_lane_u64(uint64x1_t a) {
return vget_lane_u64(a, 0);
}
// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_s64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_s64(<2 x i64> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
// CHECK: ret i64 [[VGETQ_LANE]]
int64_t test_vgetq_lane_s64(int64x2_t a) {
return vgetq_lane_s64(a, 1);
}
// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_u64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_u64(<2 x i64> noundef %a) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %a, i32 1
// CHECK: ret i64 [[VGETQ_LANE]]
uint64_t test_vgetq_lane_u64(uint64x2_t a) {
@ -193,70 +193,70 @@ uint64_t test_vgetq_lane_u64(uint64x2_t a) {
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_u8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
uint8x8_t test_vset_lane_u8(uint8_t a, uint8x8_t b) {
return vset_lane_u8(a, b, 7);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_u16(i16 %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_u16(i16 noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3
// CHECK: ret <4 x i16> [[VSET_LANE]]
uint16x4_t test_vset_lane_u16(uint16_t a, uint16x4_t b) {
return vset_lane_u16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_u32(i32 %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_u32(i32 noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1
// CHECK: ret <2 x i32> [[VSET_LANE]]
uint32x2_t test_vset_lane_u32(uint32_t a, uint32x2_t b) {
return vset_lane_u32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_s8(i8 %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_s8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
int8x8_t test_vset_lane_s8(int8_t a, int8x8_t b) {
return vset_lane_s8(a, b, 7);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_s16(i16 %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_s16(i16 noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3
// CHECK: ret <4 x i16> [[VSET_LANE]]
int16x4_t test_vset_lane_s16(int16_t a, int16x4_t b) {
return vset_lane_s16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_s32(i32 %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vset_lane_s32(i32 noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i32> %b, i32 %a, i32 1
// CHECK: ret <2 x i32> [[VSET_LANE]]
int32x2_t test_vset_lane_s32(int32_t a, int32x2_t b) {
return vset_lane_s32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_p8(i8 %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vset_lane_p8(i8 noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i8> %b, i8 %a, i32 7
// CHECK: ret <8 x i8> [[VSET_LANE]]
poly8x8_t test_vset_lane_p8(poly8_t a, poly8x8_t b) {
return vset_lane_p8(a, b, 7);
}
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_p16(i16 %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vset_lane_p16(i16 noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i16> %b, i16 %a, i32 3
// CHECK: ret <4 x i16> [[VSET_LANE]]
poly16x4_t test_vset_lane_p16(poly16_t a, poly16x4_t b) {
return vset_lane_p16(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vset_lane_f32(float %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vset_lane_f32(float noundef %a, <2 x float> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x float> %b, float %a, i32 1
// CHECK: ret <2 x float> [[VSET_LANE]]
float32x2_t test_vset_lane_f32(float32_t a, float32x2_t b) {
return vset_lane_f32(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <4 x half> @test_vset_lane_f16(half* %a, <4 x half> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x half> @test_vset_lane_f16(half* noundef %a, <4 x half> noundef %b) #0 {
// CHECK: [[__REINT_246:%.*]] = alloca half, align 2
// CHECK: [[__REINT1_246:%.*]] = alloca <4 x half>, align 8
// CHECK: [[__REINT2_246:%.*]] = alloca <4 x i16>, align 8
@ -276,70 +276,70 @@ float16x4_t test_vset_lane_f16(float16_t *a, float16x4_t b) {
return vset_lane_f16(*a, b, 3);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_u8(i8 %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_u8(i8 noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15
// CHECK: ret <16 x i8> [[VSET_LANE]]
uint8x16_t test_vsetq_lane_u8(uint8_t a, uint8x16_t b) {
return vsetq_lane_u8(a, b, 15);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_u16(i16 %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_u16(i16 noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7
// CHECK: ret <8 x i16> [[VSET_LANE]]
uint16x8_t test_vsetq_lane_u16(uint16_t a, uint16x8_t b) {
return vsetq_lane_u16(a, b, 7);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_u32(i32 %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_u32(i32 noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3
// CHECK: ret <4 x i32> [[VSET_LANE]]
uint32x4_t test_vsetq_lane_u32(uint32_t a, uint32x4_t b) {
return vsetq_lane_u32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_s8(i8 %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_s8(i8 noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15
// CHECK: ret <16 x i8> [[VSET_LANE]]
int8x16_t test_vsetq_lane_s8(int8_t a, int8x16_t b) {
return vsetq_lane_s8(a, b, 15);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_s16(i16 %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_s16(i16 noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7
// CHECK: ret <8 x i16> [[VSET_LANE]]
int16x8_t test_vsetq_lane_s16(int16_t a, int16x8_t b) {
return vsetq_lane_s16(a, b, 7);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_s32(i32 %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vsetq_lane_s32(i32 noundef %a, <4 x i32> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x i32> %b, i32 %a, i32 3
// CHECK: ret <4 x i32> [[VSET_LANE]]
int32x4_t test_vsetq_lane_s32(int32_t a, int32x4_t b) {
return vsetq_lane_s32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_p8(i8 %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vsetq_lane_p8(i8 noundef %a, <16 x i8> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <16 x i8> %b, i8 %a, i32 15
// CHECK: ret <16 x i8> [[VSET_LANE]]
poly8x16_t test_vsetq_lane_p8(poly8_t a, poly8x16_t b) {
return vsetq_lane_p8(a, b, 15);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_p16(i16 %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vsetq_lane_p16(i16 noundef %a, <8 x i16> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <8 x i16> %b, i16 %a, i32 7
// CHECK: ret <8 x i16> [[VSET_LANE]]
poly16x8_t test_vsetq_lane_p16(poly16_t a, poly16x8_t b) {
return vsetq_lane_p16(a, b, 7);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vsetq_lane_f32(float %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vsetq_lane_f32(float noundef %a, <4 x float> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <4 x float> %b, float %a, i32 3
// CHECK: ret <4 x float> [[VSET_LANE]]
float32x4_t test_vsetq_lane_f32(float32_t a, float32x4_t b) {
return vsetq_lane_f32(a, b, 3);
}
// CHECK-LABEL: define{{.*}} <8 x half> @test_vsetq_lane_f16(half* %a, <8 x half> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x half> @test_vsetq_lane_f16(half* noundef %a, <8 x half> noundef %b) #1 {
// CHECK: [[__REINT_248:%.*]] = alloca half, align 2
// CHECK: [[__REINT1_248:%.*]] = alloca <8 x half>, align 16
// CHECK: [[__REINT2_248:%.*]] = alloca <8 x i16>, align 16
@ -359,28 +359,28 @@ float16x8_t test_vsetq_lane_f16(float16_t *a, float16x8_t b) {
return vsetq_lane_f16(*a, b, 7);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_s64(i64 %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_s64(i64 noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0
// CHECK: ret <1 x i64> [[VSET_LANE]]
int64x1_t test_vset_lane_s64(int64_t a, int64x1_t b) {
return vset_lane_s64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_u64(i64 %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_u64(i64 noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %b, i64 %a, i32 0
// CHECK: ret <1 x i64> [[VSET_LANE]]
uint64x1_t test_vset_lane_u64(uint64_t a, uint64x1_t b) {
return vset_lane_u64(a, b, 0);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_s64(i64 %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_s64(i64 noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1
// CHECK: ret <2 x i64> [[VSET_LANE]]
int64x2_t test_vsetq_lane_s64(int64_t a, int64x2_t b) {
return vsetq_lane_s64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_u64(i64 %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_u64(i64 noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %b, i64 %a, i32 1
// CHECK: ret <2 x i64> [[VSET_LANE]]
uint64x2_t test_vsetq_lane_u64(uint64_t a, uint64x2_t b) {

62
clang/test/CodeGen/aarch64-poly128.c
View File

@ -13,7 +13,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
// CHECK-LABEL: define{{.*}} void @test_vstrq_p128(i128* noundef %ptr, i128 noundef %val) #0 {
// CHECK: [[TMP0:%.*]] = bitcast i128* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i128*
// CHECK: store i128 %val, i128* [[TMP1]]
@ -23,7 +23,7 @@ void test_vstrq_p128(poly128_t * ptr, poly128_t val) {
}
// CHECK-LABEL: define{{.*}} i128 @test_vldrq_p128(i128* %ptr) #0 {
// CHECK-LABEL: define{{.*}} i128 @test_vldrq_p128(i128* noundef %ptr) #0 {
// CHECK: [[TMP0:%.*]] = bitcast i128* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i128*
// CHECK: [[TMP2:%.*]] = load i128, i128* [[TMP1]]
@ -33,7 +33,7 @@ poly128_t test_vldrq_p128(poly128_t * ptr) {
}
// CHECK-LABEL: define{{.*}} void @test_ld_st_p128(i128* %ptr) #0 {
// CHECK-LABEL: define{{.*}} void @test_ld_st_p128(i128* noundef %ptr) #0 {
// CHECK: [[TMP0:%.*]] = bitcast i128* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to i128*
// CHECK: [[TMP2:%.*]] = load i128, i128* [[TMP1]]
@ -47,7 +47,7 @@ void test_ld_st_p128(poly128_t * ptr) {
}
// CHECK-LABEL: define{{.*}} i128 @test_vmull_p64(i64 %a, i64 %b) #0 {
// CHECK-LABEL: define{{.*}} i128 @test_vmull_p64(i64 noundef %a, i64 noundef %b) #0 {
// CHECK: [[VMULL_P64_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %a, i64 %b) #3
// CHECK: [[VMULL_P641_I:%.*]] = bitcast <16 x i8> [[VMULL_P64_I]] to i128
// CHECK: ret i128 [[VMULL_P641_I]]
@ -55,7 +55,7 @@ poly128_t test_vmull_p64(poly64_t a, poly64_t b) {
return vmull_p64(a, b);
}
// CHECK-LABEL: define{{.*}} i128 @test_vmull_high_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vmull_high_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %a, <1 x i32> <i32 1>
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to i64
// CHECK: [[SHUFFLE_I7_I:%.*]] = shufflevector <2 x i64> %b, <2 x i64> %b, <1 x i32> <i32 1>
@ -67,182 +67,182 @@ poly128_t test_vmull_high_p64(poly64x2_t a, poly64x2_t b) {
return vmull_high_p64(a, b);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s8(<16 x i8> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <16 x i8> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_s8(int8x16_t a) {
return vreinterpretq_p128_s8(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s16(<8 x i16> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_s16(int16x8_t a) {
return vreinterpretq_p128_s16(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s32(<4 x i32> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_s32(int32x4_t a) {
return vreinterpretq_p128_s32(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_s64(<2 x i64> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_s64(int64x2_t a) {
return vreinterpretq_p128_s64(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u8(<16 x i8> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <16 x i8> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_u8(uint8x16_t a) {
return vreinterpretq_p128_u8(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u16(<8 x i16> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_u16(uint16x8_t a) {
return vreinterpretq_p128_u16(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u32(<4 x i32> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u32(<4 x i32> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_u32(uint32x4_t a) {
return vreinterpretq_p128_u32(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_u64(<2 x i64> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_u64(uint64x2_t a) {
return vreinterpretq_p128_u64(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f32(<4 x float> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f32(<4 x float> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_f32(float32x4_t a) {
return vreinterpretq_p128_f32(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f64(<2 x double> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_f64(<2 x double> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_f64(float64x2_t a) {
return vreinterpretq_p128_f64(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p8(<16 x i8> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p8(<16 x i8> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <16 x i8> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_p8(poly8x16_t a) {
return vreinterpretq_p128_p8(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p16(<8 x i16> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p16(<8 x i16> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_p16(poly16x8_t a) {
return vreinterpretq_p128_p16(a);
}
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p64(<2 x i64> %a) #1 {
// CHECK-LABEL: define{{.*}} i128 @test_vreinterpretq_p128_p64(<2 x i64> noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to i128
// CHECK: ret i128 [[TMP0]]
poly128_t test_vreinterpretq_p128_p64(poly64x2_t a) {
return vreinterpretq_p128_p64(a);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_s8_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_s8_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <16 x i8>
// CHECK: ret <16 x i8> [[TMP0]]
int8x16_t test_vreinterpretq_s8_p128(poly128_t a) {
return vreinterpretq_s8_p128(a);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_s16_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_s16_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <8 x i16>
// CHECK: ret <8 x i16> [[TMP0]]
int16x8_t test_vreinterpretq_s16_p128(poly128_t a) {
return vreinterpretq_s16_p128(a);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_s32_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_s32_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <4 x i32>
// CHECK: ret <4 x i32> [[TMP0]]
int32x4_t test_vreinterpretq_s32_p128(poly128_t a) {
return vreinterpretq_s32_p128(a);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_s64_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_s64_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x i64>
// CHECK: ret <2 x i64> [[TMP0]]
int64x2_t test_vreinterpretq_s64_p128(poly128_t a) {
return vreinterpretq_s64_p128(a);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_u8_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_u8_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <16 x i8>
// CHECK: ret <16 x i8> [[TMP0]]
uint8x16_t test_vreinterpretq_u8_p128(poly128_t a) {
return vreinterpretq_u8_p128(a);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_u16_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_u16_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <8 x i16>
// CHECK: ret <8 x i16> [[TMP0]]
uint16x8_t test_vreinterpretq_u16_p128(poly128_t a) {
return vreinterpretq_u16_p128(a);
}
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_u32_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vreinterpretq_u32_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <4 x i32>
// CHECK: ret <4 x i32> [[TMP0]]
uint32x4_t test_vreinterpretq_u32_p128(poly128_t a) {
return vreinterpretq_u32_p128(a);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_u64_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_u64_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x i64>
// CHECK: ret <2 x i64> [[TMP0]]
uint64x2_t test_vreinterpretq_u64_p128(poly128_t a) {
return vreinterpretq_u64_p128(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vreinterpretq_f32_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vreinterpretq_f32_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <4 x float>
// CHECK: ret <4 x float> [[TMP0]]
float32x4_t test_vreinterpretq_f32_p128(poly128_t a) {
return vreinterpretq_f32_p128(a);
}
// CHECK-LABEL: define{{.*}} <2 x double> @test_vreinterpretq_f64_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vreinterpretq_f64_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x double>
// CHECK: ret <2 x double> [[TMP0]]
float64x2_t test_vreinterpretq_f64_p128(poly128_t a) {
return vreinterpretq_f64_p128(a);
}
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_p8_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vreinterpretq_p8_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <16 x i8>
// CHECK: ret <16 x i8> [[TMP0]]
poly8x16_t test_vreinterpretq_p8_p128(poly128_t a) {
return vreinterpretq_p8_p128(a);
}
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_p16_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vreinterpretq_p16_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <8 x i16>
// CHECK: ret <8 x i16> [[TMP0]]
poly16x8_t test_vreinterpretq_p16_p128(poly128_t a) {
return vreinterpretq_p16_p128(a);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_p64_p128(i128 %a) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vreinterpretq_p64_p128(i128 noundef %a) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i128 %a to <2 x i64>
// CHECK: ret <2 x i64> [[TMP0]]
poly64x2_t test_vreinterpretq_p64_p128(poly128_t a) {

96
clang/test/CodeGen/aarch64-poly64.c
View File

@ -6,7 +6,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vceq_p64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vceq_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[CMP_I:%.*]] = icmp eq <1 x i64> %a, %b
// CHECK: [[SEXT_I:%.*]] = sext <1 x i1> [[CMP_I]] to <1 x i64>
// CHECK: ret <1 x i64> [[SEXT_I]]
@ -14,7 +14,7 @@ uint64x1_t test_vceq_p64(poly64x1_t a, poly64x1_t b) {
return vceq_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vceqq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vceqq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[CMP_I:%.*]] = icmp eq <2 x i64> %a, %b
// CHECK: [[SEXT_I:%.*]] = sext <2 x i1> [[CMP_I]] to <2 x i64>
// CHECK: ret <2 x i64> [[SEXT_I]]
@ -22,7 +22,7 @@ uint64x2_t test_vceqq_p64(poly64x2_t a, poly64x2_t b) {
return vceqq_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vtst_p64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vtst_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[TMP4:%.*]] = and <1 x i64> %a, %b
// CHECK: [[TMP5:%.*]] = icmp ne <1 x i64> [[TMP4]], zeroinitializer
// CHECK: [[VTST_I:%.*]] = sext <1 x i1> [[TMP5]] to <1 x i64>
@ -31,7 +31,7 @@ uint64x1_t test_vtst_p64(poly64x1_t a, poly64x1_t b) {
return vtst_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtstq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtstq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[TMP4:%.*]] = and <2 x i64> %a, %b
// CHECK: [[TMP5:%.*]] = icmp ne <2 x i64> [[TMP4]], zeroinitializer
// CHECK: [[VTST_I:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64>
@ -40,7 +40,7 @@ uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) {
return vtstq_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbsl_p64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbsl_p64(<1 x i64> noundef %a, <1 x i64> noundef %b, <1 x i64> noundef %c) #0 {
// CHECK: [[VBSL3_I:%.*]] = and <1 x i64> %a, %b
// CHECK: [[TMP3:%.*]] = xor <1 x i64> %a, <i64 -1>
// CHECK: [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], %c
@ -50,7 +50,7 @@ poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) {
return vbsl_p64(a, b, c);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbslq_p64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbslq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b, <2 x i64> noundef %c) #1 {
// CHECK: [[VBSL3_I:%.*]] = and <2 x i64> %a, %b
// CHECK: [[TMP3:%.*]] = xor <2 x i64> %a, <i64 -1, i64 -1>
// CHECK: [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], %c
@ -60,35 +60,35 @@ poly64x2_t test_vbslq_p64(poly64x2_t a, poly64x2_t b, poly64x2_t c) {
return vbslq_p64(a, b, c);
}
// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_p64(<1 x i64> %v) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vget_lane_p64(<1 x i64> noundef %v) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %v, i32 0
// CHECK: ret i64 [[VGET_LANE]]
poly64_t test_vget_lane_p64(poly64x1_t v) {
return vget_lane_p64(v, 0);
}
// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_p64(<2 x i64> %v) #1 {
// CHECK-LABEL: define{{.*}} i64 @test_vgetq_lane_p64(<2 x i64> noundef %v) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %v, i32 1
// CHECK: ret i64 [[VGETQ_LANE]]
poly64_t test_vgetq_lane_p64(poly64x2_t v) {
return vgetq_lane_p64(v, 1);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_p64(i64 %a, <1 x i64> %v) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vset_lane_p64(i64 noundef %a, <1 x i64> noundef %v) #0 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %v, i64 %a, i32 0
// CHECK: ret <1 x i64> [[VSET_LANE]]
poly64x1_t test_vset_lane_p64(poly64_t a, poly64x1_t v) {
return vset_lane_p64(a, v, 0);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_p64(i64 %a, <2 x i64> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsetq_lane_p64(i64 noundef %a, <2 x i64> noundef %v) #1 {
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %v, i64 %a, i32 1
// CHECK: ret <2 x i64> [[VSET_LANE]]
poly64x2_t test_vsetq_lane_p64(poly64_t a, poly64x2_t v) {
return vsetq_lane_p64(a, v, 1);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcopy_lane_p64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcopy_lane_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0
// CHECK: [[VSET_LANE:%.*]] = insertelement <1 x i64> %a, i64 [[VGET_LANE]], i32 0
// CHECK: ret <1 x i64> [[VSET_LANE]]
@ -97,7 +97,7 @@ poly64x1_t test_vcopy_lane_p64(poly64x1_t a, poly64x1_t b) {
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_lane_p64(<2 x i64> %a, <1 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_lane_p64(<2 x i64> noundef %a, <1 x i64> noundef %b) #1 {
// CHECK: [[VGET_LANE:%.*]] = extractelement <1 x i64> %b, i32 0
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGET_LANE]], i32 1
// CHECK: ret <2 x i64> [[VSET_LANE]]
@ -105,7 +105,7 @@ poly64x2_t test_vcopyq_lane_p64(poly64x2_t a, poly64x1_t b) {
return vcopyq_lane_p64(a, 1, b, 0);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcopyq_laneq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[VGETQ_LANE:%.*]] = extractelement <2 x i64> %b, i32 1
// CHECK: [[VSET_LANE:%.*]] = insertelement <2 x i64> %a, i64 [[VGETQ_LANE]], i32 1
// CHECK: ret <2 x i64> [[VSET_LANE]]
@ -113,20 +113,20 @@ poly64x2_t test_vcopyq_laneq_p64(poly64x2_t a, poly64x2_t b) {
return vcopyq_laneq_p64(a, 1, b, 1);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcreate_p64(i64 %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vcreate_p64(i64 noundef %a) #0 {
// CHECK: [[TMP0:%.*]] = bitcast i64 %a to <1 x i64>
// CHECK: ret <1 x i64> [[TMP0]]
poly64x1_t test_vcreate_p64(uint64_t a) {
return vcreate_p64(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_n_p64(i64 %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_n_p64(i64 noundef %a) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <1 x i64> undef, i64 %a, i32 0
// CHECK: ret <1 x i64> [[VECINIT_I]]
poly64x1_t test_vdup_n_p64(poly64_t a) {
return vdup_n_p64(a);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_n_p64(i64 %a) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_n_p64(i64 noundef %a) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 %a, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1
// CHECK: ret <2 x i64> [[VECINIT1_I]]
@ -134,14 +134,14 @@ poly64x2_t test_vdupq_n_p64(poly64_t a) {
return vdupq_n_p64(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vmov_n_p64(i64 %a) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vmov_n_p64(i64 noundef %a) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <1 x i64> undef, i64 %a, i32 0
// CHECK: ret <1 x i64> [[VECINIT_I]]
poly64x1_t test_vmov_n_p64(poly64_t a) {
return vmov_n_p64(a);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vmovq_n_p64(i64 %a) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vmovq_n_p64(i64 noundef %a) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 %a, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 %a, i32 1
// CHECK: ret <2 x i64> [[VECINIT1_I]]
@ -149,7 +149,7 @@ poly64x2_t test_vmovq_n_p64(poly64_t a) {
return vmovq_n_p64(a);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_lane_p64(<1 x i64> %vec) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vdup_lane_p64(<1 x i64> noundef %vec) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> [[VEC:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
// CHECK: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <1 x i32> zeroinitializer
@ -158,7 +158,7 @@ poly64x1_t test_vdup_lane_p64(poly64x1_t vec) {
return vdup_lane_p64(vec, 0);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_lane_p64(<1 x i64> %vec) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_lane_p64(<1 x i64> noundef %vec) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> [[VEC:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
// CHECK: [[LANE:%.*]] = shufflevector <1 x i64> [[TMP1]], <1 x i64> [[TMP1]], <2 x i32> zeroinitializer
@ -167,7 +167,7 @@ poly64x2_t test_vdupq_lane_p64(poly64x1_t vec) {
return vdupq_lane_p64(vec, 0);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_laneq_p64(<2 x i64> %vec) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vdupq_laneq_p64(<2 x i64> noundef %vec) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> [[VEC:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
// CHECK: [[LANE:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 1>
@ -176,14 +176,14 @@ poly64x2_t test_vdupq_laneq_p64(poly64x2_t vec) {
return vdupq_laneq_p64(vec, 1);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> %low, <1 x i64> %high) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vcombine_p64(<1 x i64> noundef %low, <1 x i64> noundef %high) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <1 x i64> %low, <1 x i64> %high, <2 x i32> <i32 0, i32 1>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vcombine_p64(poly64x1_t low, poly64x1_t high) {
return vcombine_p64(low, high);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_p64(i64* %ptr) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vld1_p64(i64* noundef %ptr) #0 {
// CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <1 x i64>*
// CHECK: [[TMP2:%.*]] = load <1 x i64>, <1 x i64>* [[TMP1]]
@ -192,7 +192,7 @@ poly64x1_t test_vld1_p64(poly64_t const * ptr) {
return vld1_p64(ptr);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_p64(i64* %ptr) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vld1q_p64(i64* noundef %ptr) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]]
@ -201,7 +201,7 @@ poly64x2_t test_vld1q_p64(poly64_t const * ptr) {
return vld1q_p64(ptr);
}
// CHECK-LABEL: define{{.*}} void @test_vst1_p64(i64* %ptr, <1 x i64> %val) #0 {
// CHECK-LABEL: define{{.*}} void @test_vst1_p64(i64* noundef %ptr, <1 x i64> noundef %val) #0 {
// CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %val to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <1 x i64>*
@ -212,7 +212,7 @@ void test_vst1_p64(poly64_t * ptr, poly64x1_t val) {
return vst1_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} void @test_vst1q_p64(i64* %ptr, <2 x i64> %val) #1 {
// CHECK-LABEL: define{{.*}} void @test_vst1q_p64(i64* noundef %ptr, <2 x i64> noundef %val) #1 {
// CHECK: [[TMP0:%.*]] = bitcast i64* %ptr to i8*
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %val to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast i8* [[TMP0]] to <2 x i64>*
@ -223,7 +223,7 @@ void test_vst1q_p64(poly64_t * ptr, poly64x2_t val) {
return vst1q_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_p64(i64* %ptr) #2 {
// CHECK-LABEL: define{{.*}} %struct.poly64x1x2_t @test_vld2_p64(i64* noundef %ptr) #2 {
// CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x2_t, align 8
// CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x2_t, align 8
// CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x2_t* [[__RET]] to i8*
@ -241,7 +241,7 @@ poly64x1x2_t test_vld2_p64(poly64_t const * ptr) {
return vld2_p64(ptr);
}
// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_p64(i64* %ptr) #2 {
// CHECK-LABEL: define{{.*}} %struct.poly64x2x2_t @test_vld2q_p64(i64* noundef %ptr) #2 {
// CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x2_t, align 16
// CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x2_t, align 16
// CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x2_t* [[__RET]] to i8*
@ -259,7 +259,7 @@ poly64x2x2_t test_vld2q_p64(poly64_t const * ptr) {
return vld2q_p64(ptr);
}
// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_p64(i64* %ptr) #2 {
// CHECK-LABEL: define{{.*}} %struct.poly64x1x3_t @test_vld3_p64(i64* noundef %ptr) #2 {
// CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x3_t, align 8
// CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x3_t, align 8
// CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x3_t* [[__RET]] to i8*
@ -277,7 +277,7 @@ poly64x1x3_t test_vld3_p64(poly64_t const * ptr) {
return vld3_p64(ptr);
}
// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_p64(i64* %ptr) #2 {
// CHECK-LABEL: define{{.*}} %struct.poly64x2x3_t @test_vld3q_p64(i64* noundef %ptr) #2 {
// CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x3_t, align 16
// CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x3_t, align 16
// CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x3_t* [[__RET]] to i8*
@ -295,7 +295,7 @@ poly64x2x3_t test_vld3q_p64(poly64_t const * ptr) {
return vld3q_p64(ptr);
}
// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_p64(i64* %ptr) #2 {
// CHECK-LABEL: define{{.*}} %struct.poly64x1x4_t @test_vld4_p64(i64* noundef %ptr) #2 {
// CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x1x4_t, align 8
// CHECK: [[__RET:%.*]] = alloca %struct.poly64x1x4_t, align 8
// CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x1x4_t* [[__RET]] to i8*
@ -313,7 +313,7 @@ poly64x1x4_t test_vld4_p64(poly64_t const * ptr) {
return vld4_p64(ptr);
}
// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_p64(i64* %ptr) #2 {
// CHECK-LABEL: define{{.*}} %struct.poly64x2x4_t @test_vld4q_p64(i64* noundef %ptr) #2 {
// CHECK: [[RETVAL:%.*]] = alloca %struct.poly64x2x4_t, align 16
// CHECK: [[__RET:%.*]] = alloca %struct.poly64x2x4_t, align 16
// CHECK: [[TMP0:%.*]] = bitcast %struct.poly64x2x4_t* [[__RET]] to i8*
@ -331,7 +331,7 @@ poly64x2x4_t test_vld4q_p64(poly64_t const * ptr) {
return vld4q_p64(ptr);
}
// CHECK-LABEL: define{{.*}} void @test_vst2_p64(i64* %ptr, [2 x <1 x i64>] %val.coerce) #2 {
// CHECK-LABEL: define{{.*}} void @test_vst2_p64(i64* noundef %ptr, [2 x <1 x i64>] %val.coerce) #2 {
// CHECK: [[VAL:%.*]] = alloca %struct.poly64x1x2_t, align 8
// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x2_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x2_t, %struct.poly64x1x2_t* [[VAL]], i32 0, i32 0
@ -356,7 +356,7 @@ void test_vst2_p64(poly64_t * ptr, poly64x1x2_t val) {
return vst2_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} void @test_vst2q_p64(i64* %ptr, [2 x <2 x i64>] %val.coerce) #2 {
// CHECK-LABEL: define{{.*}} void @test_vst2q_p64(i64* noundef %ptr, [2 x <2 x i64>] %val.coerce) #2 {
// CHECK: [[VAL:%.*]] = alloca %struct.poly64x2x2_t, align 16
// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x2_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x2_t, %struct.poly64x2x2_t* [[VAL]], i32 0, i32 0
@ -381,7 +381,7 @@ void test_vst2q_p64(poly64_t * ptr, poly64x2x2_t val) {
return vst2q_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} void @test_vst3_p64(i64* %ptr, [3 x <1 x i64>] %val.coerce) #2 {
// CHECK-LABEL: define{{.*}} void @test_vst3_p64(i64* noundef %ptr, [3 x <1 x i64>] %val.coerce) #2 {
// CHECK: [[VAL:%.*]] = alloca %struct.poly64x1x3_t, align 8
// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x3_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x3_t, %struct.poly64x1x3_t* [[VAL]], i32 0, i32 0
@ -411,7 +411,7 @@ void test_vst3_p64(poly64_t * ptr, poly64x1x3_t val) {
return vst3_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} void @test_vst3q_p64(i64* %ptr, [3 x <2 x i64>] %val.coerce) #2 {
// CHECK-LABEL: define{{.*}} void @test_vst3q_p64(i64* noundef %ptr, [3 x <2 x i64>] %val.coerce) #2 {
// CHECK: [[VAL:%.*]] = alloca %struct.poly64x2x3_t, align 16
// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x3_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x3_t, %struct.poly64x2x3_t* [[VAL]], i32 0, i32 0
@ -441,7 +441,7 @@ void test_vst3q_p64(poly64_t * ptr, poly64x2x3_t val) {
return vst3q_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} void @test_vst4_p64(i64* %ptr, [4 x <1 x i64>] %val.coerce) #2 {
// CHECK-LABEL: define{{.*}} void @test_vst4_p64(i64* noundef %ptr, [4 x <1 x i64>] %val.coerce) #2 {
// CHECK: [[VAL:%.*]] = alloca %struct.poly64x1x4_t, align 8
// CHECK: [[__S1:%.*]] = alloca %struct.poly64x1x4_t, align 8
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x1x4_t, %struct.poly64x1x4_t* [[VAL]], i32 0, i32 0
@ -476,7 +476,7 @@ void test_vst4_p64(poly64_t * ptr, poly64x1x4_t val) {
return vst4_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} void @test_vst4q_p64(i64* %ptr, [4 x <2 x i64>] %val.coerce) #2 {
// CHECK-LABEL: define{{.*}} void @test_vst4q_p64(i64* noundef %ptr, [4 x <2 x i64>] %val.coerce) #2 {
// CHECK: [[VAL:%.*]] = alloca %struct.poly64x2x4_t, align 16
// CHECK: [[__S1:%.*]] = alloca %struct.poly64x2x4_t, align 16
// CHECK: [[COERCE_DIVE:%.*]] = getelementptr inbounds %struct.poly64x2x4_t, %struct.poly64x2x4_t* [[VAL]], i32 0, i32 0
@ -511,7 +511,7 @@ void test_vst4q_p64(poly64_t * ptr, poly64x2x4_t val) {
return vst4q_p64(ptr, val);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_p64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
@ -523,7 +523,7 @@ poly64x1_t test_vext_p64(poly64x1_t a, poly64x1_t b) {
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
@ -534,49 +534,49 @@ poly64x2_t test_vextq_p64(poly64x2_t a, poly64x2_t b) {
return vextq_p64(a, b, 1);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip1q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vzip1q_p64(poly64x2_t a, poly64x2_t b) {
return vzip1q_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip2q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vzip2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vzip2q_p64(poly64x2_t a, poly64x2_t b) {
return vzip2q_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp1q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vuzp1q_p64(poly64x2_t a, poly64x2_t b) {
return vuzp1q_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp2q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vuzp2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vuzp2q_p64(poly64x2_t a, poly64x2_t b) {
return vuzp2q_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn1q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn1q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vtrn1q_p64(poly64x2_t a, poly64x2_t b) {
return vtrn1q_p64(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn2q_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vtrn2q_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
// CHECK: ret <2 x i64> [[SHUFFLE_I]]
poly64x2_t test_vtrn2q_p64(poly64x2_t a, poly64x2_t b) {
return vtrn2q_u64(a, b);
}
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vsri_n_p64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vsri_n_p64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
// CHECK: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
@ -587,7 +587,7 @@ poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) {
return vsri_n_p64(a, b, 33);
}
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsriq_n_p64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vsriq_n_p64(<2 x i64> noundef %a, <2 x i64> noundef %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
// CHECK: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>

8
clang/test/CodeGen/aarch64-strictfp-builtins.c
View File

@ -15,7 +15,7 @@ int printf(const char *, ...);
// CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[STR_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[X_ADDR]], align 4
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* [[TMP0]], i32 [[TMP1]]) [[ATTR4:#.*]]
// CHECK-NEXT: [[CALL:%.*]] = call i32 (i8*, ...) @printf(i8* noundef getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i64 0, i64 0), i8* noundef [[TMP0]], i32 noundef [[TMP1]]) [[ATTR4:#.*]]
// CHECK-NEXT: ret void
//
void p(char *str, int x) {
@ -33,7 +33,7 @@ void p(char *str, int x) {
// CHECK-NEXT: [[SHL1:%.*]] = shl i128 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp eq i128 [[SHL1]], -10384593717069655257060992658440192
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isinf(long double ld) {
@ -51,7 +51,7 @@ void test_long_double_isinf(long double ld) {
// CHECK-NEXT: [[SHL1:%.*]] = shl i128 [[BITCAST]], 1
// CHECK-NEXT: [[CMP:%.*]] = icmp ult i128 [[SHL1]], -10384593717069655257060992658440192
// CHECK-NEXT: [[RES:%.*]] = zext i1 [[CMP]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]]) [[ATTR4]]
// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([13 x i8], [13 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]]) [[ATTR4]]
// CHECK-NEXT: ret void
//
void test_long_double_isfinite(long double ld) {
@ -70,7 +70,7 @@ void test_long_double_isfinite(long double ld) {
// CHECK-NEXT: [[TMP1:%.*]] = sub i128 170135991163610696904058773219554885632, [[ABS]]
// CHECK-NEXT: [[ISNAN:%.*]] = lshr i128 [[TMP1]], 127
// CHECK-NEXT: [[RES:%.*]] = trunc i128 [[ISNAN]] to i32
// CHECK-NEXT: call void @p(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 [[RES]])
// CHECK-NEXT: call void @p(i8* noundef getelementptr inbounds ([10 x i8], [10 x i8]* @.str.[[#STRID:STRID+1]], i64 0, i64 0), i32 noundef [[RES]])
// CHECK-NEXT: ret void
//
void test_long_double_isnan(long double ld) {

16
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c
View File

@ -50,7 +50,7 @@ vec2048 x2048 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0,
#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS
#define N __ARM_FEATURE_SVE_BITS
typedef int8_t vec_int8 __attribute__((vector_size(N / 8)));
// CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> %x)
// CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> noundef %x)
// CHECK128-NEXT: entry:
// CHECK128-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
// CHECK128-NEXT: [[CASTSCALABLESVE:%.*]] = call <vscale x 16 x i8> @llvm.experimental.vector.insert.nxv16i8.v16i8(<vscale x 16 x i8> undef, <16 x i8> [[X:%.*]], i64 0)
@ -59,7 +59,7 @@ typedef int8_t vec_int8 __attribute__((vector_size(N / 8)));
// CHECK128-NEXT: ret <16 x i8> [[CASTFIXEDSVE]]
// CHECK-LABEL: define{{.*}} void @f2(
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture readonly %0)
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture noundef readonly %0)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]]
// CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
@ -78,23 +78,23 @@ typedef int8_t vec1 __attribute__((vector_size(N / 8)));
void f3(vec1);
typedef svint8_t vec2 __attribute__((arm_sve_vector_bits(N)));
// CHECK128-LABEL: define{{.*}} void @g(<vscale x 16 x i8> %x.coerce)
// CHECK128-LABEL: define{{.*}} void @g(<vscale x 16 x i8> noundef %x.coerce)
// CHECK128-NEXT: entry:
// CHECK128-NEXT: [[X:%.*]] = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> [[X_COERCE:%.*]], i64 0)
// CHECK128-NEXT: call void @f3(<16 x i8> [[X]]) [[ATTR5:#.*]]
// CHECK128-NEXT: call void @f3(<16 x i8> noundef [[X]]) [[ATTR5:#.*]]
// CHECK128-NEXT: ret void
// CHECK-LABEL: define{{.*}} void @g(<vscale x 16 x i8> %x.coerce)
// CHECK-LABEL: define{{.*}} void @g(<vscale x 16 x i8> noundef %x.coerce)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS,8)]] x i8>, align 16
// CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS,8)]] x i8> @llvm.experimental.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8(<vscale x 16 x i8> [[X_COERCE:%.*]], i64 0)
// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[X]], <[[#div(VBITS,8)]] x i8>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6]]
// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
// CHECK-NEXT: ret void
// CHECK128-LABEL: declare void @f3(<16 x i8>)
// CHECK128-LABEL: declare void @f3(<16 x i8> noundef)
// CHECK-LABEL: declare void @f3(
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>*)
// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noundef)
void g(vec2 x) { f3(x); } // OK
#endif

8
clang/test/CodeGen/aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp
View File

@ -47,7 +47,7 @@ void test02() {
#define N __ARM_FEATURE_SVE_BITS
// CHECK-LABEL: define{{.*}} <vscale x 4 x i32> @_Z1f9__SVE_VLSIu11__SVInt32_tLj
// CHECK-SAME: [[#VBITS]]
// CHECK-SAME: EES_(<vscale x 4 x i32> %x.coerce, <vscale x 4 x i32> %y.coerce)
// CHECK-SAME: EES_(<vscale x 4 x i32> noundef %x.coerce, <vscale x 4 x i32> noundef %y.coerce)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[Y:%.*]] = call <[[#div(VBITS, 32)]] x i32> @llvm.experimental.vector.extract.v[[#div(VBITS, 32)]]i32.nxv4i32(<vscale x 4 x i32> [[X_COERCE1:%.*]], i64 0)
@ -66,15 +66,15 @@ void f(vec1);
typedef svint16_t vec2 __attribute__((arm_sve_vector_bits(N)));
// CHECK-LABEL: define{{.*}} void @_Z1g9__SVE_VLSIu11__SVInt16_tLj
// CHECK-SAME: [[#VBITS]]
// CHECK-SAME: EE(<vscale x 8 x i16> %x.coerce)
// CHECK-SAME: EE(<vscale x 8 x i16> noundef %x.coerce)
// CHECK-NEXT: entry:
// CHECK128-NEXT: [[X:%.*]] = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0)
// CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> [[X]]) [[ATTR5:#.*]]
// CHECK128-NEXT: call void @_Z1fDv8_s(<8 x i16> noundef [[X]]) [[ATTR5:#.*]]
// CHECK128-NEXT: ret void
// CHECKWIDE-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS, 16)]] x i16>, align 16
// CHECKWIDE-NEXT: [[X:%.*]] = call <[[#div(VBITS, 16)]] x i16> @llvm.experimental.vector.extract.v[[#div(VBITS, 16)]]i16.nxv8i16(<vscale x 8 x i16> [[X_COERCE:%.*]], i64 0)
// CHECKWIDE-NEXT: store <[[#div(VBITS, 16)]] x i16> [[X]], <[[#div(VBITS, 16)]] x i16>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6:!tbaa !.*]]
// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
// CHECKWIDE-NEXT: call void @_Z1fDv[[#div(VBITS, 16)]]_s(<[[#div(VBITS, 16)]] x i16>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]
// CHECKWIDE-NEXT: ret void
void g(vec2 x) { f(x); } // OK
#endif

2
clang/test/CodeGen/aarch64-varargs.c
View File

@ -885,7 +885,7 @@ overaligned_int128_struct_member overaligned_int128_struct_member_test() {
}
void check_start(int n, ...) {
// CHECK-LABEL: define{{.*}} void @check_start(i32 %n, ...)
// CHECK-LABEL: define{{.*}} void @check_start(i32 noundef %n, ...)
va_list the_list;
va_start(the_list, n);

2
clang/test/CodeGen/address-space-field1.c
View File

@ -1,6 +1,6 @@
// RUN: %clang_cc1 -emit-llvm -triple x86_64-apple-darwin10 < %s -o - | FileCheck %s
// CHECK:%struct.S = type { i32, i32 }
// CHECK:define{{.*}} void @test_addrspace(%struct.S addrspace(1)* %p1, %struct.S addrspace(2)* %p2) [[NUW:#[0-9]+]]
// CHECK:define{{.*}} void @test_addrspace(%struct.S addrspace(1)* noundef %p1, %struct.S addrspace(2)* noundef %p2) [[NUW:#[0-9]+]]
// CHECK: [[p1addr:%.*]] = alloca %struct.S addrspace(1)*
// CHECK: [[p2addr:%.*]] = alloca %struct.S addrspace(2)*
// CHECK: store %struct.S addrspace(1)* %p1, %struct.S addrspace(1)** [[p1addr]]

2
clang/test/CodeGen/address-space.c
View File

@ -14,7 +14,7 @@ int a __attribute__((address_space(0)));
// CHECK: load i32, i32 addrspace(1)* @foo
int test1() { return foo; }
// CHECK-LABEL: define{{.*}} i32 @test2(i32 %i)
// CHECK-LABEL: define{{.*}} i32 @test2(i32 noundef %i)
// CHECK: load i32, i32 addrspace(1)*
// CHECK-NEXT: ret i32
int test2(int i) { return ban[i]; }

8
clang/test/CodeGen/aix-alignment.c
View File

@ -15,22 +15,22 @@ typedef struct {
// AIX: @d1 = global %struct.StructDouble zeroinitializer, align 8
StructDouble d1;
// AIX: double @retDouble(double %x)
// AIX: double @retDouble(double noundef %x)
// AIX: %x.addr = alloca double, align 8
// AIX: store double %x, double* %x.addr, align 8
// AIX: load double, double* %x.addr, align 8
// AIX: ret double %0
double retDouble(double x) { return x; }
// AIX32: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* byval(%struct.StructDouble) align 4 %x)
// AIX64: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* byval(%struct.StructDouble) align 8 %x)
// AIX32: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* noundef byval(%struct.StructDouble) align 4 %x)
// AIX64: define void @bar(%struct.StructDouble* noalias sret(%struct.StructDouble) align 4 %agg.result, %struct.StructDouble* noundef byval(%struct.StructDouble) align 8 %x)
// AIX: %0 = bitcast %struct.StructDouble* %agg.result to i8*
// AIX: %1 = bitcast %struct.StructDouble* %x to i8*
// AIX32: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 %1, i32 16, i1 false)
// AIX64: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %0, i8* align 8 %1, i64 16, i1 false)
StructDouble bar(StructDouble x) { return x; }
// AIX: define void @foo(double* %out, double* %in)
// AIX: define void @foo(double* noundef %out, double* noundef %in)
// AIX32: %0 = load double*, double** %in.addr, align 4
// AIX64: %0 = load double*, double** %in.addr, align 8
// AIX: %1 = load double, double* %0, align 4

10
clang/test/CodeGen/aix-altivec.c
View File

@ -2,7 +2,7 @@
// RUN: %clang_cc1 -triple powerpc64-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc-unknown-aix -target-feature +altivec -target-cpu pwr8 -emit-llvm %s -o - | FileCheck %s
vector float foo1(vector float x) { return x; }
// CHECK: define <4 x float> @foo1(<4 x float> %x) [[ATTR:#[0-9]+]] {
// CHECK: define <4 x float> @foo1(<4 x float> noundef %x) [[ATTR:#[0-9]+]] {
// CHECK: entry:
// CHECK: %x.addr = alloca <4 x float>, align 16
// CHECK: store <4 x float> %x, <4 x float>* %x.addr, align 16
@ -10,7 +10,7 @@ vector float foo1(vector float x) { return x; }
// CHECK: ret <4 x float> %0
// CHECK: }
vector double foo2(vector double x) { return x; }
// CHECK: define <2 x double> @foo2(<2 x double> %x) [[ATTR]] {
// CHECK: define <2 x double> @foo2(<2 x double> noundef %x) [[ATTR]] {
// CHECK: entry:
// CHECK: %x.addr = alloca <2 x double>, align 16
// CHECK: store <2 x double> %x, <2 x double>* %x.addr, align 16
@ -18,7 +18,7 @@ vector double foo2(vector double x) { return x; }
// CHECK: ret <2 x double> %0
// CHECK: }
vector int foo3(vector int x) { return x; }
// CHECK: define <4 x i32> @foo3(<4 x i32> %x) [[ATTR]] {
// CHECK: define <4 x i32> @foo3(<4 x i32> noundef %x) [[ATTR]] {
// CHECK: entry:
// CHECK: %x.addr = alloca <4 x i32>, align 16
// CHECK: store <4 x i32> %x, <4 x i32>* %x.addr, align 16
@ -26,7 +26,7 @@ vector int foo3(vector int x) { return x; }
// CHECK: ret <4 x i32> %0
// CHECK: }
vector short int foo4(vector short int x) { return x; }
// CHECK: define <8 x i16> @foo4(<8 x i16> %x) [[ATTR]] {
// CHECK: define <8 x i16> @foo4(<8 x i16> noundef %x) [[ATTR]] {
// CHECK: entry:
// CHECK: %x.addr = alloca <8 x i16>, align 16
// CHECK: store <8 x i16> %x, <8 x i16>* %x.addr, align 16
@ -34,7 +34,7 @@ vector short int foo4(vector short int x) { return x; }
// CHECK: ret <8 x i16> %0
// CHECK: }
vector char foo5(vector char x) { return x; }
// CHECK: define <16 x i8> @foo5(<16 x i8> %x) [[ATTR]] {
// CHECK: define <16 x i8> @foo5(<16 x i8> noundef %x) [[ATTR]] {
// CHECK: entry:
// CHECK: %x.addr = alloca <16 x i8>, align 16
// CHECK: store <16 x i8> %x, <16 x i8>* %x.addr, align 16

12
clang/test/CodeGen/aix-ignore-xcoff-visibility.cpp
View File

@ -56,18 +56,18 @@ void prambar() {}
// VISIBILITY-IR: @b = protected global i32 0
// VISIBILITY-IR: @pramb = hidden global i32 0
// VISIBILITY-IR: define hidden void @_Z5foo_hPi(i32* %p)
// VISIBILITY-IR: define hidden void @_Z5foo_hPi(i32* noundef %p)
// VISIBILITY-IR: declare hidden void @_Z12zoo_extern_hv()
// VISIBILITY-IR: define protected void @_Z3barv()
// VISIBILITY-IR: define linkonce_odr hidden i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this)
// VISIBILITY-IR: define weak_odr protected i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this)
// VISIBILITY-IR: define linkonce_odr hidden noundef i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this)
// VISIBILITY-IR: define weak_odr protected noundef i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this)
// VISIBILITY-IR: define hidden void @_Z7prambarv()
// NOVISIBILITY-IR: @b = global i32 0
// NOVISIBILITY-IR: @pramb = global i32 0
// NOVISIBILITY-IR: define void @_Z5foo_hPi(i32* %p)
// NOVISIBILITY-IR: define void @_Z5foo_hPi(i32* noundef %p)
// NOVISIBILITY-IR: declare void @_Z12zoo_extern_hv()
// NOVISIBILITY-IR: define void @_Z3barv()
// NOVISIBILITY-IR: define linkonce_odr i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this)
// NOVISIBILITY-IR: define weak_odr i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this)
// NOVISIBILITY-IR: define linkonce_odr noundef i32 @_ZNK9TestClass5valueEv(%class.TestClass* {{[^,]*}} %this)
// NOVISIBILITY-IR: define weak_odr noundef i32 @_ZN5basicIiE7getdataEv(%class.basic* {{[^,]*}} %this)
// NOVISIBILITY-IR: define void @_Z7prambarv()

16
clang/test/CodeGen/aix-return.c
View File

@ -7,27 +7,27 @@
// AIX-LABEL: define void @retVoid()
void retVoid(void) {}
// AIX-LABEL: define signext i8 @retChar(i8 signext %x)
// AIX-LABEL: define signext i8 @retChar(i8 noundef signext %x)
char retChar(char x) { return x; }
// AIX-LABEL: define signext i16 @retShort(i16 signext %x)
// AIX-LABEL: define signext i16 @retShort(i16 noundef signext %x)
short retShort(short x) { return x; }
// AIX32-LABEL: define i32 @retInt(i32 %x)
// AIX64-LABEL: define signext i32 @retInt(i32 signext %x)
// AIX32-LABEL: define i32 @retInt(i32 noundef %x)
// AIX64-LABEL: define signext i32 @retInt(i32 noundef signext %x)
int retInt(int x) { return 1; }
// AIX-LABEL: define i64 @retLongLong(i64 %x)
// AIX-LABEL: define i64 @retLongLong(i64 noundef %x)
long long retLongLong(long long x) { return x; }
// AIX-LABEL: define signext i8 @retEnumChar(i8 signext %x)
// AIX-LABEL: define signext i8 @retEnumChar(i8 noundef signext %x)
enum EnumChar : char { IsChar };
enum EnumChar retEnumChar(enum EnumChar x) {
return x;
}
// AIX32-LABEL: define i32 @retEnumInt(i32 %x)
// AIX64-LABEL: define signext i32 @retEnumInt(i32 signext %x)
// AIX32-LABEL: define i32 @retEnumInt(i32 noundef %x)
// AIX64-LABEL: define signext i32 @retEnumInt(i32 noundef signext %x)
enum EnumInt : int { IsInt };
enum EnumInt retEnumInt(enum EnumInt x) {
return x;

44
clang/test/CodeGen/aix-struct-arg.c
View File

@ -38,52 +38,52 @@ typedef struct {
vector signed int vsi;
} StructVector;
// AIX32-LABEL: define void @arg0(%struct.Zero* byval(%struct.Zero) align 4 %x)
// AIX64-LABEL: define void @arg0(%struct.Zero* byval(%struct.Zero) align 8 %x)
// AIX32-LABEL: define void @arg0(%struct.Zero* noundef byval(%struct.Zero) align 4 %x)
// AIX64-LABEL: define void @arg0(%struct.Zero* noundef byval(%struct.Zero) align 8 %x)
void arg0(Zero x) {}
// AIX32-LABEL: define void @arg1(%struct.One* byval(%struct.One) align 4 %x)
// AIX64-LABEL: define void @arg1(%struct.One* byval(%struct.One) align 8 %x)
// AIX32-LABEL: define void @arg1(%struct.One* noundef byval(%struct.One) align 4 %x)
// AIX64-LABEL: define void @arg1(%struct.One* noundef byval(%struct.One) align 8 %x)
void arg1(One x) {}
// AIX32-LABEL: define void @arg2(%struct.Two* byval(%struct.Two) align 4 %x)
// AIX64-LABEL: define void @arg2(%struct.Two* byval(%struct.Two) align 8 %x)
// AIX32-LABEL: define void @arg2(%struct.Two* noundef byval(%struct.Two) align 4 %x)
// AIX64-LABEL: define void @arg2(%struct.Two* noundef byval(%struct.Two) align 8 %x)
void arg2(Two x) {}
// AIX32-LABEL: define void @arg3(%struct.Three* byval(%struct.Three) align 4 %x)
// AIX64-LABEL: define void @arg3(%struct.Three* byval(%struct.Three) align 8 %x)
// AIX32-LABEL: define void @arg3(%struct.Three* noundef byval(%struct.Three) align 4 %x)
// AIX64-LABEL: define void @arg3(%struct.Three* noundef byval(%struct.Three) align 8 %x)
void arg3(Three x) {}
// AIX32-LABEL: define void @arg4(%struct.Four* byval(%struct.Four) align 4 %x)
// AIX64-LABEL: define void @arg4(%struct.Four* byval(%struct.Four) align 8 %x)
// AIX32-LABEL: define void @arg4(%struct.Four* noundef byval(%struct.Four) align 4 %x)
// AIX64-LABEL: define void @arg4(%struct.Four* noundef byval(%struct.Four) align 8 %x)
void arg4(Four x) {}
// AIX32-LABEL: define void @arg5(%struct.Five* byval(%struct.Five) align 4 %x)
// AIX64-LABEL: define void @arg5(%struct.Five* byval(%struct.Five) align 8 %x)
// AIX32-LABEL: define void @arg5(%struct.Five* noundef byval(%struct.Five) align 4 %x)
// AIX64-LABEL: define void @arg5(%struct.Five* noundef byval(%struct.Five) align 8 %x)
void arg5(Five x) {}
// AIX32-LABEL: define void @arg6(%struct.Six* byval(%struct.Six) align 4 %x)
// AIX64-LABEL: define void @arg6(%struct.Six* byval(%struct.Six) align 8 %x)
// AIX32-LABEL: define void @arg6(%struct.Six* noundef byval(%struct.Six) align 4 %x)
// AIX64-LABEL: define void @arg6(%struct.Six* noundef byval(%struct.Six) align 8 %x)
void arg6(Six x) {}
// AIX32-LABEL: define void @arg7(%struct.Seven* byval(%struct.Seven) align 4 %x)
// AIX64-LABEL: define void @arg7(%struct.Seven* byval(%struct.Seven) align 8 %x)
// AIX32-LABEL: define void @arg7(%struct.Seven* noundef byval(%struct.Seven) align 4 %x)
// AIX64-LABEL: define void @arg7(%struct.Seven* noundef byval(%struct.Seven) align 8 %x)
void arg7(Seven x) {}
// AIX32-LABEL: define void @arg8(%struct.Eight* byval(%struct.Eight) align 4 %0)
// AIX32-LABEL: define void @arg8(%struct.Eight* noundef byval(%struct.Eight) align 4 %0)
// AIX32: %x = alloca %struct.Eight, align 8
// AIX32: call void @llvm.memcpy.p0i8.p0i8.i32
// AIX64-LABEL: define void @arg8(%struct.Eight* byval(%struct.Eight) align 8 %x)
// AIX64-LABEL: define void @arg8(%struct.Eight* noundef byval(%struct.Eight) align 8 %x)
void arg8(Eight x) {}
// AIX32-LABEL: define void @arg9(%struct.OverAligned* byval(%struct.OverAligned) align 4 %0)
// AIX32-LABEL: define void @arg9(%struct.OverAligned* noundef byval(%struct.OverAligned) align 4 %0)
// AIX32: %x = alloca %struct.OverAligned, align 32
// AIX32: call void @llvm.memcpy.p0i8.p0i8.i32
// AIX64-LABEL: define void @arg9(%struct.OverAligned* byval(%struct.OverAligned) align 8 %0)
// AIX64-LABEL: define void @arg9(%struct.OverAligned* noundef byval(%struct.OverAligned) align 8 %0)
// AIX64: %x = alloca %struct.OverAligned, align 32
// AIX64: call void @llvm.memcpy.p0i8.p0i8.i64
void arg9(OverAligned x) {}
// AIX32-LABEL: define void @arg10(%struct.StructVector* byval(%struct.StructVector) align 16 %x)
// AIX64-LABEL: define void @arg10(%struct.StructVector* byval(%struct.StructVector) align 16 %x)
// AIX32-LABEL: define void @arg10(%struct.StructVector* noundef byval(%struct.StructVector) align 16 %x)
// AIX64-LABEL: define void @arg10(%struct.StructVector* noundef byval(%struct.StructVector) align 16 %x)
void arg10(StructVector x) {}

4
clang/test/CodeGen/aix-vaargs.c
View File

@ -19,8 +19,8 @@ void testva (int n, ...) {
__builtin_va_end(ap);
}
// AIX32: define void @testva(i32 %n, ...)
// AIX64: define void @testva(i32 signext %n, ...)
// AIX32: define void @testva(i32 noundef %n, ...)
// AIX64: define void @testva(i32 noundef signext %n, ...)
// CHECK-NEXT: entry:
// CHECK-NEXT: %n.addr = alloca i32, align 4

12
clang/test/CodeGen/alias.c
View File

@ -72,16 +72,16 @@ static int inner_weak(int a) { return 0; }
extern __typeof(inner) inner_a __attribute__((alias("inner")));
static __typeof(inner_weak) inner_weak_a __attribute__((weakref, alias("inner_weak")));
// CHECKCC: @inner_a ={{.*}} alias i32 (i32), i32 (i32)* @inner
// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner(i32 %a) [[NUW:#[0-9]+]] {
// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner(i32 noundef %a) [[NUW:#[0-9]+]] {
int outer(int a) { return inner(a); }
// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer(i32 %a) [[NUW]] {
// CHECKCC: call arm_aapcs_vfpcc i32 @inner(i32 %{{.*}})
// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer(i32 noundef %a) [[NUW]] {
// CHECKCC: call arm_aapcs_vfpcc i32 @inner(i32 noundef %{{.*}})
int outer_weak(int a) { return inner_weak_a(a); }
// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer_weak(i32 %a) [[NUW]] {
// CHECKCC: call arm_aapcs_vfpcc i32 @inner_weak(i32 %{{.*}})
// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner_weak(i32 %a) [[NUW]] {
// CHECKCC: define{{.*}} arm_aapcs_vfpcc i32 @outer_weak(i32 noundef %a) [[NUW]] {
// CHECKCC: call arm_aapcs_vfpcc i32 @inner_weak(i32 noundef %{{.*}})
// CHECKCC: define internal arm_aapcs_vfpcc i32 @inner_weak(i32 noundef %a) [[NUW]] {
// CHECKBASIC: attributes [[NUW]] = { noinline nounwind{{.*}} }

63
clang/test/CodeGen/align_value.cpp
View File

@ -3,15 +3,14 @@
typedef double * __attribute__((align_value(64))) aligned_double;
// CHECK-LABEL: define {{[^@]+}}@_Z3fooPdS_Rd
// CHECK-SAME: (double* align 64 [[X:%.*]], double* align 32 [[Y:%.*]], double* nonnull align 128 dereferenceable(8) [[Z:%.*]]) #0
// CHECK-LABEL: @_Z3fooPdS_Rd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double*, align 8
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca double*, align 8
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca double*, align 8
// CHECK-NEXT: store double* [[X]], double** [[X_ADDR]], align 8
// CHECK-NEXT: store double* [[Y]], double** [[Y_ADDR]], align 8
// CHECK-NEXT: store double* [[Z]], double** [[Z_ADDR]], align 8
// CHECK-NEXT: store double* [[X:%.*]], double** [[X_ADDR]], align 8
// CHECK-NEXT: store double* [[Y:%.*]], double** [[Y_ADDR]], align 8
// CHECK-NEXT: store double* [[Z:%.*]], double** [[Z_ADDR]], align 8
// CHECK-NEXT: ret void
//
void foo(aligned_double x, double * y __attribute__((align_value(32))),
@ -21,11 +20,10 @@ struct ad_struct {
aligned_double a;
};
// CHECK-LABEL: define {{[^@]+}}@_Z3fooR9ad_struct
// CHECK-SAME: (%struct.ad_struct* nonnull align 8 dereferenceable(8) [[X:%.*]]) #0
// CHECK-LABEL: @_Z3fooR9ad_struct(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca %struct.ad_struct*, align 8
// CHECK-NEXT: store %struct.ad_struct* [[X]], %struct.ad_struct** [[X_ADDR]], align 8
// CHECK-NEXT: store %struct.ad_struct* [[X:%.*]], %struct.ad_struct** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load %struct.ad_struct*, %struct.ad_struct** [[X_ADDR]], align 8
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_AD_STRUCT:%.*]], %struct.ad_struct* [[TMP0]], i32 0, i32 0
// CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[A]], align 8
@ -37,11 +35,10 @@ double *foo(ad_struct& x) {
return x.a;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3gooP9ad_struct
// CHECK-SAME: (%struct.ad_struct* [[X:%.*]]) #0
// CHECK-LABEL: @_Z3gooP9ad_struct(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca %struct.ad_struct*, align 8
// CHECK-NEXT: store %struct.ad_struct* [[X]], %struct.ad_struct** [[X_ADDR]], align 8
// CHECK-NEXT: store %struct.ad_struct* [[X:%.*]], %struct.ad_struct** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load %struct.ad_struct*, %struct.ad_struct** [[X_ADDR]], align 8
// CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_AD_STRUCT:%.*]], %struct.ad_struct* [[TMP0]], i32 0, i32 0
// CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[A]], align 8
@ -53,11 +50,10 @@ double *goo(ad_struct *x) {
return x->a;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3barPPd
// CHECK-SAME: (double** [[X:%.*]]) #0
// CHECK-LABEL: @_Z3barPPd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8
// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP0]], align 8
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[TMP1]], i64 64) ]
@ -68,11 +64,10 @@ double *bar(aligned_double *x) {
return *x;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3carRPd
// CHECK-SAME: (double** nonnull align 8 dereferenceable(8) [[X:%.*]]) #0
// CHECK-LABEL: @_Z3carRPd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8
// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[TMP0]], align 8
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[TMP1]], i64 64) ]
@ -83,11 +78,10 @@ double *car(aligned_double &x) {
return x;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3darPPd
// CHECK-SAME: (double** [[X:%.*]]) #0
// CHECK-LABEL: @_Z3darPPd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8
// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double*, double** [[TMP0]], i64 5
// CHECK-NEXT: [[TMP1:%.*]] = load double*, double** [[ARRAYIDX]], align 8
@ -100,9 +94,9 @@ double *dar(aligned_double *x) {
}
aligned_double eep();
// CHECK-LABEL: define {{[^@]+}}@_Z3retv() #0
// CHECK-LABEL: @_Z3retv(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[CALL:%.*]] = call double* @_Z3eepv()
// CHECK-NEXT: [[CALL:%.*]] = call noundef double* @_Z3eepv()
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(double* [[CALL]], i64 64) ]
// CHECK-NEXT: ret double* [[CALL]]
//
@ -111,11 +105,10 @@ double *ret() {
return eep();
}
// CHECK-LABEL: define {{[^@]+}}@_Z3no1PPd
// CHECK-SAME: (double** [[X:%.*]]) #0
// CHECK-LABEL: @_Z3no1PPd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8
// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8
// CHECK-NEXT: ret double** [[TMP0]]
//
@ -123,11 +116,10 @@ double **no1(aligned_double *x) {
return x;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3no2RPd
// CHECK-SAME: (double** nonnull align 8 dereferenceable(8) [[X:%.*]]) #0
// CHECK-LABEL: @_Z3no2RPd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8
// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8
// CHECK-NEXT: ret double** [[TMP0]]
//
@ -135,11 +127,10 @@ double *&no2(aligned_double &x) {
return x;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3no3RPd
// CHECK-SAME: (double** nonnull align 8 dereferenceable(8) [[X:%.*]]) #0
// CHECK-LABEL: @_Z3no3RPd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double**, align 8
// CHECK-NEXT: store double** [[X]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: store double** [[X:%.*]], double*** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double**, double*** [[X_ADDR]], align 8
// CHECK-NEXT: ret double** [[TMP0]]
//
@ -147,11 +138,10 @@ double **no3(aligned_double &x) {
return &x;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3no3Pd
// CHECK-SAME: (double* align 64 [[X:%.*]]) #0
// CHECK-LABEL: @_Z3no3Pd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double*, align 8
// CHECK-NEXT: store double* [[X]], double** [[X_ADDR]], align 8
// CHECK-NEXT: store double* [[X:%.*]], double** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double*, double** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[TMP0]], align 8
// CHECK-NEXT: ret double [[TMP1]]
@ -160,11 +150,10 @@ double no3(aligned_double x) {
return *x;
}
// CHECK-LABEL: define {{[^@]+}}@_Z3no4Pd
// CHECK-SAME: (double* align 64 [[X:%.*]]) #0
// CHECK-LABEL: @_Z3no4Pd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca double*, align 8
// CHECK-NEXT: store double* [[X]], double** [[X_ADDR]], align 8
// CHECK-NEXT: store double* [[X:%.*]], double** [[X_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double*, double** [[X_ADDR]], align 8
// CHECK-NEXT: ret double* [[TMP0]]
//

46
clang/test/CodeGen/alloc-align-attr.c
View File

@ -4,13 +4,12 @@
__INT32_TYPE__*m1(__INT32_TYPE__ i) __attribute__((alloc_align(1)));
// Condition where parameter to m1 is not size_t.
// CHECK-LABEL: define {{[^@]+}}@test1
// CHECK-SAME: (i32 [[A:%.*]]) #0
// CHECK-LABEL: @test1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 [[TMP0]])
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 noundef [[TMP0]])
// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4
@ -20,14 +19,13 @@ __INT32_TYPE__ test1(__INT32_TYPE__ a) {
return *m1(a);
}
// Condition where test2 param needs casting.
// CHECK-LABEL: define {{[^@]+}}@test2
// CHECK-SAME: (i64 [[A:%.*]]) #0
// CHECK-LABEL: @test2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 [[CONV]])
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m1(i32 noundef [[CONV]])
// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = zext i32 [[CONV]] to i64
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4
@ -39,14 +37,13 @@ __INT32_TYPE__ test2(__SIZE_TYPE__ a) {
__INT32_TYPE__ *m2(__SIZE_TYPE__ i) __attribute__((alloc_align(1)));
// test3 param needs casting, but 'm2' is correct.
// CHECK-LABEL: define {{[^@]+}}@test3
// CHECK-SAME: (i32 [[A:%.*]]) #0
// CHECK-LABEL: @test3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// CHECK-NEXT: [[CONV:%.*]] = sext i32 [[TMP0]] to i64
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 [[CONV]])
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 noundef [[CONV]])
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CONV]]) ]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4
// CHECK-NEXT: ret i32 [[TMP1]]
@ -56,13 +53,12 @@ __INT32_TYPE__ test3(__INT32_TYPE__ a) {
}
// Every type matches, canonical example.
// CHECK-LABEL: define {{[^@]+}}@test4
// CHECK-SAME: (i64 [[A:%.*]]) #0
// CHECK-LABEL: @test4(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 [[TMP0]])
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m2(i64 noundef [[TMP0]])
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[TMP0]]) ]
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[CALL]], align 4
// CHECK-NEXT: ret i32 [[TMP1]]
@ -77,8 +73,7 @@ struct MultiArgs { __INT64_TYPE__ a, b;};
// Struct parameter doesn't take up an IR parameter, 'i' takes up 2.
// Truncation to i64 is permissible, since alignments of greater than 2^64 are insane.
__INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2)));
// CHECK-LABEL: define {{[^@]+}}@test5
// CHECK-SAME: (i64 [[A_COERCE0:%.*]], i64 [[A_COERCE1:%.*]]) #0
// CHECK-LABEL: @test5(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = alloca i128, align 16
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i128, align 16
@ -86,9 +81,9 @@ __INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2)))
// CHECK-NEXT: [[COERCE:%.*]] = alloca i128, align 16
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i128* [[A]] to { i64, i64 }*
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 0
// CHECK-NEXT: store i64 [[A_COERCE0]], i64* [[TMP1]], align 16
// CHECK-NEXT: store i64 [[A_COERCE0:%.*]], i64* [[TMP1]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 1
// CHECK-NEXT: store i64 [[A_COERCE1]], i64* [[TMP2]], align 8
// CHECK-NEXT: store i64 [[A_COERCE1:%.*]], i64* [[TMP2]], align 8
// CHECK-NEXT: [[A1:%.*]] = load i128, i128* [[A]], align 16
// CHECK-NEXT: store i128 [[A1]], i128* [[A_ADDR]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load i128, i128* [[A_ADDR]], align 16
@ -98,7 +93,7 @@ __INT32_TYPE__ *m3(struct Empty s, __int128_t i) __attribute__((alloc_align(2)))
// CHECK-NEXT: [[TMP6:%.*]] = load i64, i64* [[TMP5]], align 16
// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP4]], i32 0, i32 1
// CHECK-NEXT: [[TMP8:%.*]] = load i64, i64* [[TMP7]], align 8
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m3(i64 [[TMP6]], i64 [[TMP8]])
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m3(i64 noundef [[TMP6]], i64 noundef [[TMP8]])
// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = trunc i128 [[TMP3]] to i64
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ]
// CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[CALL]], align 4
@ -110,8 +105,7 @@ __INT32_TYPE__ test5(__int128_t a) {
}
// Struct parameter takes up 2 parameters, 'i' takes up 2.
__INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align(2)));
// CHECK-LABEL: define {{[^@]+}}@test6
// CHECK-SAME: (i64 [[A_COERCE0:%.*]], i64 [[A_COERCE1:%.*]]) #0
// CHECK-LABEL: @test6(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = alloca i128, align 16
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i128, align 16
@ -119,9 +113,9 @@ __INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align(
// CHECK-NEXT: [[COERCE:%.*]] = alloca i128, align 16
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i128* [[A]] to { i64, i64 }*
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 0
// CHECK-NEXT: store i64 [[A_COERCE0]], i64* [[TMP1]], align 16
// CHECK-NEXT: store i64 [[A_COERCE0:%.*]], i64* [[TMP1]], align 16
// CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP0]], i32 0, i32 1
// CHECK-NEXT: store i64 [[A_COERCE1]], i64* [[TMP2]], align 8
// CHECK-NEXT: store i64 [[A_COERCE1:%.*]], i64* [[TMP2]], align 8
// CHECK-NEXT: [[A1:%.*]] = load i128, i128* [[A]], align 16
// CHECK-NEXT: store i128 [[A1]], i128* [[A_ADDR]], align 16
// CHECK-NEXT: [[TMP3:%.*]] = load i128, i128* [[A_ADDR]], align 16
@ -136,7 +130,7 @@ __INT32_TYPE__ *m4(struct MultiArgs s, __int128_t i) __attribute__((alloc_align(
// CHECK-NEXT: [[TMP11:%.*]] = load i64, i64* [[TMP10]], align 16
// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds { i64, i64 }, { i64, i64 }* [[TMP9]], i32 0, i32 1
// CHECK-NEXT: [[TMP13:%.*]] = load i64, i64* [[TMP12]], align 8
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m4(i64 [[TMP6]], i64 [[TMP8]], i64 [[TMP11]], i64 [[TMP13]])
// CHECK-NEXT: [[CALL:%.*]] = call i32* @m4(i64 [[TMP6]], i64 [[TMP8]], i64 noundef [[TMP11]], i64 noundef [[TMP13]])
// CHECK-NEXT: [[CASTED_ALIGN:%.*]] = trunc i128 [[TMP3]] to i64
// CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(i32* [[CALL]], i64 [[CASTED_ALIGN]]) ]
// CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[CALL]], align 4

2
clang/test/CodeGen/alloc-fns-alignment.c
View File

@ -48,7 +48,7 @@ void *aligned_alloc_large_constant_test(size_t n) {
// ALIGN16: align 16 i8* @realloc
// CHECK-LABEL: @aligned_alloc_variable_test
// ALIGN16: %[[ALLOCATED:.*]] = call align 16 i8* @aligned_alloc({{i32|i64}} %[[ALIGN:.*]], {{i32|i64}} %[[NBYTES:.*]])
// ALIGN16: %[[ALLOCATED:.*]] = call align 16 i8* @aligned_alloc({{i32|i64}} noundef %[[ALIGN:.*]], {{i32|i64}} noundef %[[NBYTES:.*]])
// ALIGN16-NEXT: call void @llvm.assume(i1 true) [ "align"(i8* %[[ALLOCATED]], {{i32|i64}} %[[ALIGN]]) ]
// CHECK-LABEL: @aligned_alloc_constant_test

12
clang/test/CodeGen/alloc-size-fnptr.c
View File

@ -14,9 +14,9 @@ extern void *my_calloc(int, int) __attribute__((alloc_size(1, 2)));
// CHECK-LABEL: @call_direct
void call_direct(void) {
my_malloc(50);
// CHECK: call i8* @my_malloc(i32 50) [[DIRECT_MALLOC_ATTR:#[0-9]+]]
// CHECK: call i8* @my_malloc(i32 noundef 50) [[DIRECT_MALLOC_ATTR:#[0-9]+]]
my_calloc(1, 16);
// CHECK: call i8* @my_calloc(i32 1, i32 16) [[DIRECT_CALLOC_ATTR:#[0-9]+]]
// CHECK: call i8* @my_calloc(i32 noundef 1, i32 noundef 16) [[DIRECT_CALLOC_ATTR:#[0-9]+]]
}
extern void *(*malloc_function_pointer)(void *, int)__attribute__((alloc_size(2)));
@ -26,10 +26,10 @@ extern void *(*calloc_function_pointer)(void *, int, int)__attribute__((alloc_si
void call_function_pointer(void) {
malloc_function_pointer(NULL, 100);
// CHECK: [[MALLOC_FN_PTR:%.+]] = load i8* (i8*, i32)*, i8* (i8*, i32)** @malloc_function_pointer, align 8
// CHECK: call i8* [[MALLOC_FN_PTR]](i8* null, i32 100) [[INDIRECT_MALLOC_ATTR:#[0-9]+]]
// CHECK: call i8* [[MALLOC_FN_PTR]](i8* noundef null, i32 noundef 100) [[INDIRECT_MALLOC_ATTR:#[0-9]+]]
calloc_function_pointer(NULL, 2, 4);
// CHECK: [[CALLOC_FN_PTR:%.+]] = load i8* (i8*, i32, i32)*, i8* (i8*, i32, i32)** @calloc_function_pointer, align 8
// CHECK: call i8* [[CALLOC_FN_PTR]](i8* null, i32 2, i32 4) [[INDIRECT_CALLOC_ATTR:#[0-9]+]]
// CHECK: call i8* [[CALLOC_FN_PTR]](i8* noundef null, i32 noundef 2, i32 noundef 4) [[INDIRECT_CALLOC_ATTR:#[0-9]+]]
}
typedef void *(__attribute__((alloc_size(3))) * my_malloc_fn_pointer_type)(void *, void *, int);
@ -41,10 +41,10 @@ extern my_calloc_fn_pointer_type calloc_function_pointer_with_typedef;
void call_function_pointer_typedef(void) {
malloc_function_pointer_with_typedef(NULL, NULL, 200);
// CHECK: [[INDIRECT_TYPEDEF_MALLOC_FN_PTR:%.+]] = load i8* (i8*, i8*, i32)*, i8* (i8*, i8*, i32)** @malloc_function_pointer_with_typedef, align 8
// CHECK: call i8* [[INDIRECT_TYPEDEF_MALLOC_FN_PTR]](i8* null, i8* null, i32 200) [[INDIRECT_TYPEDEF_MALLOC_ATTR:#[0-9]+]]
// CHECK: call i8* [[INDIRECT_TYPEDEF_MALLOC_FN_PTR]](i8* noundef null, i8* noundef null, i32 noundef 200) [[INDIRECT_TYPEDEF_MALLOC_ATTR:#[0-9]+]]
calloc_function_pointer_with_typedef(NULL, NULL, 8, 4);
// CHECK: [[INDIRECT_TYPEDEF_CALLOC_FN_PTR:%.+]] = load i8* (i8*, i8*, i32, i32)*, i8* (i8*, i8*, i32, i32)** @calloc_function_pointer_with_typedef, align 8
// CHECK: call i8* [[INDIRECT_TYPEDEF_CALLOC_FN_PTR]](i8* null, i8* null, i32 8, i32 4) [[INDIRECT_TYPEDEF_CALLOC_ATTR:#[0-9]+]]
// CHECK: call i8* [[INDIRECT_TYPEDEF_CALLOC_FN_PTR]](i8* noundef null, i8* noundef null, i32 noundef 8, i32 noundef 4) [[INDIRECT_TYPEDEF_CALLOC_ATTR:#[0-9]+]]
}
// CHECK: attributes [[DIRECT_MALLOC_ATTR]] = { allocsize(0) }

26
clang/test/CodeGen/arc/arguments.c
View File

@ -3,7 +3,7 @@
// Basic argument tests for ARC.
// CHECK: define{{.*}} void @f0(i32 inreg %i, i32 inreg %j, i64 inreg %k)
// CHECK: define{{.*}} void @f0(i32 inreg noundef %i, i32 inreg noundef %j, i64 inreg noundef %k)
void f0(int i, long j, long long k) {}
typedef struct {
@ -38,13 +38,13 @@ s3 f3() {
return foo;
}
// CHECK: define{{.*}} void @f4(i64 inreg %i)
// CHECK: define{{.*}} void @f4(i64 inreg noundef %i)
void f4(long long i) {}
// CHECK: define{{.*}} void @f5(i8 inreg signext %a, i16 inreg signext %b)
// CHECK: define{{.*}} void @f5(i8 inreg noundef signext %a, i16 inreg noundef signext %b)
void f5(signed char a, short b) {}
// CHECK: define{{.*}} void @f6(i8 inreg zeroext %a, i16 inreg zeroext %b)
// CHECK: define{{.*}} void @f6(i8 inreg noundef zeroext %a, i16 inreg noundef zeroext %b)
void f6(unsigned char a, unsigned short b) {}
enum my_enum {
@ -53,14 +53,14 @@ enum my_enum {
ENUM3,
};
// Enums should be treated as the underlying i32.
// CHECK: define{{.*}} void @f7(i32 inreg %a)
// CHECK: define{{.*}} void @f7(i32 inreg noundef %a)
void f7(enum my_enum a) {}
enum my_big_enum {
ENUM4 = 0xFFFFFFFFFFFFFFFF,
};
// Big enums should be treated as the underlying i64.
// CHECK: define{{.*}} void @f8(i64 inreg %a)
// CHECK: define{{.*}} void @f8(i64 inreg noundef %a)
void f8(enum my_big_enum a) {}
union simple_union {
@ -80,32 +80,32 @@ typedef struct {
// CHECK: define{{.*}} void @f10(i32 inreg %bf1.coerce)
void f10(bitfield1 bf1) {}
// CHECK: define{{.*}} inreg { float, float } @cplx1(float inreg %r)
// CHECK: define{{.*}} inreg { float, float } @cplx1(float inreg noundef %r)
_Complex float cplx1(float r) {
return r + 2.0fi;
}
// CHECK: define{{.*}} inreg { double, double } @cplx2(double inreg %r)
// CHECK: define{{.*}} inreg { double, double } @cplx2(double inreg noundef %r)
_Complex double cplx2(double r) {
return r + 2.0i;
}
// CHECK: define{{.*}} inreg { i32, i32 } @cplx3(i32 inreg %r)
// CHECK: define{{.*}} inreg { i32, i32 } @cplx3(i32 inreg noundef %r)
_Complex int cplx3(int r) {
return r + 2i;
}
// CHECK: define{{.*}} inreg { i64, i64 } @cplx4(i64 inreg %r)
// CHECK: define{{.*}} inreg { i64, i64 } @cplx4(i64 inreg noundef %r)
_Complex long long cplx4(long long r) {
return r + 2i;
}
// CHECK: define{{.*}} inreg { i8, i8 } @cplx6(i8 inreg signext %r)
// CHECK: define{{.*}} inreg { i8, i8 } @cplx6(i8 inreg noundef signext %r)
_Complex signed char cplx6(signed char r) {
return r + 2i;
}
// CHECK: define{{.*}} inreg { i16, i16 } @cplx7(i16 inreg signext %r)
// CHECK: define{{.*}} inreg { i16, i16 } @cplx7(i16 inreg noundef signext %r)
_Complex short cplx7(short r) {
return r + 2i;
}
@ -128,7 +128,7 @@ void st3(s16 a, s16 b, s16 c) {}
// 1 sret + 1 i32 + 2*(i32 coerce) + 4*(i32 coerce) + 1 byval
s16 st4(int x, s8 a, s16 b, s16 c) { return b; }
// CHECK: define{{.*}} void @st4(%struct.s16* noalias sret(%struct.s16) align 4 %agg.result, i32 inreg %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce)
// CHECK: define{{.*}} void @st4(%struct.s16* noalias sret(%struct.s16) align 4 %agg.result, i32 inreg noundef %x, i32 inreg %a.coerce0, i32 inreg %a.coerce1, i32 inreg %b.coerce0, i32 inreg %b.coerce1, i32 inreg %b.coerce2, i32 inreg %b.coerce3, { i32, i32, i32, i32 } %c.coerce)
// 1 sret + 2*(i32 coerce) + 4*(i32 coerce) + 4*(i32 coerce)
s16 st5(s8 a, s16 b, s16 c) { return b; }

10
clang/test/CodeGen/arithmetic-fence-builtin.c
View File

@ -14,7 +14,7 @@
//
int v;
int addit(float a, float b) {
// CHECK: define {{.*}}@addit(float %a, float %b) #0 {
// CHECK: define {{.*}}@addit(float noundef %a, float noundef %b) #0 {
_Complex double cd, cd1;
cd = __arithmetic_fence(cd1);
// CHECKFAST: call{{.*}} double @llvm.arithmetic.fence.f64({{.*}}real)
@ -57,18 +57,18 @@ int addit(float a, float b) {
// CHECK-NEXT ret i32 0
}
int addit1(int a, int b) {
// CHECK: define {{.*}}@addit1(i32 %a, i32 %b{{.*}}
// CHECK: define {{.*}}@addit1(i32 noundef %a, i32 noundef %b{{.*}}
v = (a + b);
// CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.int(float %add)
// CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.int(float noundef %add)
return 0;
}
#ifdef FAST
#pragma float_control(precise, on)
int subit(float a, float b, float *fp) {
// CHECKFAST: define {{.*}}@subit(float %a, float %b{{.*}}
// CHECKFAST: define {{.*}}@subit(float noundef %a, float noundef %b{{.*}}
*fp = __arithmetic_fence(a - b);
*fp = (a + b);
// CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.f32(float %add)
// CHECK-NOT: call{{.*}} float @llvm.arithmetic.fence.f32(float noundef %add)
return 0;
}
#endif

24
clang/test/CodeGen/arm-aapcs-vfp.c
View File

@ -48,15 +48,15 @@ void test_array(struct nested_array arg) {
}
extern void complex_callee(__complex__ double);
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex({ double, double } %{{.*}})
// CHECK64: define{{.*}} void @test_complex([2 x double] %cd.coerce)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex({ double, double } noundef %{{.*}})
// CHECK64: define{{.*}} void @test_complex([2 x double] noundef %cd.coerce)
void test_complex(__complex__ double cd) {
complex_callee(cd);
}
// Long double is the same as double on AAPCS, it should be homogeneous.
extern void complex_long_callee(__complex__ long double);
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex_long({ double, double } %{{.*}})
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_complex_long({ double, double } noundef %{{.*}})
void test_complex_long(__complex__ long double cd) {
complex_callee(cd);
}
@ -71,7 +71,7 @@ struct big_struct {
float f4;
};
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_big([5 x i32] %{{.*}})
// CHECK64: define{{.*}} void @test_big(%struct.big_struct* %{{.*}})
// CHECK64: define{{.*}} void @test_big(%struct.big_struct* noundef %{{.*}})
// CHECK64: call void @llvm.memcpy
// CHECK64: call void @big_callee(%struct.big_struct*
extern void big_callee(struct big_struct);
@ -115,36 +115,36 @@ void test_neon(struct neon_struct arg) {
neon_callee(arg);
}
// CHECK-LABEL: define{{.*}} arm_aapcs_vfpcc void @f33(%struct.s33* byval(%struct.s33) align 4 %s)
// CHECK-LABEL: define{{.*}} arm_aapcs_vfpcc void @f33(%struct.s33* noundef byval(%struct.s33) align 4 %s)
struct s33 { char buf[32*32]; };
void f33(struct s33 s) { }
typedef struct { long long x; int y; } struct_long_long_int;
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_1(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i64 %k, i32 %l)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_1(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, i64 noundef %k, i32 noundef %l)
void test_vfp_stack_gpr_split_1(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, long long k, int l) {}
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [2 x i64] %k.coerce)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_2(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, [2 x i64] %k.coerce)
void test_vfp_stack_gpr_split_2(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_long_long_int k) {}
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(%struct.struct_long_long_int* noalias sret(%struct.struct_long_long_int) align 8 %agg.result, double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, [2 x i64] %k.coerce)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_3(%struct.struct_long_long_int* noalias sret(%struct.struct_long_long_int) align 8 %agg.result, double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, [2 x i64] %k.coerce)
struct_long_long_int test_vfp_stack_gpr_split_3(double a, double b, double c, double d, double e, double f, double g, double h, double i, struct_long_long_int k) {}
typedef struct { int a; int b:4; int c; } struct_int_bitfield_int;
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_test_vfp_stack_gpr_split_bitfield(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, i32 %k, [3 x i32] %l.coerce)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_test_vfp_stack_gpr_split_bitfield(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, i32 noundef %k, [3 x i32] %l.coerce)
void test_test_vfp_stack_gpr_split_bitfield(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, int k, struct_int_bitfield_int l) {}
// Note: this struct requires internal padding
typedef struct { int x; long long y; } struct_int_long_long;
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_4(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, [2 x i64] %k.coerce)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_4(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, [2 x i64] %k.coerce)
void test_vfp_stack_gpr_split_4(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_int_long_long k) {}
// This very large struct (passed byval) uses up the GPRs, so no padding is needed
typedef struct { int x[17]; } struct_seventeen_ints;
typedef struct { int x[4]; } struct_four_ints;
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_5(%struct.struct_seventeen_ints* byval(%struct.struct_seventeen_ints) align 4 %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, double %j, [4 x i32] %k.coerce)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_5(%struct.struct_seventeen_ints* noundef byval(%struct.struct_seventeen_ints) align 4 %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, double noundef %j, [4 x i32] %k.coerce)
void test_vfp_stack_gpr_split_5(struct_seventeen_ints a, double b, double c, double d, double e, double f, double g, double h, double i, double j, struct_four_ints k) {}
// Here, parameter k would need padding to prevent it from being split, but it
// is passed ByVal (due to being > 64 bytes), so the backend handles this instead.
void test_vfp_stack_gpr_split_6(double a, double b, double c, double d, double e, double f, double g, double h, double i, int j, struct_seventeen_ints k) {}
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_6(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i, i32 %j, %struct.struct_seventeen_ints* byval(%struct.struct_seventeen_ints) align 4 %k)
// CHECK: define{{.*}} arm_aapcs_vfpcc void @test_vfp_stack_gpr_split_6(double noundef %a, double noundef %b, double noundef %c, double noundef %d, double noundef %e, double noundef %f, double noundef %g, double noundef %h, double noundef %i, i32 noundef %j, %struct.struct_seventeen_ints* noundef byval(%struct.struct_seventeen_ints) align 4 %k)

48
clang/test/CodeGen/arm-abi-vector.c
View File

@ -48,11 +48,11 @@ double varargs_vec_2i(int fixed, ...) {
double test_2i(__int2 *in) {
// CHECK: test_2i
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_2i(i32 noundef 3, <2 x i32> noundef {{%.*}})
// APCS-GNU: test_2i
// APCS-GNU: call double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_2i(i32 noundef 3, <2 x i32> noundef {{%.*}})
// ANDROID: test_2i
// ANDROID: call double (i32, ...) @varargs_vec_2i(i32 3, <2 x i32> {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_2i(i32 noundef 3, <2 x i32> noundef {{%.*}})
return varargs_vec_2i(3, *in);
}
@ -80,11 +80,11 @@ double varargs_vec_3c(int fixed, ...) {
double test_3c(__char3 *in) {
// CHECK: test_3c
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3c(i32 noundef 3, i32 {{%.*}})
// APCS-GNU: test_3c
// APCS-GNU: call double (i32, ...) @varargs_vec_3c(i32 3, i32 {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_3c(i32 noundef 3, i32 {{%.*}})
// ANDROID: test_3c
// ANDROID: call double (i32, ...) @varargs_vec_3c(i32 3, <3 x i8> {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_3c(i32 noundef 3, <3 x i8> noundef {{%.*}})
return varargs_vec_3c(3, *in);
}
@ -123,11 +123,11 @@ double varargs_vec_5c(int fixed, ...) {
double test_5c(__char5 *in) {
// CHECK: test_5c
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}})
// APCS-GNU: test_5c
// APCS-GNU: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}})
// ANDROID: test_5c
// ANDROID: call double (i32, ...) @varargs_vec_5c(i32 5, <2 x i32> {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_5c(i32 noundef 5, <2 x i32> {{%.*}})
return varargs_vec_5c(5, *in);
}
@ -166,11 +166,11 @@ double varargs_vec_9c(int fixed, ...) {
double test_9c(__char9 *in) {
// CHECK: test_9c
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}})
// APCS-GNU: test_9c
// APCS-GNU: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}})
// ANDROID: test_9c
// ANDROID: call double (i32, ...) @varargs_vec_9c(i32 9, <4 x i32> {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_9c(i32 noundef 9, <4 x i32> {{%.*}})
return varargs_vec_9c(9, *in);
}
@ -198,11 +198,11 @@ double varargs_vec_19c(int fixed, ...) {
double test_19c(__char19 *in) {
// CHECK: test_19c
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}})
// APCS-GNU: test_19c
// APCS-GNU: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}})
// ANDROID: test_19c
// ANDROID: call double (i32, ...) @varargs_vec_19c(i32 19, <19 x i8>* {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_19c(i32 noundef 19, <19 x i8>* noundef {{%.*}})
return varargs_vec_19c(19, *in);
}
@ -236,11 +236,11 @@ double varargs_vec_3s(int fixed, ...) {
double test_3s(__short3 *in) {
// CHECK: test_3s
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_3s(i32 noundef 3, <2 x i32> {{%.*}})
// APCS-GNU: test_3s
// APCS-GNU: call double (i32, ...) @varargs_vec_3s(i32 3, <2 x i32> {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_3s(i32 noundef 3, <2 x i32> {{%.*}})
// ANDROID: test_3s
// ANDROID: call double (i32, ...) @varargs_vec_3s(i32 3, <3 x i16> {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_3s(i32 noundef 3, <3 x i16> noundef {{%.*}})
return varargs_vec_3s(3, *in);
}
@ -278,11 +278,11 @@ double varargs_vec_5s(int fixed, ...) {
double test_5s(__short5 *in) {
// CHECK: test_5s
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}})
// APCS-GNU: test_5s
// APCS-GNU: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}})
// ANDROID: test_5s
// ANDROID: call double (i32, ...) @varargs_vec_5s(i32 5, <4 x i32> {{%.*}})
// ANDROID: call double (i32, ...) @varargs_vec_5s(i32 noundef 5, <4 x i32> {{%.*}})
return varargs_vec_5s(5, *in);
}
@ -320,10 +320,10 @@ double varargs_struct(int fixed, ...) {
double test_struct(StructWithVec* d) {
// CHECK: test_struct
// CHECK: call arm_aapcscc double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}})
// CHECK: call arm_aapcscc double (i32, ...) @varargs_struct(i32 noundef 3, [2 x i64] {{%.*}})
// APCS-GNU: test_struct
// APCS-GNU: call double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}})
// APCS-GNU: call double (i32, ...) @varargs_struct(i32 noundef 3, [2 x i64] {{%.*}})
// ANDROID: test_struct
// ANDROID: call double (i32, ...) @varargs_struct(i32 3, [2 x i64] {{%.*}})
// ANDROID: call double (i32, ...) @varargs_struct(i32 noundef 3, [2 x i64] {{%.*}})
return varargs_struct(3, *d);
}

10
clang/test/CodeGen/arm-arguments.c
View File

@ -176,14 +176,14 @@ void f32(struct s32 s) { }
// PR13350
struct s33 { char buf[32*32]; };
void f33(struct s33 s) { }
// APCS-GNU-LABEL: define{{.*}} void @f33(%struct.s33* byval(%struct.s33) align 4 %s)
// AAPCS-LABEL: define{{.*}} arm_aapcscc void @f33(%struct.s33* byval(%struct.s33) align 4 %s)
// APCS-GNU-LABEL: define{{.*}} void @f33(%struct.s33* noundef byval(%struct.s33) align 4 %s)
// AAPCS-LABEL: define{{.*}} arm_aapcscc void @f33(%struct.s33* noundef byval(%struct.s33) align 4 %s)
// PR14048
struct s34 { char c; };
void f34(struct s34 s);
void g34(struct s34 *s) { f34(*s); }
// AAPCS: @g34(%struct.s34* %s)
// AAPCS: @g34(%struct.s34* noundef %s)
// AAPCS: %[[a:.*]] = alloca [1 x i32]
// AAPCS: load [1 x i32], [1 x i32]* %[[a]]
@ -204,7 +204,7 @@ float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) {
*(float32x4_t *)&s2);
return v;
}
// APCS-GNU-LABEL: define{{.*}} <4 x float> @f35(i32 %i, %struct.s35* byval(%struct.s35) align 4 %0, %struct.s35* byval(%struct.s35) align 4 %1)
// APCS-GNU-LABEL: define{{.*}} <4 x float> @f35(i32 noundef %i, %struct.s35* noundef byval(%struct.s35) align 4 %0, %struct.s35* noundef byval(%struct.s35) align 4 %1)
// APCS-GNU: %[[a:.*]] = alloca %struct.s35, align 16
// APCS-GNU: %[[b:.*]] = bitcast %struct.s35* %[[a]] to i8*
// APCS-GNU: %[[c:.*]] = bitcast %struct.s35* %0 to i8*
@ -212,7 +212,7 @@ float32x4_t f35(int i, s35_with_align s1, s35_with_align s2) {
// APCS-GNU: %[[d:.*]] = bitcast %struct.s35* %[[a]] to <4 x float>*
// APCS-GNU: load <4 x float>, <4 x float>* %[[d]], align 16
// AAPCS-LABEL: define{{.*}} arm_aapcscc <4 x float> @f35(i32 %i, %struct.s35* byval(%struct.s35) align 4 %s1, %struct.s35* byval(%struct.s35) align 4 %s2)
// AAPCS-LABEL: define{{.*}} arm_aapcscc <4 x float> @f35(i32 noundef %i, %struct.s35* noundef byval(%struct.s35) align 4 %s1, %struct.s35* noundef byval(%struct.s35) align 4 %s2)
// AAPCS: %[[a_addr:.*]] = alloca <4 x float>, align 16
// AAPCS: %[[b_addr:.*]] = alloca <4 x float>, align 16
// AAPCS: %[[p1:.*]] = bitcast %struct.s35* %s1 to <4 x float>*

10
clang/test/CodeGen/arm-bf16-params-returns.c
View File

@ -10,19 +10,19 @@
__bf16 test_ret_bf16(__bf16 v) {
return v;
}
// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc bfloat @test_ret_bf16(bfloat noundef returned %v) {{.*}} {
// CHECK32-HARD: ret bfloat %v
// CHECK32-SOFTFP: define{{.*}} bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
// CHECK32-SOFTFP: define{{.*}} bfloat @test_ret_bf16(bfloat noundef returned %v) {{.*}} {
// CHECK32-SOFTFP: ret bfloat %v
// CHECK64: define{{.*}} bfloat @test_ret_bf16(bfloat returned %v) {{.*}} {
// CHECK64: define{{.*}} bfloat @test_ret_bf16(bfloat noundef returned %v) {{.*}} {
// CHECK64: ret bfloat %v
bfloat16x4_t test_ret_bf16x4_t(bfloat16x4_t v) {
return v;
}
// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} {
// CHECK32-HARD: define{{.*}} arm_aapcs_vfpcc <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) {{.*}} {
// CHECK32-HARD: ret <4 x bfloat> %v
// CHECK32-SOFTFP: define{{.*}} <2 x i32> @test_ret_bf16x4_t(<2 x i32> [[V0:.*]]) {{.*}} {
// CHECK32-SOFTFP: ret <2 x i32> %v
// CHECK64: define{{.*}} <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> returned %v) {{.*}} {
// CHECK64: define{{.*}} <4 x bfloat> @test_ret_bf16x4_t(<4 x bfloat> noundef returned %v) {{.*}} {
// CHECK64: ret <4 x bfloat> %v

2
clang/test/CodeGen/arm-byval-align.c
View File

@ -7,7 +7,7 @@ struct foo {
int d[16];
};
// CHECK: %struct.foo* byval(%struct.foo) align 8 %z
// CHECK: %struct.foo* noundef byval(%struct.foo) align 8 %z
long long bar(int a, int b, int c, int d, int e,
struct foo z) {
return z.a;

4
clang/test/CodeGen/arm-cmse-attr.c
View File

@ -29,9 +29,9 @@ void f4() __attribute__((cmse_nonsecure_entry))
{
}
// CHECK: define{{.*}} void @f1(void ()* nocapture readonly %fptr) {{[^#]*}}#0 {
// CHECK: define{{.*}} void @f1(void ()* nocapture noundef readonly %fptr) {{[^#]*}}#0 {
// CHECK: call void %fptr() #2
// CHECK: define{{.*}} void @f2(void ()* nocapture readonly %fptr) {{[^#]*}}#0 {
// CHECK: define{{.*}} void @f2(void ()* nocapture noundef readonly %fptr) {{[^#]*}}#0 {
// CHECK: call void %fptr() #2
// CHECK: define{{.*}} void @f3() {{[^#]*}}#1 {
// CHECK: define{{.*}} void @f4() {{[^#]*}}#1 {

4
clang/test/CodeGen/arm-cmse-call.c
View File

@ -40,7 +40,7 @@ void f(int i) {
p2(i);
// CHECK: %[[#P2:]] = load {{.*}} @p2
// CHECK: call void %[[#P2]](i32 %i) #[[#A2]]
// CHECK: call void %[[#P2]](i32 noundef %i) #[[#A2]]
a0[i]();
// CHECK: %[[EP0:.*]] = getelementptr {{.*}} @a0
@ -70,7 +70,7 @@ void f(int i) {
b[i](i);
// CHECK: %[[EP5:.*]] = getelementptr {{.*}} @b
// CHECK: %[[#E5:]] = load {{.*}} %[[EP5]]
// CHECK: call void %[[#E5]](i32 %i) #[[#A2]]
// CHECK: call void %[[#E5]](i32 noundef %i) #[[#A2]]
}
// CHECK: attributes #[[#A1]] = { nounwind }

76
clang/test/CodeGen/arm-float-helpers.c
View File

@ -32,192 +32,192 @@
// other runtime functions such as the _Complex helper routines are not covered.
float fadd(float a, float b) { return a + b; }
// CHECK-LABEL: define{{.*}} float @fadd(float %a, float %b)
// CHECK-LABEL: define{{.*}} float @fadd(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fadd
// CHECK: %add = fadd float {{.*}}, {{.*}}
float fdiv(float a, float b) { return a / b; }
// CHECK-LABEL: define{{.*}} float @fdiv(float %a, float %b)
// CHECK-LABEL: define{{.*}} float @fdiv(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fdiv
// CHECK: %div = fdiv float {{.*}}, {{.*}}
float fmul(float a, float b) { return a * b; }
// CHECK-LABEL: define{{.*}} float @fmul(float %a, float %b)
// CHECK-LABEL: define{{.*}} float @fmul(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fmul
// CHECK: %mul = fmul float {{.*}}, {{.*}}
float fsub(float a, float b) { return a - b; }
// CHECK-LABEL: define{{.*}} float @fsub(float %a, float %b)
// CHECK-LABEL: define{{.*}} float @fsub(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fsub
// CHECK: %sub = fsub float {{.*}}, {{.*}}
int fcmpeq(float a, float b) { return a == b; }
// CHECK-LABEL: define{{.*}} i32 @fcmpeq(float %a, float %b)
// CHECK-LABEL: define{{.*}} i32 @fcmpeq(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fcmpeq
// CHECK: %cmp = fcmp oeq float {{.*}}, {{.*}}
int fcmplt(float a, float b) { return a < b; }
// CHECK-LABEL: define{{.*}} i32 @fcmplt(float %a, float %b)
// CHECK-LABEL: define{{.*}} i32 @fcmplt(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fcmplt
// CHECK: %cmp = fcmp olt float {{.*}}, {{.*}}
int fcmple(float a, float b) { return a <= b; }
// CHECK-LABEL: define{{.*}} i32 @fcmple(float %a, float %b)
// CHECK-LABEL: define{{.*}} i32 @fcmple(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fcmple
// CHECK: %cmp = fcmp ole float {{.*}}, {{.*}}
int fcmpge(float a, float b) { return a >= b; }
// CHECK-LABEL: define{{.*}} i32 @fcmpge(float %a, float %b)
// CHECK-LABEL: define{{.*}} i32 @fcmpge(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fcmpge
// CHECK: %cmp = fcmp oge float {{.*}}, {{.*}}
int fcmpgt(float a, float b) { return a > b; }
// CHECK-LABEL: define{{.*}} i32 @fcmpgt(float %a, float %b)
// CHECK-LABEL: define{{.*}} i32 @fcmpgt(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fcmpgt
// CHECK: %cmp = fcmp ogt float {{.*}}, {{.*}}
int fcmpun(float a, float b) { return __builtin_isunordered(a, b); }
// CHECK-LABEL: define{{.*}} i32 @fcmpun(float %a, float %b)
// CHECK-LABEL: define{{.*}} i32 @fcmpun(float noundef %a, float noundef %b)
// CHECK-NOT: __aeabi_fcmpun
// CHECK: %cmp = fcmp uno float {{.*}}, {{.*}}
double dadd(double a, double b) { return a + b; }
// CHECK-LABEL: define{{.*}} double @dadd(double %a, double %b)
// CHECK-LABEL: define{{.*}} double @dadd(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dadd
// CHECK: %add = fadd double {{.*}}, {{.*}}
double ddiv(double a, double b) { return a / b; }
// CHECK-LABEL: define{{.*}} double @ddiv(double %a, double %b)
// CHECK-LABEL: define{{.*}} double @ddiv(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_ddiv
// CHECK: %div = fdiv double {{.*}}, {{.*}}
double dmul(double a, double b) { return a * b; }
// CHECK-LABEL: define{{.*}} double @dmul(double %a, double %b)
// CHECK-LABEL: define{{.*}} double @dmul(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dmul
// CHECK: %mul = fmul double {{.*}}, {{.*}}
double dsub(double a, double b) { return a - b; }
// CHECK-LABEL: define{{.*}} double @dsub(double %a, double %b)
// CHECK-LABEL: define{{.*}} double @dsub(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dsub
// CHECK: %sub = fsub double {{.*}}, {{.*}}
int dcmpeq(double a, double b) { return a == b; }
// CHECK-LABEL: define{{.*}} i32 @dcmpeq(double %a, double %b)
// CHECK-LABEL: define{{.*}} i32 @dcmpeq(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dcmpeq
// CHECK: %cmp = fcmp oeq double {{.*}}, {{.*}}
int dcmplt(double a, double b) { return a < b; }
// CHECK-LABEL: define{{.*}} i32 @dcmplt(double %a, double %b)
// CHECK-LABEL: define{{.*}} i32 @dcmplt(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dcmplt
// CHECK: %cmp = fcmp olt double {{.*}}, {{.*}}
int dcmple(double a, double b) { return a <= b; }
// CHECK-LABEL: define{{.*}} i32 @dcmple(double %a, double %b)
// CHECK-LABEL: define{{.*}} i32 @dcmple(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dcmple
// CHECK: %cmp = fcmp ole double {{.*}}, {{.*}}
int dcmpge(double a, double b) { return a >= b; }
// CHECK-LABEL: define{{.*}} i32 @dcmpge(double %a, double %b)
// CHECK-LABEL: define{{.*}} i32 @dcmpge(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dcmpge
// CHECK: %cmp = fcmp oge double {{.*}}, {{.*}}
int dcmpgt(double a, double b) { return a > b; }
// CHECK-LABEL: define{{.*}} i32 @dcmpgt(double %a, double %b)
// CHECK-LABEL: define{{.*}} i32 @dcmpgt(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dcmpgt
// CHECK: %cmp = fcmp ogt double {{.*}}, {{.*}}
int dcmpun(double a, double b) { return __builtin_isunordered(a, b); }
// CHECK-LABEL: define{{.*}} i32 @dcmpun(double %a, double %b)
// CHECK-LABEL: define{{.*}} i32 @dcmpun(double noundef %a, double noundef %b)
// CHECK-NOT: __aeabi_dcmpun
// CHECK: %cmp = fcmp uno double {{.*}}, {{.*}}
int d2iz(double a) { return (int)a; }
// CHECK-LABEL: define{{.*}} i32 @d2iz(double %a)
// CHECK-LABEL: define{{.*}} i32 @d2iz(double noundef %a)
// CHECK-NOT: __aeabi_d2iz
// CHECK: %conv = fptosi double {{.*}} to i32
unsigned int d2uiz(double a) { return (unsigned int)a; }
// CHECK-LABEL: define{{.*}} i32 @d2uiz(double %a)
// CHECK-LABEL: define{{.*}} i32 @d2uiz(double noundef %a)
// CHECK-NOT: __aeabi_d2uiz
// CHECK: %conv = fptoui double {{.*}} to i32
long long d2lz(double a) { return (long long)a; }
// CHECK-LABEL: define{{.*}} i64 @d2lz(double %a)
// CHECK-LABEL: define{{.*}} i64 @d2lz(double noundef %a)
// CHECK-NOT: __aeabi_d2lz
// CHECK: %conv = fptosi double {{.*}} to i64
unsigned long long d2ulz(double a) { return (unsigned long long)a; }
// CHECK-LABEL: define{{.*}} i64 @d2ulz(double %a)
// CHECK-LABEL: define{{.*}} i64 @d2ulz(double noundef %a)
// CHECK-NOT: __aeabi_d2ulz
// CHECK: %conv = fptoui double {{.*}} to i64
int f2iz(float a) { return (int)a; }
// CHECK-LABEL: define{{.*}} i32 @f2iz(float %a)
// CHECK-LABEL: define{{.*}} i32 @f2iz(float noundef %a)
// CHECK-NOT: __aeabi_f2iz
// CHECK: %conv = fptosi float {{.*}} to i32
unsigned int f2uiz(float a) { return (unsigned int)a; }
// CHECK-LABEL: define{{.*}} i32 @f2uiz(float %a)
// CHECK-LABEL: define{{.*}} i32 @f2uiz(float noundef %a)
// CHECK-NOT: __aeabi_f2uiz
// CHECK: %conv = fptoui float {{.*}} to i32
long long f2lz(float a) { return (long long)a; }
// CHECK-LABEL: define{{.*}} i64 @f2lz(float %a)
// CHECK-LABEL: define{{.*}} i64 @f2lz(float noundef %a)
// CHECK-NOT: __aeabi_f2lz
// CHECK: %conv = fptosi float {{.*}} to i64
unsigned long long f2ulz(float a) { return (unsigned long long)a; }
// CHECK-LABEL: define{{.*}} i64 @f2ulz(float %a)
// CHECK-LABEL: define{{.*}} i64 @f2ulz(float noundef %a)
// CHECK-NOT: __aeabi_f2ulz
// CHECK: %conv = fptoui float {{.*}} to i64
float d2f(double a) { return (float)a; }
// CHECK-LABEL: define{{.*}} float @d2f(double %a)
// CHECK-LABEL: define{{.*}} float @d2f(double noundef %a)
// CHECK-NOT: __aeabi_d2f
// CHECK: %conv = fptrunc double {{.*}} to float
double f2d(float a) { return (double)a; }
// CHECK-LABEL: define{{.*}} double @f2d(float %a)
// CHECK-LABEL: define{{.*}} double @f2d(float noundef %a)
// CHECK-NOT: __aeabi_f2d
// CHECK: %conv = fpext float {{.*}} to double
double i2d(int a) { return (double)a; }
// CHECK-LABEL: define{{.*}} double @i2d(i32 %a)
// CHECK-LABEL: define{{.*}} double @i2d(i32 noundef %a)
// CHECK-NOT: __aeabi_i2d
// CHECK: %conv = sitofp i32 {{.*}} to double
double ui2d(unsigned int a) { return (double)a; }
// CHECK-LABEL: define{{.*}} double @ui2d(i32 %a)
// CHECK-LABEL: define{{.*}} double @ui2d(i32 noundef %a)
// CHECK-NOT: __aeabi_ui2d
// CHECK: %conv = uitofp i32 {{.*}} to double
double l2d(long long a) { return (double)a; }
// CHECK-LABEL: define{{.*}} double @l2d(i64 %a)
// CHECK-LABEL: define{{.*}} double @l2d(i64 noundef %a)
// CHECK-NOT: __aeabi_l2d
// CHECK: %conv = sitofp i64 {{.*}} to double
double ul2d(unsigned long long a) { return (unsigned long long)a; }
// CHECK-LABEL: define{{.*}} double @ul2d(i64 %a)
// CHECK-LABEL: define{{.*}} double @ul2d(i64 noundef %a)
// CHECK-NOT: __aeabi_ul2d
// CHECK: %conv = uitofp i64 {{.*}} to double
float i2f(int a) { return (int)a; }
// CHECK-LABEL: define{{.*}} float @i2f(i32 %a)
// CHECK-LABEL: define{{.*}} float @i2f(i32 noundef %a)
// CHECK-NOT: __aeabi_i2f
// CHECK: %conv = sitofp i32 {{.*}} to float
float ui2f(unsigned int a) { return (unsigned int)a; }
// CHECK-LABEL: define{{.*}} float @ui2f(i32 %a)
// CHECK-LABEL: define{{.*}} float @ui2f(i32 noundef %a)
// CHECK-NOT: __aeabi_ui2f
// CHECK: %conv = uitofp i32 {{.*}} to float
float l2f(long long a) { return (long long)a; }
// CHECK-LABEL: define{{.*}} float @l2f(i64 %a)
// CHECK-LABEL: define{{.*}} float @l2f(i64 noundef %a)
// CHECK-NOT: __aeabi_l2f
// CHECK: %conv = sitofp i64 {{.*}} to float
float ul2f(unsigned long long a) { return (unsigned long long)a; }
// CHECK-LABEL: define{{.*}} float @ul2f(i64 %a)
// CHECK-LABEL: define{{.*}} float @ul2f(i64 noundef %a)
// CHECK-NOT: __aeabi_ul2f
// CHECK: %conv = uitofp i64 {{.*}} to float

12
clang/test/CodeGen/arm-fp16-arguments.c
View File

@ -5,9 +5,9 @@
__fp16 g;
void t1(__fp16 a) { g = a; }
// SOFT: define{{.*}} void @t1(half [[PARAM:%.*]])
// HARD: define{{.*}} arm_aapcs_vfpcc void @t1(half [[PARAM:%.*]])
// NATIVE: define{{.*}} void @t1(half [[PARAM:%.*]])
// SOFT: define{{.*}} void @t1(half noundef [[PARAM:%.*]])
// HARD: define{{.*}} arm_aapcs_vfpcc void @t1(half noundef [[PARAM:%.*]])
// NATIVE: define{{.*}} void @t1(half noundef [[PARAM:%.*]])
// CHECK: store half [[PARAM]], half* @g
__fp16 t2() { return g; }
@ -20,9 +20,9 @@ __fp16 t2() { return g; }
_Float16 h;
void t3(_Float16 a) { h = a; }
// SOFT: define{{.*}} void @t3(half [[PARAM:%.*]])
// HARD: define{{.*}} arm_aapcs_vfpcc void @t3(half [[PARAM:%.*]])
// NATIVE: define{{.*}} void @t3(half [[PARAM:%.*]])
// SOFT: define{{.*}} void @t3(half noundef [[PARAM:%.*]])
// HARD: define{{.*}} arm_aapcs_vfpcc void @t3(half noundef [[PARAM:%.*]])
// NATIVE: define{{.*}} void @t3(half noundef [[PARAM:%.*]])
// CHECK: store half [[PARAM]], half* @h
_Float16 t4() { return h; }

2
clang/test/CodeGen/arm-homogenous.c
View File

@ -95,7 +95,7 @@ void test_array_of_floats(void) {
float a[4] = {1.0, 2.0, 3.0, 4.0};
takes_array_of_floats(a);
}
// CHECK: declare arm_aapcs_vfpcc void @takes_array_of_floats(float*)
// CHECK: declare arm_aapcs_vfpcc void @takes_array_of_floats(float* noundef)
/* Struct-type homogenous aggregate */
typedef struct {

2
clang/test/CodeGen/arm-mangle-bf16.cpp
View File

@ -2,5 +2,5 @@
// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi hard -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple arm-arm-none-eabi -target-feature +bf16 -mfloat-abi softfp -emit-llvm -o - %s | FileCheck %s
// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat %b)
// CHECK: define {{.*}}void @_Z3foou6__bf16(bfloat noundef %b)
void foo(__bf16 b) {}

30
clang/test/CodeGen/arm-neon-directed-rounding.c
View File

@ -9,7 +9,7 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnda_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnda_f32(<2 x float> noundef %a)
// CHECK-A32: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a)
// CHECK-A64: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRNDA_V1_I]]
@ -17,7 +17,7 @@ float32x2_t test_vrnda_f32(float32x2_t a) {
return vrnda_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndaq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndaq_f32(<4 x float> noundef %a)
// CHECK-A32: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a)
// CHECK-A64: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDAQ_V1_I]]
@ -25,7 +25,7 @@ float32x4_t test_vrndaq_f32(float32x4_t a) {
return vrndaq_f32(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndm_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndm_f32(<2 x float> noundef %a)
// CHECK-A32: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> %a)
// CHECK-A64: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRNDM_V1_I]]
@ -33,7 +33,7 @@ float32x2_t test_vrndm_f32(float32x2_t a) {
return vrndm_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndmq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndmq_f32(<4 x float> noundef %a)
// CHECK-A32: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> %a)
// CHECK-A64: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDMQ_V1_I]]
@ -41,7 +41,7 @@ float32x4_t test_vrndmq_f32(float32x4_t a) {
return vrndmq_f32(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndn_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndn_f32(<2 x float> noundef %a)
// CHECK-A32: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> %a)
// CHECK-A64: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRNDN_V1_I]]
@ -49,7 +49,7 @@ float32x2_t test_vrndn_f32(float32x2_t a) {
return vrndn_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndnq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndnq_f32(<4 x float> noundef %a)
// CHECK-A32: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintn.v4f32(<4 x float> %a)
// CHECK-A64: [[VRNDNQ_V1_I:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDNQ_V1_I]]
@ -57,7 +57,7 @@ float32x4_t test_vrndnq_f32(float32x4_t a) {
return vrndnq_f32(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndp_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndp_f32(<2 x float> noundef %a)
// CHECK-A32: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintp.v2f32(<2 x float> %a)
// CHECK-A64: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRNDP_V1_I]]
@ -65,7 +65,7 @@ float32x2_t test_vrndp_f32(float32x2_t a) {
return vrndp_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndpq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndpq_f32(<4 x float> noundef %a)
// CHECK-A32: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintp.v4f32(<4 x float> %a)
// CHECK-A64: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDPQ_V1_I]]
@ -73,7 +73,7 @@ float32x4_t test_vrndpq_f32(float32x4_t a) {
return vrndpq_f32(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndx_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndx_f32(<2 x float> noundef %a)
// CHECK-A32: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintx.v2f32(<2 x float> %a)
// CHECK-A64: [[VRNDX_V1_I:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRNDX_V1_I]]
@ -81,7 +81,7 @@ float32x2_t test_vrndx_f32(float32x2_t a) {
return vrndx_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndxq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndxq_f32(<4 x float> noundef %a)
// CHECK-A32: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintx.v4f32(<4 x float> %a)
// CHECK-A64: [[VRNDXQ_V1_I:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDXQ_V1_I]]
@ -89,7 +89,7 @@ float32x4_t test_vrndxq_f32(float32x4_t a) {
return vrndxq_f32(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnd_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrnd_f32(<2 x float> noundef %a)
// CHECK-A32: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintz.v2f32(<2 x float> %a)
// CHECK-A64: [[VRND_V1_I:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRND_V1_I]]
@ -97,7 +97,7 @@ float32x2_t test_vrnd_f32(float32x2_t a) {
return vrnd_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndq_f32(<4 x float> noundef %a)
// CHECK-A32: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintz.v4f32(<4 x float> %a)
// CHECK-A64: [[VRNDQ_V1_I:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDQ_V1_I]]
@ -105,7 +105,7 @@ float32x4_t test_vrndq_f32(float32x4_t a) {
return vrndq_f32(a);
}
// CHECK-LABEL: define{{.*}} float @test_vrndns_f32(float %a)
// CHECK-LABEL: define{{.*}} float @test_vrndns_f32(float noundef %a)
// CHECK-A32: [[VRNDN_I:%.*]] = call float @llvm.arm.neon.vrintn.f32(float %a)
// CHECK-A64: [[VRNDN_I:%.*]] = call float @llvm.roundeven.f32(float %a)
// CHECK: ret float [[VRNDN_I]]
@ -113,7 +113,7 @@ float32_t test_vrndns_f32(float32_t a) {
return vrndns_f32(a);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndi_f32(<2 x float> %a)
// CHECK-LABEL: define{{.*}} <2 x float> @test_vrndi_f32(<2 x float> noundef %a)
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
// CHECK: [[VRNDI1_I:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %a)
// CHECK: ret <2 x float> [[VRNDI1_I]]
@ -121,7 +121,7 @@ float32x2_t test_vrndi_f32(float32x2_t a) {
return vrndi_f32(a);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndiq_f32(<4 x float> %a)
// CHECK-LABEL: define{{.*}} <4 x float> @test_vrndiq_f32(<4 x float> noundef %a)
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
// CHECK: [[VRNDI1_I:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a)
// CHECK: ret <4 x float> [[VRNDI1_I]]

16
clang/test/CodeGen/arm-neon-dot-product.c
View File

@ -8,35 +8,35 @@
#include <arm_neon.h>
uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: ret <2 x i32> [[RESULT]]
return vdot_u32(a, b, c);
}
uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: ret <4 x i32> [[RESULT]]
return vdotq_u32(a, b, c);
}
int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.arm.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: ret <2 x i32> [[RESULT]]
return vdot_s32(a, b, c);
}
int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <16 x i8> noundef %c)
// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.arm.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: ret <4 x i32> [[RESULT]]
return vdotq_s32(a, b, c);
}
uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
@ -46,7 +46,7 @@ uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
}
uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
@ -56,7 +56,7 @@ uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
}
int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
@ -66,7 +66,7 @@ int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
}
int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> noundef %a, <16 x i8> noundef %b, <8 x i8> noundef %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>

8
clang/test/CodeGen/arm-neon-fma.c
View File

@ -9,21 +9,21 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <2 x float> @test_fma_order(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_fma_order(<2 x float> noundef %accum, <2 x float> noundef %lhs, <2 x float> noundef %rhs) #0 {
// CHECK: [[TMP6:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %rhs, <2 x float> %accum) #3
// CHECK: ret <2 x float> [[TMP6]]
float32x2_t test_fma_order(float32x2_t accum, float32x2_t lhs, float32x2_t rhs) {
return vfma_f32(accum, lhs, rhs);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_fmaq_order(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_fmaq_order(<4 x float> noundef %accum, <4 x float> noundef %lhs, <4 x float> noundef %rhs) #1 {
// CHECK: [[TMP6:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %rhs, <4 x float> %accum) #3
// CHECK: ret <4 x float> [[TMP6]]
float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) {
return vfmaq_f32(accum, lhs, rhs);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vfma_n_f32(<2 x float> noundef %a, <2 x float> noundef %b, float noundef %n) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1
// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
@ -34,7 +34,7 @@ float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
return vfma_n_f32(a, b, n);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vfmaq_n_f32(<4 x float> noundef %a, <4 x float> noundef %b, float noundef %n) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2

8
clang/test/CodeGen/arm-neon-numeric-maxmin.c
View File

@ -4,28 +4,28 @@
#include <arm_neon.h>
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmaxnm_f32(<2 x float> %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmaxnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
// CHECK: [[VMAXNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %a, <2 x float> %b) #3
// CHECK: ret <2 x float> [[VMAXNM_V2_I]]
float32x2_t test_vmaxnm_f32(float32x2_t a, float32x2_t b) {
return vmaxnm_f32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmaxnmq_f32(<4 x float> %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmaxnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #1 {
// CHECK: [[VMAXNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %a, <4 x float> %b) #3
// CHECK: ret <4 x float> [[VMAXNMQ_V2_I]]
float32x4_t test_vmaxnmq_f32(float32x4_t a, float32x4_t b) {
return vmaxnmq_f32(a, b);
}
// CHECK-LABEL: define{{.*}} <2 x float> @test_vminnm_f32(<2 x float> %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vminnm_f32(<2 x float> noundef %a, <2 x float> noundef %b) #0 {
// CHECK: [[VMINNM_V2_I:%.*]] = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %a, <2 x float> %b) #3
// CHECK: ret <2 x float> [[VMINNM_V2_I]]
float32x2_t test_vminnm_f32(float32x2_t a, float32x2_t b) {
return vminnm_f32(a, b);
}
// CHECK-LABEL: define{{.*}} <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vminnmq_f32(<4 x float> noundef %a, <4 x float> noundef %b) #1 {
// CHECK: [[VMINNMQ_V2_I:%.*]] = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %a, <4 x float> %b) #3
// CHECK: ret <4 x float> [[VMINNMQ_V2_I]]
float32x4_t test_vminnmq_f32(float32x4_t a, float32x4_t b) {

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