forked from OSchip/llvm-project
[AMDGPU] Scalar Memory instructions TD refactoring
Differential revision: https://reviews.llvm.org/D23996 llvm-svn: 280349
This commit is contained in:
Valery Pykhtin
parent
97403d15ee
commit
1b13886b5f
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@ -71,14 +71,6 @@ defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
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>;
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} // End isCommutable = 1
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//===----------------------------------------------------------------------===//
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// SMRD Instructions
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//===----------------------------------------------------------------------===//
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defm S_DCACHE_INV_VOL : SMRD_Inval <smrd<0x1d, 0x22>,
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"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
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//===----------------------------------------------------------------------===//
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// MUBUF Instructions
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//===----------------------------------------------------------------------===//
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@ -199,60 +199,6 @@ class VOP3Common <dag outs, dag ins, string asm = "",
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} // End Uses = [EXEC]
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//===----------------------------------------------------------------------===//
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// Scalar operations
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//===----------------------------------------------------------------------===//
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class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
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bits<7> sdst;
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bits<7> sbase;
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let Inst{8} = imm;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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}
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class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> {
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bits<8> offset;
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let Inst{7-0} = offset;
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}
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class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> {
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bits<8> soff;
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let Inst{7-0} = soff;
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}
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class SMRD_IMMe_ci <bits<5> op> : Enc64 {
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bits<7> sdst;
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bits<7> sbase;
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bits<32> offset;
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let Inst{7-0} = 0xff;
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let Inst{8} = 0;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let Inst{63-32} = offset;
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}
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class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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let LGKM_CNT = 1;
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let SMRD = 1;
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let mayStore = 0;
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let mayLoad = 1;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteSMEM];
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}
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//===----------------------------------------------------------------------===//
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// Vector ALU operations
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//===----------------------------------------------------------------------===//
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@ -54,14 +54,6 @@ class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
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let VI3 = vi;
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}
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// Specify an SMRD opcode for SI and SMEM opcode for VI
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// FIXME: This should really be bits<5> si, Tablegen crashes if
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// parameter default value is other parameter with different bit size
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class smrd<bits<8> si, bits<8> vi = si> {
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field bits<5> SI = si{4-0};
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field bits<8> VI = vi;
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}
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// Execpt for the NONE field, this must be kept in sync with the
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// SIEncodingFamily enum in AMDGPUInstrInfo.cpp
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@ -173,13 +165,6 @@ def mubuf_sextloadi16 : MubufLoad <sextloadi16>;
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def mubuf_load_atomic : MubufLoad <atomic_load>;
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def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
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auto Ld = cast<LoadSDNode>(N);
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return Ld->getAlignment() >= 4 &&
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Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
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static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
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}]>;
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//===----------------------------------------------------------------------===//
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// PatFrags for global memory operations
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//===----------------------------------------------------------------------===//
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@ -477,8 +462,6 @@ def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
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def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
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def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
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def smrd_offset : NamedOperandU32<"SMRDOffset", NamedMatchClass<"SMRDOffset">>;
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def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset", NamedMatchClass<"SMRDLiteralOffset">>;
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def glc : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
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def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
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@ -547,13 +530,6 @@ def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
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def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">;
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def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">;
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def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
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def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
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def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
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def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
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def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
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def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
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def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
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def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
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@ -640,159 +616,6 @@ multiclass EXP_m {
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}
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}
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//===----------------------------------------------------------------------===//
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// Scalar classes
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SMRD classes
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//===----------------------------------------------------------------------===//
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class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
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SMRD <outs, ins, "", pattern>,
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SIMCInstr<opName, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins,
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string asm> :
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SMRD <outs, ins, asm, []>,
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SMRD_IMMe <op>,
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SIMCInstr<opName, SIEncodingFamily.SI> {
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let AssemblerPredicates = [isSICI];
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let DecoderNamespace = "SICI";
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let DisableDecoder = DisableSIDecoder;
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}
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class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
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string asm> :
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SMRD <outs, ins, asm, []>,
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SMRD_SOFFe <op>,
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SIMCInstr<opName, SIEncodingFamily.SI> {
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let AssemblerPredicates = [isSICI];
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let DecoderNamespace = "SICI";
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let DisableDecoder = DisableSIDecoder;
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}
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class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins,
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string asm, list<dag> pattern = []> :
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SMRD <outs, ins, asm, pattern>,
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SMEM_IMMe_vi <op>,
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SIMCInstr<opName, SIEncodingFamily.VI> {
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let AssemblerPredicates = [isVI];
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let DecoderNamespace = "VI";
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let DisableDecoder = DisableVIDecoder;
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}
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class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
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string asm, list<dag> pattern = []> :
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SMRD <outs, ins, asm, pattern>,
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SMEM_SOFFe_vi <op>,
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SIMCInstr<opName, SIEncodingFamily.VI> {
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let AssemblerPredicates = [isVI];
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let DecoderNamespace = "VI";
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let DisableDecoder = DisableVIDecoder;
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}
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multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins,
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string asm, list<dag> pattern> {
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def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
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def _si : SMRD_IMM_Real_si <op.SI, opName, outs, ins, asm>;
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// glc is only applicable to scalar stores, which are not yet
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// implemented.
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let glc = 0 in {
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def _vi : SMRD_IMM_Real_vi <op.VI, opName, outs, ins, asm>;
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}
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}
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multiclass SMRD_SOFF_m <smrd op, string opName, dag outs, dag ins,
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string asm, list<dag> pattern> {
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def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
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def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, ins, asm>;
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// glc is only applicable to scalar stores, which are not yet
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// implemented.
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let glc = 0 in {
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def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, ins, asm>;
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}
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}
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multiclass SMRD_Special <smrd op, string opName, dag outs,
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int sdst_ = ?,
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string opStr = "",
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list<dag> pattern = []> {
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let hasSideEffects = 1 in {
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def "" : SMRD_Pseudo <opName, outs, (ins), pattern>;
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let sbase = 0, soff = 0, sdst = sdst_ in {
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def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, (ins), opName#opStr>;
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let glc = 0 in {
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def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, (ins), opName#opStr>;
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}
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}
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}
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}
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multiclass SMRD_Inval <smrd op, string opName,
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SDPatternOperator node> {
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let mayStore = 1 in {
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defm : SMRD_Special<op, opName, (outs), 0, "", [(node)]>;
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}
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}
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class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
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SMRD_SOFF_Real_vi<op, opName, (outs), (ins), opName, [(node)]> {
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let hasSideEffects = 1;
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let mayStore = 1;
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let sbase = 0;
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let sdst = 0;
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let glc = 0;
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let soff = 0;
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}
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class SMEM_Ret <bits<8> op, string opName, SDPatternOperator node> :
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SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins),
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opName#" $sdst", [(set i64:$sdst, (node))]> {
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let hasSideEffects = 1;
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let mayStore = ?;
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let mayLoad = ?;
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let sbase = 0;
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let glc = 0;
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let soff = 0;
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}
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multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
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RegisterClass dstClass> {
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defm _IMM : SMRD_IMM_m <
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op, opName#"_IMM", (outs dstClass:$sdst),
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(ins baseClass:$sbase, smrd_offset:$offset),
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opName#" $sdst, $sbase, $offset", []
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>;
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def _IMM_ci : SMRD <
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(outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
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opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
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let AssemblerPredicates = [isCIOnly];
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let DecoderNamespace = "CI";
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}
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defm _SGPR : SMRD_SOFF_m <
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op, opName#"_SGPR", (outs dstClass:$sdst),
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(ins baseClass:$sbase, SReg_32:$soff),
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opName#" $sdst, $sbase, $soff", []
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>;
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}
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//===----------------------------------------------------------------------===//
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// Vector ALU classes
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//===----------------------------------------------------------------------===//
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@ -22,6 +22,7 @@ def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
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def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
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include "SOPInstructions.td"
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include "SMInstructions.td"
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let SubtargetPredicate = isGCN in {
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@ -32,53 +33,6 @@ let SubtargetPredicate = isGCN in {
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defm EXP : EXP_m;
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//===----------------------------------------------------------------------===//
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// SMRD Instructions
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//===----------------------------------------------------------------------===//
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// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
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// SMRD instructions, because the SReg_32_XM0 register class does not include M0
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// and writing to M0 from an SMRD instruction will hang the GPU.
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defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SReg_32_XM0>;
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defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
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defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
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defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
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defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
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defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
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smrd<0x08>, "s_buffer_load_dword", SReg_128, SReg_32_XM0
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>;
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defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
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smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64
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>;
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defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
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smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128
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>;
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defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
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smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256
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>;
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defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
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smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
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>;
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let mayStore = ? in {
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// FIXME: mayStore = ? is a workaround for tablegen bug for different
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// inferred mayStore flags for the instruction pattern vs. standalone
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// Pat. Each considers the other contradictory.
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defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime",
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(outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
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>;
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}
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defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
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int_amdgcn_s_dcache_inv>;
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//===----------------------------------------------------------------------===//
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// VOPC Instructions
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//===----------------------------------------------------------------------===//
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@ -1826,64 +1780,6 @@ def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
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def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
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def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
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def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
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// SMRD Patterns
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//===----------------------------------------------------------------------===//
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multiclass SMRD_Pattern <string Instr, ValueType vt> {
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// 1. IMM offset
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def : Pat <
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(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
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(vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
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>;
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// 2. SGPR offset
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def : Pat <
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(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
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(vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
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>;
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def : Pat <
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(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
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(vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
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> {
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let Predicates = [isCIOnly];
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}
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}
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// Global and constant loads can be selected to either MUBUF or SMRD
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// instructions, but SMRD instructions are faster so we want the instruction
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// selector to prefer those.
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let AddedComplexity = 100 in {
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defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
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// 1. Offset as an immediate
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def : Pat <
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(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
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>;
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// 2. Offset loaded in an 32bit SGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
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(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
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>;
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let Predicates = [isCI] in {
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def : Pat <
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(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
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(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)
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>;
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} // End Predicates = [isCI]
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} // End let AddedComplexity = 10000
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//===----------------------------------------------------------------------===//
|
||||
// VOP1 Patterns
|
||||
|
|
@ -2983,13 +2879,6 @@ defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
|
|||
|
||||
def : BFEPattern <V_BFE_U32, S_MOV_B32>;
|
||||
|
||||
let Predicates = [isSICI] in {
|
||||
def : Pat <
|
||||
(i64 (readcyclecounter)),
|
||||
(S_MEMTIME)
|
||||
>;
|
||||
}
|
||||
|
||||
def : Pat<
|
||||
(fcanonicalize f32:$src),
|
||||
(V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,430 @@
|
|||
//===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def smrd_offset : NamedOperandU32<"SMRDOffset",
|
||||
NamedMatchClass<"SMRDOffset">> {
|
||||
let OperandType = "OPERAND_IMMEDIATE";
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Scalar Memory classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
|
||||
InstSI <outs, ins, "", pattern>,
|
||||
SIMCInstr<opName, SIEncodingFamily.NONE> {
|
||||
let isPseudo = 1;
|
||||
let isCodeGenOnly = 1;
|
||||
|
||||
let LGKM_CNT = 1;
|
||||
let SMRD = 1;
|
||||
let mayStore = 0;
|
||||
let mayLoad = 1;
|
||||
let hasSideEffects = 0;
|
||||
let UseNamedOperandTable = 1;
|
||||
let SchedRW = [WriteSMEM];
|
||||
let SubtargetPredicate = isGCN;
|
||||
|
||||
string Mnemonic = opName;
|
||||
string AsmOperands = asmOps;
|
||||
|
||||
bits<1> has_sbase = 1;
|
||||
bits<1> has_sdst = 1;
|
||||
bits<1> has_offset = 1;
|
||||
bits<1> offset_is_imm = 0;
|
||||
}
|
||||
|
||||
class SM_Real <SM_Pseudo ps>
|
||||
: InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
|
||||
|
||||
let isPseudo = 0;
|
||||
let isCodeGenOnly = 0;
|
||||
|
||||
// copy relevant pseudo op flags
|
||||
let SubtargetPredicate = ps.SubtargetPredicate;
|
||||
let AsmMatchConverter = ps.AsmMatchConverter;
|
||||
|
||||
// encoding
|
||||
bits<7> sbase;
|
||||
bits<7> sdst;
|
||||
bits<32> offset;
|
||||
bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
|
||||
}
|
||||
|
||||
class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
|
||||
: SM_Pseudo<opName, outs, ins, asmOps, pattern> {
|
||||
RegisterClass BaseClass;
|
||||
}
|
||||
|
||||
multiclass SM_Pseudo_Loads<string opName,
|
||||
RegisterClass baseClass,
|
||||
RegisterClass dstClass> {
|
||||
def _IMM : SM_Load_Pseudo <opName,
|
||||
(outs dstClass:$sdst),
|
||||
(ins baseClass:$sbase, i32imm:$offset),
|
||||
" $sdst, $sbase, $offset", []> {
|
||||
let offset_is_imm = 1;
|
||||
let BaseClass = baseClass;
|
||||
let PseudoInstr = opName # "_IMM";
|
||||
}
|
||||
def _SGPR : SM_Load_Pseudo <opName,
|
||||
(outs dstClass:$sdst),
|
||||
(ins baseClass:$sbase, SReg_32:$soff),
|
||||
" $sdst, $sbase, $offset", []> {
|
||||
let BaseClass = baseClass;
|
||||
let PseudoInstr = opName # "_SGPR";
|
||||
}
|
||||
}
|
||||
|
||||
class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
|
||||
opName, (outs SReg_64:$sdst), (ins),
|
||||
" $sdst", [(set i64:$sdst, (node))]> {
|
||||
let hasSideEffects = 1;
|
||||
// FIXME: mayStore = ? is a workaround for tablegen bug for different
|
||||
// inferred mayStore flags for the instruction pattern vs. standalone
|
||||
// Pat. Each considers the other contradictory.
|
||||
let mayStore = ?;
|
||||
let mayLoad = ?;
|
||||
let has_sbase = 0;
|
||||
let has_offset = 0;
|
||||
}
|
||||
|
||||
class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
|
||||
opName, (outs), (ins), "", [(node)]> {
|
||||
let hasSideEffects = 1;
|
||||
let mayStore = 1;
|
||||
let has_sdst = 0;
|
||||
let has_sbase = 0;
|
||||
let has_offset = 0;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Scalar Memory Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
|
||||
// SMRD instructions, because the SReg_32_XM0 register class does not include M0
|
||||
// and writing to M0 from an SMRD instruction will hang the GPU.
|
||||
defm S_LOAD_DWORD : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0>;
|
||||
defm S_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64>;
|
||||
defm S_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>;
|
||||
defm S_LOAD_DWORDX8 : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>;
|
||||
defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads <
|
||||
"s_buffer_load_dword", SReg_128, SReg_32_XM0
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads <
|
||||
"s_buffer_load_dwordx2", SReg_128, SReg_64
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <
|
||||
"s_buffer_load_dwordx4", SReg_128, SReg_128
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
|
||||
"s_buffer_load_dwordx8", SReg_128, SReg_256
|
||||
>;
|
||||
|
||||
defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
|
||||
"s_buffer_load_dwordx16", SReg_128, SReg_512
|
||||
>;
|
||||
|
||||
def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
|
||||
def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
|
||||
|
||||
let SubtargetPredicate = isCIVI in {
|
||||
def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
|
||||
} // let SubtargetPredicate = isCIVI
|
||||
|
||||
let SubtargetPredicate = isVI in {
|
||||
def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
|
||||
def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
|
||||
def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
|
||||
} // SubtargetPredicate = isVI
|
||||
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Scalar Memory Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
|
||||
auto Ld = cast<LoadSDNode>(N);
|
||||
return Ld->getAlignment() >= 4 &&
|
||||
Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
|
||||
static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
|
||||
}]>;
|
||||
|
||||
def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
|
||||
def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
|
||||
def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
|
||||
def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
|
||||
def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
|
||||
def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
|
||||
|
||||
let Predicates = [isGCN] in {
|
||||
|
||||
multiclass SMRD_Pattern <string Instr, ValueType vt> {
|
||||
|
||||
// 1. IMM offset
|
||||
def : Pat <
|
||||
(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
|
||||
(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset))
|
||||
>;
|
||||
|
||||
// 2. SGPR offset
|
||||
def : Pat <
|
||||
(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
|
||||
(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset))
|
||||
>;
|
||||
}
|
||||
|
||||
let Predicates = [isSICI] in {
|
||||
def : Pat <
|
||||
(i64 (readcyclecounter)),
|
||||
(S_MEMTIME)
|
||||
>;
|
||||
}
|
||||
|
||||
// Global and constant loads can be selected to either MUBUF or SMRD
|
||||
// instructions, but SMRD instructions are faster so we want the instruction
|
||||
// selector to prefer those.
|
||||
let AddedComplexity = 100 in {
|
||||
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
|
||||
defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
|
||||
|
||||
// 1. Offset as an immediate
|
||||
def SM_LOAD_PATTERN : Pat < // name this pattern to reuse AddedComplexity on CI
|
||||
(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
|
||||
(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
|
||||
>;
|
||||
|
||||
// 2. Offset loaded in an 32bit SGPR
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
|
||||
(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
|
||||
>;
|
||||
|
||||
} // End let AddedComplexity = 100
|
||||
|
||||
} // let Predicates = [isGCN]
|
||||
|
||||
let Predicates = [isVI] in {
|
||||
|
||||
// 1. Offset as 20bit DWORD immediate
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, IMM20bit:$offset),
|
||||
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
|
||||
>;
|
||||
|
||||
def : Pat <
|
||||
(i64 (readcyclecounter)),
|
||||
(S_MEMREALTIME)
|
||||
>;
|
||||
|
||||
} // let Predicates = [isVI]
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Targets
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SI
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
|
||||
: SM_Real<ps>
|
||||
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
|
||||
, Enc32 {
|
||||
|
||||
let AssemblerPredicates = [isSICI];
|
||||
let DecoderNamespace = "SICI";
|
||||
|
||||
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
|
||||
let Inst{8} = imm;
|
||||
let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
|
||||
let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
|
||||
let Inst{26-22} = op;
|
||||
let Inst{31-27} = 0x18; //encoding
|
||||
}
|
||||
|
||||
multiclass SM_Real_Loads_si<bits<5> op, string ps,
|
||||
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
|
||||
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
|
||||
def _IMM_si : SMRD_Real_si <op, immPs> {
|
||||
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset:$offset);
|
||||
}
|
||||
def _SGPR_si : SMRD_Real_si <op, sgprPs> {
|
||||
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset);
|
||||
}
|
||||
}
|
||||
|
||||
defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
|
||||
defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
|
||||
defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
|
||||
defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
|
||||
defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">;
|
||||
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">;
|
||||
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">;
|
||||
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">;
|
||||
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
|
||||
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
|
||||
|
||||
def S_MEMTIME_si : SMRD_Real_si <0x1e, S_MEMTIME>;
|
||||
def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VI
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
|
||||
: SM_Real<ps>
|
||||
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
|
||||
, Enc64 {
|
||||
|
||||
let AssemblerPredicates = [isVI];
|
||||
let DecoderNamespace = "VI";
|
||||
|
||||
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
|
||||
let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
|
||||
|
||||
// glc is only applicable to scalar stores, which are not yet
|
||||
// implemented.
|
||||
let Inst{16} = 0; // glc bit
|
||||
let Inst{17} = imm;
|
||||
let Inst{25-18} = op;
|
||||
let Inst{31-26} = 0x30; //encoding
|
||||
let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
|
||||
}
|
||||
|
||||
multiclass SM_Real_Loads_vi<bits<8> op, string ps,
|
||||
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
|
||||
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
|
||||
def _IMM_vi : SMEM_Real_vi <op, immPs> {
|
||||
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset:$offset);
|
||||
}
|
||||
def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
|
||||
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset);
|
||||
}
|
||||
}
|
||||
|
||||
defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
|
||||
defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
|
||||
defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
|
||||
defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">;
|
||||
defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">;
|
||||
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">;
|
||||
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">;
|
||||
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">;
|
||||
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">;
|
||||
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">;
|
||||
|
||||
def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
|
||||
def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
|
||||
def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
|
||||
def S_DCACHE_WB_VOL_vi : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>;
|
||||
def S_MEMTIME_vi : SMEM_Real_vi <0x24, S_MEMTIME>;
|
||||
def S_MEMREALTIME_vi : SMEM_Real_vi <0x25, S_MEMREALTIME>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// CI
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
|
||||
NamedMatchClass<"SMRDLiteralOffset">> {
|
||||
let OperandType = "OPERAND_IMMEDIATE";
|
||||
}
|
||||
|
||||
class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
|
||||
SM_Real<ps>,
|
||||
Enc64 {
|
||||
|
||||
let AssemblerPredicates = [isCIOnly];
|
||||
let DecoderNamespace = "CI";
|
||||
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset);
|
||||
|
||||
let LGKM_CNT = ps.LGKM_CNT;
|
||||
let SMRD = ps.SMRD;
|
||||
let mayLoad = ps.mayLoad;
|
||||
let mayStore = ps.mayStore;
|
||||
let hasSideEffects = ps.hasSideEffects;
|
||||
let SchedRW = ps.SchedRW;
|
||||
let UseNamedOperandTable = ps.UseNamedOperandTable;
|
||||
|
||||
let Inst{7-0} = 0xff;
|
||||
let Inst{8} = 0;
|
||||
let Inst{14-9} = sbase{6-1};
|
||||
let Inst{21-15} = sdst{6-0};
|
||||
let Inst{26-22} = op;
|
||||
let Inst{31-27} = 0x18; //encoding
|
||||
let Inst{63-32} = offset{31-0};
|
||||
}
|
||||
|
||||
def S_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>;
|
||||
def S_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>;
|
||||
def S_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>;
|
||||
def S_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>;
|
||||
def S_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>;
|
||||
def S_BUFFER_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>;
|
||||
def S_BUFFER_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>;
|
||||
def S_BUFFER_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>;
|
||||
def S_BUFFER_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>;
|
||||
def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>;
|
||||
|
||||
class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
|
||||
: SM_Real<ps>
|
||||
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
|
||||
, Enc32 {
|
||||
|
||||
let AssemblerPredicates = [isCIOnly];
|
||||
let DecoderNamespace = "CI";
|
||||
|
||||
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
|
||||
let Inst{8} = imm;
|
||||
let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
|
||||
let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
|
||||
let Inst{26-22} = op;
|
||||
let Inst{31-27} = 0x18; //encoding
|
||||
}
|
||||
|
||||
def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
|
||||
|
||||
let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in {
|
||||
|
||||
class SMRD_Pattern_ci <string Instr, ValueType vt> : Pat <
|
||||
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
|
||||
(vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset))> {
|
||||
let Predicates = [isCIOnly];
|
||||
}
|
||||
|
||||
def : SMRD_Pattern_ci <"S_LOAD_DWORD", i32>;
|
||||
def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>;
|
||||
def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>;
|
||||
def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>;
|
||||
def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
|
||||
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
|
||||
(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)> {
|
||||
let Predicates = [isCI]; // should this be isCIOnly?
|
||||
}
|
||||
|
||||
} // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity
|
||||
|
||||
|
|
@ -69,29 +69,6 @@ class MTBUFe_vi <bits<4> op> : Enc64 {
|
|||
let Inst{63-56} = soffset;
|
||||
}
|
||||
|
||||
class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
|
||||
bits<7> sbase;
|
||||
bits<7> sdst;
|
||||
bits<1> glc;
|
||||
|
||||
let Inst{5-0} = sbase{6-1};
|
||||
let Inst{12-6} = sdst;
|
||||
let Inst{16} = glc;
|
||||
let Inst{17} = imm;
|
||||
let Inst{25-18} = op;
|
||||
let Inst{31-26} = 0x30; //encoding
|
||||
}
|
||||
|
||||
class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> {
|
||||
bits<20> offset;
|
||||
let Inst{51-32} = offset;
|
||||
}
|
||||
|
||||
class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> {
|
||||
bits<20> soff;
|
||||
let Inst{51-32} = soff;
|
||||
}
|
||||
|
||||
class VOP3a_vi <bits<10> op> : Enc64 {
|
||||
bits<2> src0_modifiers;
|
||||
bits<9> src0;
|
||||
|
|
|
|||
|
|
@ -101,29 +101,10 @@ def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
|
|||
def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
|
||||
def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SMEM Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def S_DCACHE_WB : SMEM_Inval <0x21,
|
||||
"s_dcache_wb", int_amdgcn_s_dcache_wb>;
|
||||
|
||||
def S_DCACHE_WB_VOL : SMEM_Inval <0x23,
|
||||
"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
|
||||
|
||||
def S_MEMREALTIME : SMEM_Ret<0x25,
|
||||
"s_memrealtime", int_amdgcn_s_memrealtime>;
|
||||
|
||||
} // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI
|
||||
|
||||
let Predicates = [isVI] in {
|
||||
|
||||
// 1. Offset as 20bit DWORD immediate
|
||||
def : Pat <
|
||||
(SIload_constant v4i32:$sbase, IMM20bit:$offset),
|
||||
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
|
||||
>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// DPP Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -139,9 +120,4 @@ def : Pat <
|
|||
// Misc Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def : Pat <
|
||||
(i64 (readcyclecounter)),
|
||||
(S_MEMREALTIME)
|
||||
>;
|
||||
|
||||
} // End Predicates = [isVI]
|
||||
|
|
|
|||
Loading…
Reference in New Issue