forked from OSchip/llvm-project
[mips][sched] Temporarily rename IIAlu to IIM16Alu. NFC.
Summary: The only instructions left in IIAlu are MIPS16 specific. We're not implementing a MIPS16 scheduler at this time so rename the class to make it obvious that they are MIPS16 instructions. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12188 llvm-svn: 248267
This commit is contained in:
Daniel Sanders
parent
8216d88511
commit
1af1d275bc
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@ -530,19 +530,19 @@ class MayStore {
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// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
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// To add a constant to a 32-bit integer.
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//
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def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
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def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIM16Alu>;
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def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
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def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIM16Alu>,
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ArithLogic16Defs<0> {
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let AddedComplexity = 5;
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}
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def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
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def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIM16Alu>,
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ArithLogic16Defs<0> {
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let isCodeGenOnly = 1;
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}
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def AddiuRxRyOffMemX16:
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FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
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FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIM16Alu>;
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//
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@ -550,7 +550,7 @@ def AddiuRxRyOffMemX16:
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// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
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// To add a constant to the program counter.
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//
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def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
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def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIM16Alu>;
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//
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// Format: ADDIU sp, immediate MIPS16e
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@ -558,14 +558,14 @@ def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
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// To add a constant to the stack pointer.
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//
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def AddiuSpImm16
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: FI816_SP_ins<0b011, "addiu", IIAlu> {
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: FI816_SP_ins<0b011, "addiu", IIM16Alu> {
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let Defs = [SP];
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let Uses = [SP];
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let AddedComplexity = 5;
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}
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def AddiuSpImmX16
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: FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
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: FEXT_I816_SP_ins<0b011, "addiu", IIM16Alu> {
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let Defs = [SP];
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let Uses = [SP];
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}
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@ -576,14 +576,14 @@ def AddiuSpImmX16
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// To add 32-bit integers.
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//
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def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
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def AdduRxRyRz16: FRRR16_ins<01, "addu", IIM16Alu>, ArithLogic16Defs<1>;
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//
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// Format: AND rx, ry MIPS16e
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// Purpose: AND
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// To do a bitwise logical AND.
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def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
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def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIM16Alu>, ArithLogic16Defs<1>;
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//
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@ -591,7 +591,7 @@ def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
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// Purpose: Branch on Equal to Zero
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
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//
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@ -599,7 +599,7 @@ def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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// Purpose: Branch on Equal to Zero (Extended)
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
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//
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// Format: B offset MIPS16e
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@ -607,27 +607,27 @@ def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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// To do an unconditional PC-relative branch.
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//
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def Bimm16: FI16_ins<0b00010, "b", IIAlu>, branch16;
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def Bimm16: FI16_ins<0b00010, "b", IIM16Alu>, branch16;
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// Format: B offset MIPS16e
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// Purpose: Unconditional Branch
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// To do an unconditional PC-relative branch.
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//
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def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
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def BimmX16: FEXT_I16_ins<0b00010, "b", IIM16Alu>, branch16;
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//
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// Format: BNEZ rx, offset MIPS16e
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// Purpose: Branch on Not Equal to Zero
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
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//
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// Format: BNEZ rx, offset MIPS16e
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// Purpose: Branch on Not Equal to Zero (Extended)
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
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//
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@ -641,11 +641,11 @@ def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
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// Purpose: Branch on T Equal to Zero (Extended)
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// To test special register T then do a PC-relative conditional branch.
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//
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def Bteqz16: FI816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
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def Bteqz16: FI816_ins<0b000, "bteqz", IIM16Alu>, cbranch16 {
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let Uses = [T8];
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}
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def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
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def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIM16Alu>, cbranch16 {
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let Uses = [T8];
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}
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@ -669,11 +669,11 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
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// To test special register T then do a PC-relative conditional branch.
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//
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def Btnez16: FI816_ins<0b001, "btnez", IIAlu>, cbranch16 {
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def Btnez16: FI816_ins<0b001, "btnez", IIM16Alu>, cbranch16 {
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let Uses = [T8];
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}
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def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
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def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIM16Alu> ,cbranch16 {
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let Uses = [T8];
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}
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@ -695,7 +695,7 @@ def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
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// Purpose: Compare
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// To compare the contents of two GPRs.
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//
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def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
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def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIM16Alu> {
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let Defs = [T8];
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}
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@ -704,7 +704,7 @@ def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
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// Purpose: Compare Immediate
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// To compare a constant with the contents of a GPR.
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//
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def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
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def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIM16Alu> {
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let Defs = [T8];
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}
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@ -713,7 +713,7 @@ def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
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// Purpose: Compare Immediate (Extended)
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// To compare a constant with the contents of a GPR.
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//
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def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
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def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIM16Alu> {
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let Defs = [T8];
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}
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@ -723,7 +723,7 @@ def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
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// Purpose: Divide Word
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// To divide 32-bit signed integers.
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//
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def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
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def DivRxRy16: FRR16_div_ins<0b11010, "div", IIM16Alu> {
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let Defs = [HI0, LO0];
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}
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@ -732,7 +732,7 @@ def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
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// Purpose: Divide Unsigned Word
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// To divide 32-bit unsigned integers.
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//
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def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
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def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIM16Alu> {
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let Defs = [HI0, LO0];
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}
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//
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@ -742,13 +742,13 @@ def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
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// region and preserve the current ISA.
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//
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def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
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def Jal16 : FJAL16_ins<0b0, "jal", IIM16Alu> {
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let hasDelaySlot = 0; // not true, but we add the nop for now
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let isCall=1;
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let Defs = [RA];
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}
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def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
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def JalB16 : FJALB16_ins<0b0, "jal", IIM16Alu>, branch16 {
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let hasDelaySlot = 0; // not true, but we add the nop for now
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let isBranch=1;
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let Defs = [RA];
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@ -761,7 +761,7 @@ def JalB16 : FJALB16_ins<0b0, "jal", IIAlu>, branch16 {
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// address register.
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//
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def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
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def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIM16Alu> {
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let isBranch = 1;
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let isIndirectBranch = 1;
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let hasDelaySlot = 1;
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@ -769,14 +769,14 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
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let isBarrier=1;
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}
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def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
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def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIM16Alu> {
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let isBranch = 1;
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let isIndirectBranch = 1;
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let isTerminator=1;
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let isBarrier=1;
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}
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def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
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def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
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let isBranch = 1;
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let isIndirectBranch = 1;
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let isTerminator=1;
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@ -825,16 +825,16 @@ def LhuRxRyOffMemX16:
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// Purpose: Load Immediate
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// To load a constant into a GPR.
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//
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def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
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def LiRxImm16: FRI16_ins<0b01101, "li", IIM16Alu>;
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//
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// Format: LI rx, immediate MIPS16e
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// Purpose: Load Immediate (Extended)
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// To load a constant into a GPR.
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//
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def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
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def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIM16Alu>;
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def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
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def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIM16Alu> {
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let isCodeGenOnly = 1;
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}
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@ -863,21 +863,21 @@ def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
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// Purpose: Move
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// To move the contents of a GPR to a GPR.
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//
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def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
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def Move32R16: FI8_MOV32R16_ins<"move", IIM16Alu>;
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//
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// Format: MOVE ry, r32 MIPS16e
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//Purpose: Move
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// To move the contents of a GPR to a GPR.
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//
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def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
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def MoveR3216: FI8_MOVR3216_ins<"move", IIM16Alu>;
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//
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// Format: MFHI rx MIPS16e
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// Purpose: Move From HI Register
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// To copy the special purpose HI register to a GPR.
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//
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def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
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def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
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let Uses = [HI0];
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let hasSideEffects = 0;
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}
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@ -887,7 +887,7 @@ def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
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// Purpose: Move From LO Register
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// To copy the special purpose LO register to a GPR.
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//
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def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
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def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
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let Uses = [LO0];
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let hasSideEffects = 0;
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}
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@ -895,13 +895,13 @@ def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
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//
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// Pseudo Instruction for mult
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//
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def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
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def MultRxRy16: FMULT16_ins<"mult", IIM16Alu> {
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let isCommutable = 1;
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let hasSideEffects = 0;
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let Defs = [HI0, LO0];
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}
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def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
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def MultuRxRy16: FMULT16_ins<"multu", IIM16Alu> {
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let isCommutable = 1;
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let hasSideEffects = 0;
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let Defs = [HI0, LO0];
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@ -912,7 +912,7 @@ def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
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// Purpose: Multiply Word
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// To multiply 32-bit signed integers.
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//
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def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
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def MultRxRyRz16: FMULT16_LO_ins<"mult", IIM16Alu> {
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let isCommutable = 1;
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let hasSideEffects = 0;
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let Defs = [HI0, LO0];
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@ -923,7 +923,7 @@ def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
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// Purpose: Multiply Unsigned Word
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// To multiply 32-bit unsigned integers.
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//
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def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
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def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIM16Alu> {
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let isCommutable = 1;
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let hasSideEffects = 0;
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let Defs = [HI0, LO0];
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@ -934,21 +934,21 @@ def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
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// Purpose: Negate
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// To negate an integer value.
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//
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def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
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def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIM16Alu>;
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//
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// Format: NOT rx, ry MIPS16e
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// Purpose: Not
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// To complement an integer value
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//
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def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
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def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIM16Alu>;
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//
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// Format: OR rx, ry MIPS16e
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// Purpose: Or
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// To do a bitwise logical OR.
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//
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def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
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def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIM16Alu>, ArithLogic16Defs<1>;
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//
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// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
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@ -1012,7 +1012,7 @@ def SbRxRyOffMemX16:
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// Sign-extend least significant byte in register rx.
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//
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def SebRx16
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: FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
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: FRR_SF16_ins<0b10001, 0b100, "seb", IIM16Alu>;
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//
|
||||
// Format: SEH rx MIPS16e
|
||||
|
|
@ -1020,7 +1020,7 @@ def SebRx16
|
|||
// Sign-extend least significant word in register rx.
|
||||
//
|
||||
def SehRx16
|
||||
: FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
|
||||
: FRR_SF16_ins<0b10001, 0b101, "seh", IIM16Alu>;
|
||||
|
||||
//
|
||||
// The Sel(T) instructions are pseudos
|
||||
|
|
@ -1149,21 +1149,21 @@ def ShRxRyOffMemX16:
|
|||
// Purpose: Shift Word Left Logical (Extended)
|
||||
// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
|
||||
//
|
||||
def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
|
||||
def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIM16Alu>;
|
||||
|
||||
//
|
||||
// Format: SLLV ry, rx MIPS16e
|
||||
// Purpose: Shift Word Left Logical Variable
|
||||
// To execute a left-shift of a word by a variable number of bits.
|
||||
//
|
||||
def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
|
||||
def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIM16Alu>;
|
||||
|
||||
// Format: SLTI rx, immediate MIPS16e
|
||||
// Purpose: Set on Less Than Immediate
|
||||
// To record the result of a less-than comparison with a constant.
|
||||
//
|
||||
//
|
||||
def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
|
||||
def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIM16Alu> {
|
||||
let Defs = [T8];
|
||||
}
|
||||
|
||||
|
|
@ -1173,7 +1173,7 @@ def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
|
|||
// To record the result of a less-than comparison with a constant.
|
||||
//
|
||||
//
|
||||
def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
|
||||
def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIM16Alu> {
|
||||
let Defs = [T8];
|
||||
}
|
||||
|
||||
|
|
@ -1184,7 +1184,7 @@ def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
|
|||
// To record the result of a less-than comparison with a constant.
|
||||
//
|
||||
//
|
||||
def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
|
||||
def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIM16Alu> {
|
||||
let Defs = [T8];
|
||||
}
|
||||
|
||||
|
|
@ -1194,7 +1194,7 @@ def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
|
|||
// To record the result of a less-than comparison with a constant.
|
||||
//
|
||||
//
|
||||
def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
|
||||
def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIM16Alu> {
|
||||
let Defs = [T8];
|
||||
}
|
||||
//
|
||||
|
|
@ -1209,7 +1209,7 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
|
|||
// Purpose: Set on Less Than
|
||||
// To record the result of a less-than comparison.
|
||||
//
|
||||
def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
|
||||
def SltRxRy16: FRR16R_ins<0b00010, "slt", IIM16Alu>{
|
||||
let Defs = [T8];
|
||||
}
|
||||
|
||||
|
|
@ -1219,7 +1219,7 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
|
|||
// Purpose: Set on Less Than Unsigned
|
||||
// To record the result of an unsigned less-than comparison.
|
||||
//
|
||||
def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
|
||||
def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIM16Alu>{
|
||||
let Defs = [T8];
|
||||
}
|
||||
|
||||
|
|
@ -1236,7 +1236,7 @@ def SltuCCRxRy16: FCCRR16_ins<"sltu">;
|
|||
// To execute an arithmetic right-shift of a word by a variable
|
||||
// number of bits.
|
||||
//
|
||||
def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
|
||||
def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIM16Alu>;
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -1245,7 +1245,7 @@ def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
|
|||
// To execute an arithmetic right-shift of a word by a fixed
|
||||
// number of bits-1 to 8 bits.
|
||||
//
|
||||
def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
|
||||
def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIM16Alu>;
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -1254,7 +1254,7 @@ def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
|
|||
// To execute a logical right-shift of a word by a variable
|
||||
// number of bits.
|
||||
//
|
||||
def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
|
||||
def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIM16Alu>;
|
||||
|
||||
|
||||
//
|
||||
|
|
@ -1263,14 +1263,14 @@ def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
|
|||
// To execute a logical right-shift of a word by a fixed
|
||||
// number of bits-1 to 31 bits.
|
||||
//
|
||||
def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
|
||||
def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIM16Alu>;
|
||||
|
||||
//
|
||||
// Format: SUBU rz, rx, ry MIPS16e
|
||||
// Purpose: Subtract Unsigned Word
|
||||
// To subtract 32-bit integers
|
||||
//
|
||||
def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
|
||||
def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIM16Alu>, ArithLogic16Defs<0>;
|
||||
|
||||
//
|
||||
// Format: SW ry, offset(rx) MIPS16e
|
||||
|
|
@ -1294,7 +1294,7 @@ def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
|
|||
// Purpose: Xor
|
||||
// To do a bitwise logical XOR.
|
||||
//
|
||||
def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
|
||||
def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIM16Alu>, ArithLogic16Defs<1>;
|
||||
|
||||
class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
|
||||
let Predicates = [InMips16Mode];
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ def IMULDIV : FuncUnit;
|
|||
//===----------------------------------------------------------------------===//
|
||||
// Instruction Itinerary classes used for Mips
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IIAlu : InstrItinClass;
|
||||
// IIM16Alu is a placeholder class for most MIPS16 instructions.
|
||||
def IIM16Alu : InstrItinClass;
|
||||
def IIBranch : InstrItinClass;
|
||||
def IIPseudo : InstrItinClass;
|
||||
|
||||
|
|
@ -184,7 +185,7 @@ def II_XORI : InstrItinClass;
|
|||
// Mips Generic instruction itineraries.
|
||||
//===----------------------------------------------------------------------===//
|
||||
def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
|
||||
InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
|
||||
|
|
|
|||
Loading…
Reference in New Issue