forked from OSchip/llvm-project
Add ARM support to update_llc_test_checks.py
Just the minimal support to get it working at the moment. Includes checks for test/CodeGen/ARM/vzip.ll as an example. Differential Revision: https://reviews.llvm.org/D27829 llvm-svn: 290144
This commit is contained in:
Eli Friedman
parent
8beac28564
commit
1a9a887a29
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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@ -20,11 +21,11 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vzipi8_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
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; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
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; CHECK-NEXT: vzip.8 [[LDR0]], [[LDR1]]
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; CHECK-NEXT: vmov r0, r1, [[LDR0]]
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; CHECK-NEXT: vmov r2, r3, [[LDR1]]
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vzip.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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@ -52,11 +53,11 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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; CHECK-LABEL: vzipi16_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
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; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
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; CHECK-NEXT: vzip.16 [[LDR0]], [[LDR1]]
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; CHECK-NEXT: vmov r0, r1, [[LDR0]]
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; CHECK-NEXT: vmov r2, r3, [[LDR1]]
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vzip.16 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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@ -220,11 +221,11 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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; CHECK-LABEL: vzipi8_undef_Qres:
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; CHECK: @ BB#0:
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; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
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; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
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; CHECK-NEXT: vzip.8 [[LDR0]], [[LDR1]]
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; CHECK-NEXT: vmov r0, r1, [[LDR0]]
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; CHECK-NEXT: vmov r2, r3, [[LDR1]]
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vzip.8 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, <8 x i8>* %A
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%tmp2 = load <8 x i8>, <8 x i8>* %B
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@ -266,9 +267,15 @@ define <32 x i8> @vzipQi8_undef_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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}
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define <8 x i16> @vzip_lower_shufflemask_undef(<4 x i16>* %A, <4 x i16>* %B) {
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; CHECK-LABEL: vzip_lower_shufflemask_undef:
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; CHECK: @ BB#0: @ %entry
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; CHECK-NEXT: vldr d17, [r1]
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vzip.16 d16, d17
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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entry:
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; CHECK-LABEL: vzip_lower_shufflemask_undef
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; CHECK: vzip
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%tmp1 = load <4 x i16>, <4 x i16>* %A
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%tmp2 = load <4 x i16>, <4 x i16>* %B
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%0 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
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@ -276,30 +283,45 @@ entry:
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}
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define <4 x i32> @vzip_lower_shufflemask_zeroed(<2 x i32>* %A) {
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; CHECK-LABEL: vzip_lower_shufflemask_zeroed:
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; CHECK: @ BB#0: @ %entry
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vdup.32 q9, d16[0]
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; CHECK-NEXT: vzip.32 q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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entry:
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; CHECK-LABEL: vzip_lower_shufflemask_zeroed
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; CHECK-NOT: vtrn
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; CHECK: vzip
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 0, i32 1, i32 0>
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ret <4 x i32> %0
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}
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define <4 x i32> @vzip_lower_shufflemask_vuzp(<2 x i32>* %A) {
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; CHECK-LABEL: vzip_lower_shufflemask_vuzp:
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; CHECK: @ BB#0: @ %entry
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vdup.32 q9, d16[0]
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; CHECK-NEXT: vzip.32 q8, q9
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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entry:
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; CHECK-LABEL: vzip_lower_shufflemask_vuzp
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; CHECK-NOT: vuzp
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; CHECK: vzip
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 0>
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ret <4 x i32> %0
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}
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define void @vzip_undef_rev_shufflemask_vtrn(<2 x i32>* %A, <4 x i32>* %B) {
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; CHECK-LABEL: vzip_undef_rev_shufflemask_vtrn:
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; CHECK: @ BB#0: @ %entry
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vorr q9, q8, q8
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; CHECK-NEXT: vzip.32 q8, q9
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; CHECK-NEXT: vext.32 q8, q8, q8, #2
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; CHECK-NEXT: vst1.64 {d16, d17}, [r1]
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; CHECK-NEXT: mov pc, lr
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entry:
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; CHECK-LABEL: vzip_undef_rev_shufflemask_vtrn
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; CHECK-NOT: vtrn
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; CHECK: vzip
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 0>
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store <4 x i32> %0, <4 x i32>* %B
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@ -307,10 +329,16 @@ entry:
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}
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define void @vzip_vext_factor(<8 x i16>* %A, <4 x i16>* %B) {
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; CHECK-LABEL: vzip_vext_factor:
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; CHECK: @ BB#0: @ %entry
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; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
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; CHECK-NEXT: vext.16 d16, d16, d17, #3
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; CHECK-NEXT: vext.16 d17, d16, d16, #1
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; CHECK-NEXT: vzip.16 d16, d17
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; CHECK-NEXT: vext.16 d16, d16, d16, #1
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; CHECK-NEXT: vstr d16, [r1]
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; CHECK-NEXT: mov pc, lr
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entry:
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; CHECK-LABEL: vzip_vext_factor
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; CHECK: vext.16 d16, d16, d17, #3
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; CHECK: vzip
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%0 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 4, i32 5, i32 3>
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store <4 x i16> %0, <4 x i16>* %B
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@ -318,12 +346,14 @@ entry:
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}
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define <8 x i8> @vdup_zip(i8* nocapture readonly %x, i8* nocapture readonly %y) {
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; CHECK-LABEL: vdup_zip:
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; CHECK: @ BB#0: @ %entry
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; CHECK-NEXT: vld1.8 {d16[]}, [r1]
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; CHECK-NEXT: vld1.8 {d17[]}, [r0]
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; CHECK-NEXT: vzip.8 d17, d16
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; CHECK-NEXT: vmov r0, r1, d17
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; CHECK-NEXT: mov pc, lr
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entry:
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; CHECK-LABEL: vdup_zip:
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; CHECK: vld1.8
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; CHECK-NEXT: vld1.8
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; CHECK-NEXT: vzip.8
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; CHECK-NEXT: vmov r0, r1
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%0 = load i8, i8* %x, align 1
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%1 = insertelement <8 x i8> undef, i8 %0, i32 0
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%lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>
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@ -28,6 +28,13 @@ def llc(args, cmd_args, ir):
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SCRUB_WHITESPACE_RE = re.compile(r'(?!^(| \w))[ \t]+', flags=re.M)
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SCRUB_TRAILING_WHITESPACE_RE = re.compile(r'[ \t]+$', flags=re.M)
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SCRUB_KILL_COMMENT_RE = re.compile(r'^ *#+ +kill:.*\n')
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ASM_FUNCTION_X86_RE = re.compile(
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r'^_?(?P<func>[^:]+):[ \t]*#+[ \t]*@(?P=func)\n[^:]*?'
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r'(?P<body>^##?[ \t]+[^:]+:.*?)\s*'
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r'^\s*(?:[^:\n]+?:\s*\n\s*\.size|\.cfi_endproc|\.globl|\.comm|\.(?:sub)?section)',
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flags=(re.M | re.S))
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SCRUB_X86_SHUFFLES_RE = (
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re.compile(
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r'^(\s*\w+) [^#\n]+#+ ((?:[xyz]mm\d+|mem)( \{%k\d+\}( \{z\})?)? = .*)$',
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@ -35,20 +42,21 @@ SCRUB_X86_SHUFFLES_RE = (
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SCRUB_X86_SP_RE = re.compile(r'\d+\(%(esp|rsp)\)')
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SCRUB_X86_RIP_RE = re.compile(r'[.\w]+\(%rip\)')
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SCRUB_X86_LCP_RE = re.compile(r'\.LCPI[0-9]+_[0-9]+')
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SCRUB_KILL_COMMENT_RE = re.compile(r'^ *#+ +kill:.*\n')
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ASM_FUNCTION_ARM_RE = re.compile(
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r'^(?P<func>[0-9a-zA-Z_]+):\n' # f: (name of function)
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r'\s+\.fnstart\n' # .fnstart
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r'(?P<body>.*?)\n' # (body of the function)
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r'.Lfunc_end[0-9]+:\n', # .Lfunc_end0:
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flags=(re.M | re.S))
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RUN_LINE_RE = re.compile('^\s*;\s*RUN:\s*(.*)$')
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IR_FUNCTION_RE = re.compile('^\s*define\s+(?:internal\s+)?[^@]*@(\w+)\s*\(')
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ASM_FUNCTION_RE = re.compile(
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r'^_?(?P<func>[^:]+):[ \t]*#+[ \t]*@(?P=func)\n[^:]*?'
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r'(?P<body>^##?[ \t]+[^:]+:.*?)\s*'
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r'^\s*(?:[^:\n]+?:\s*\n\s*\.size|\.cfi_endproc|\.globl|\.comm|\.(?:sub)?section)',
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flags=(re.M | re.S))
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CHECK_PREFIX_RE = re.compile('--check-prefix=(\S+)')
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CHECK_RE = re.compile(r'^\s*;\s*([^:]+?)(?:-NEXT|-NOT|-DAG|-LABEL)?:')
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def scrub_asm(asm):
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def scrub_asm_x86(asm):
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# Scrub runs of whitespace out of the assembly, but leave the leading
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# whitespace in place.
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asm = SCRUB_WHITESPACE_RE.sub(r' ', asm)
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@ -68,14 +76,31 @@ def scrub_asm(asm):
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asm = SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
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return asm
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def scrub_asm_arm(asm):
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# Scrub runs of whitespace out of the assembly, but leave the leading
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# whitespace in place.
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asm = SCRUB_WHITESPACE_RE.sub(r' ', asm)
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# Expand the tabs used for indentation.
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asm = string.expandtabs(asm, 2)
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# Strip kill operands inserted into the asm.
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asm = SCRUB_KILL_COMMENT_RE.sub('', asm)
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# Strip trailing whitespace.
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asm = SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
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return asm
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# Build up a dictionary of all the function bodies.
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def build_function_body_dictionary(raw_tool_output, prefixes, func_dict, verbose):
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for m in ASM_FUNCTION_RE.finditer(raw_tool_output):
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is_arm = re.compile(r'\n\s+\.syntax unified\n').search(raw_tool_output)
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function_re = ASM_FUNCTION_ARM_RE if is_arm else ASM_FUNCTION_X86_RE
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for m in function_re.finditer(raw_tool_output):
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if not m:
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continue
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func = m.group('func')
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scrubbed_body = scrub_asm(m.group('body'))
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if is_arm:
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scrubbed_body = scrub_asm_arm(m.group('body'))
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else:
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scrubbed_body = scrub_asm_x86(m.group('body'))
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if func.startswith('stress'):
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# We only use the last line of the function body for stress tests.
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scrubbed_body = '\n'.join(scrubbed_body.splitlines()[-1:])
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