forked from OSchip/llvm-project
parent
c25eb5d051
commit
1a86e8461a
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@ -9445,7 +9445,7 @@ X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
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MachineBasicBlock *
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X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
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assert((Subtarget->hasSSE3()) && "Target must have SSE3 features enabled");
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assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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@ -9455,7 +9455,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
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unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
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MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
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for (int i = 0; i < X86::AddrNumOperands; ++i)
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(*MIB).addOperand(MI->getOperand(i));
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MIB.addOperand(MI->getOperand(i));
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unsigned ValOps = X86::AddrNumOperands;
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BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
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@ -9472,7 +9472,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
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MachineBasicBlock *
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X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
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assert((Subtarget->hasSSE3()) && "Target must have SSE3 features enabled");
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assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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@ -824,8 +824,8 @@ namespace llvm {
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/// Utility functions to emit monitor and mwait instructions. These
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/// need to make sure that the arguments to the intrinsic are in the
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/// correct registers.
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MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB)
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const;
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MachineBasicBlock *EmitMonitor(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
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/// Utility function to emit atomic bitwise operations (and, or, xor).
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