Fix some cleanups from my last patch.

llvm-svn: 120410
This commit is contained in:
Eric Christopher 2010-11-30 08:10:28 +00:00
parent c25eb5d051
commit 1a86e8461a
2 changed files with 5 additions and 5 deletions

View File

@ -9445,7 +9445,7 @@ X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
MachineBasicBlock *
X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
assert((Subtarget->hasSSE3()) && "Target must have SSE3 features enabled");
assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
@ -9455,7 +9455,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
for (int i = 0; i < X86::AddrNumOperands; ++i)
(*MIB).addOperand(MI->getOperand(i));
MIB.addOperand(MI->getOperand(i));
unsigned ValOps = X86::AddrNumOperands;
BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
@ -9472,7 +9472,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
MachineBasicBlock *
X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
assert((Subtarget->hasSSE3()) && "Target must have SSE3 features enabled");
assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();

View File

@ -824,8 +824,8 @@ namespace llvm {
/// Utility functions to emit monitor and mwait instructions. These
/// need to make sure that the arguments to the intrinsic are in the
/// correct registers.
MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB)
const;
MachineBasicBlock *EmitMonitor(MachineInstr *MI,
MachineBasicBlock *BB) const;
MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
/// Utility function to emit atomic bitwise operations (and, or, xor).