maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Fix misc uses of "long" variables to use "int64_t". 

I don't have any evidence these particular uses are actually causing any
issues, but we should avoid accidentally truncating immediate values
depending on the host.
This commit is contained in:
Eli Friedman 2022-07-27 09:37:13 -07:00
parent 32622d6de4
commit 1a6d82b93f
5 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -3865,7 +3865,7 @@ bool AMDGPUAsmParser::validateMIMGDim(const MCInst &Inst) {
if (DimIdx < 0) if (DimIdx < 0)
return true; return true;
long Imm = Inst.getOperand(DimIdx).getImm(); int64_t Imm = Inst.getOperand(DimIdx).getImm();
if (Imm < 0 || Imm >= 8) if (Imm < 0 || Imm >= 8)
return false; return false;

2
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -177,7 +177,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
LowerCompactBranch(TmpInst); LowerCompactBranch(TmpInst);
} }
unsigned long N = Fixups.size(); size_t N = Fixups.size();
uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
// Check for unimplemented opcodes. // Check for unimplemented opcodes.

7
llvm/lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -74,7 +74,7 @@ struct Address {
int FI; int FI;
} Base; } Base;
long Offset; int64_t Offset;
// Innocuous defaults for our address. // Innocuous defaults for our address.
Address() Address()
@ -338,7 +338,7 @@ bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
break; break;
case Instruction::GetElementPtr: { case Instruction::GetElementPtr: {
Address SavedAddr = Addr; Address SavedAddr = Addr;
long TmpOffset = Addr.Offset; int64_t TmpOffset = Addr.Offset;
// Iterate through the GEP folding the constants into offsets where // Iterate through the GEP folding the constants into offsets where
// we can. // we can.
@ -437,8 +437,7 @@ void PPCFastISel::PPCSimplifyAddress(Address &Addr, bool &UseOffset,
if (!UseOffset) { if (!UseOffset) {
IntegerType *OffsetTy = Type::getInt64Ty(*Context); IntegerType *OffsetTy = Type::getInt64Ty(*Context);
const ConstantInt *Offset = const ConstantInt *Offset = ConstantInt::getSigned(OffsetTy, Addr.Offset);
ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
IndexReg = PPCMaterializeInt(Offset, MVT::i64); IndexReg = PPCMaterializeInt(Offset, MVT::i64);
assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
} }

2
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -15415,7 +15415,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineMemOperand *BaseMMO = MachineMemOperand *BaseMMO =
MF.getMachineMemOperand(LD->getMemOperand(), MF.getMachineMemOperand(LD->getMemOperand(),
-(long)MemVT.getStoreSize()+1, -(int64_t)MemVT.getStoreSize()+1,
2*MemVT.getStoreSize()-1); 2*MemVT.getStoreSize()-1);
// Create the new base load. // Create the new base load.

2
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -478,7 +478,7 @@ def HI16 : SDNodeXForm<imm, [{
def HA16 : SDNodeXForm<imm, [{ def HA16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
long Val = N->getZExtValue(); int64_t Val = N->getZExtValue();
return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
}]>; }]>;
def MB : SDNodeXForm<imm, [{ def MB : SDNodeXForm<imm, [{