forked from OSchip/llvm-project
[RISCV] Use Triple::isRISCV/isRISCV32/isRISCV64 helps in some places. NFC
Reviewed By: reames Differential Revision: https://reviews.llvm.org/D132197
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a47ec1b797
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@ -968,14 +968,9 @@ void CodeGenModule::EmitOpenCLMetadata() {
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void CodeGenModule::EmitBackendOptionsMetadata(
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const CodeGenOptions CodeGenOpts) {
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switch (getTriple().getArch()) {
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default:
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break;
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case llvm::Triple::riscv32:
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case llvm::Triple::riscv64:
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if (getTriple().isRISCV()) {
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getModule().addModuleFlag(llvm::Module::Error, "SmallDataLimit",
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CodeGenOpts.SmallDataLimit);
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break;
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}
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}
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@ -52,7 +52,7 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const llvm::Triple &Triple,
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const llvm::opt::ArgList &Args,
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const llvm::opt::Arg *A, StringRef Mcpu,
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std::vector<StringRef> &Features) {
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bool Is64Bit = (Triple.getArch() == llvm::Triple::riscv64);
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bool Is64Bit = Triple.isRISCV64();
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llvm::RISCV::CPUKind CPUKind = llvm::RISCV::parseCPUKind(Mcpu);
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if (!llvm::RISCV::checkCPUKind(CPUKind, Is64Bit) ||
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!llvm::RISCV::getCPUFeaturesExceptStdExt(CPUKind, Features)) {
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@ -163,9 +163,7 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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}
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StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
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assert((Triple.getArch() == llvm::Triple::riscv32 ||
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Triple.getArch() == llvm::Triple::riscv64) &&
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"Unexpected triple");
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assert(Triple.isRISCV() && "Unexpected triple");
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// GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
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// configured using `--with-abi=`, then the logic for the default choice is
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@ -213,7 +211,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
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// We deviate from GCC's defaults here:
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// - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
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// - On all other OSs we use the double floating point calling convention.
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if (Triple.getArch() == llvm::Triple::riscv32) {
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if (Triple.isRISCV32()) {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "ilp32";
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else
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@ -228,9 +226,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
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StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
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const llvm::Triple &Triple) {
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assert((Triple.getArch() == llvm::Triple::riscv32 ||
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Triple.getArch() == llvm::Triple::riscv64) &&
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"Unexpected triple");
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assert(Triple.isRISCV() && "Unexpected triple");
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// GCC's logic around choosing a default `-march=` is complex. If GCC is not
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// configured using `--with-arch=`, then the logic for the default choice is
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@ -291,7 +287,7 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
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// We deviate from GCC's defaults here:
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// - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
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// - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
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if (Triple.getArch() == llvm::Triple::riscv32) {
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if (Triple.isRISCV32()) {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "rv32imac";
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else
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@ -39,7 +39,7 @@ static bool findRISCVMultilibs(const Driver &D,
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StringRef Arch = riscv::getRISCVArch(Args, TargetTriple);
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StringRef Abi = tools::riscv::getRISCVABI(Args, TargetTriple);
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if (TargetTriple.getArch() == llvm::Triple::riscv64) {
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if (TargetTriple.isRISCV64()) {
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Multilib Imac = makeMultilib("").flag("+march=rv64imac").flag("+mabi=lp64");
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Multilib Imafdc = makeMultilib("/rv64imafdc/lp64d")
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.flag("+march=rv64imafdc")
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@ -57,7 +57,7 @@ static bool findRISCVMultilibs(const Driver &D,
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Result.Multilibs = MultilibSet().Either(Imac, Imafdc);
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return Result.Multilibs.select(Flags, Result.SelectedMultilib);
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}
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if (TargetTriple.getArch() == llvm::Triple::riscv32) {
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if (TargetTriple.isRISCV32()) {
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Multilib Imac =
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makeMultilib("").flag("+march=rv32imac").flag("+mabi=ilp32");
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Multilib I =
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@ -140,8 +140,7 @@ static bool isAArch64BareMetal(const llvm::Triple &Triple) {
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}
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static bool isRISCVBareMetal(const llvm::Triple &Triple) {
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if (Triple.getArch() != llvm::Triple::riscv32 &&
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Triple.getArch() != llvm::Triple::riscv64)
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if (!Triple.isRISCV())
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return false;
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if (Triple.getVendor() != llvm::Triple::UnknownVendor)
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