maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[PowerPC] Add missing handling for half precision 

The fix for PR39865 took care of some of the handling for half precision
but it missed a number of issues that still exist. This patch fixes the
remaining issues that cause crashes in the PPC back end.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45776

Differential revision: https://reviews.llvm.org/D79283
This commit is contained in:
Nemanja Ivanovic 2020-05-22 07:48:09 -05:00
parent eddcce0814
commit 1a493b0fa5
6 changed files with 1151 additions and 179 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -10755,6 +10755,7 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::FP_EXTEND && assert(Op.getOpcode() == ISD::FP_EXTEND &&
"Should only be called for ISD::FP_EXTEND"); "Should only be called for ISD::FP_EXTEND");
// FIXME: handle extends from half precision float vectors on P9.
// We only want to custom lower an extend from v2f32 to v2f64. // We only want to custom lower an extend from v2f32 to v2f64.
if (Op.getValueType() != MVT::v2f64 || if (Op.getValueType() != MVT::v2f64 ||
Op.getOperand(0).getValueType() != MVT::v2f32) Op.getOperand(0).getValueType() != MVT::v2f32)
@ -10968,6 +10969,11 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::BITCAST: case ISD::BITCAST:
// Don't handle bitcast here. // Don't handle bitcast here.
return; return;
case ISD::FP_EXTEND:
SDValue Lowered = LowerFP_EXTEND(SDValue(N, 0), DAG);
if (Lowered)
Results.push_back(Lowered);
return;
} }
} }

2
llvm/lib/Target/PowerPC/PPCISelLowering.h
View File

@ -640,7 +640,7 @@ namespace llvm {
/// then the VPERM for the shuffle. All in all a very slow sequence. /// then the VPERM for the shuffle. All in all a very slow sequence.
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
const override { const override {
if (VT.getScalarSizeInBits() % 8 == 0) if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0)
return TypeWidenVector; return TypeWidenVector;
return TargetLoweringBase::getPreferredVectorAction(VT); return TargetLoweringBase::getPreferredVectorAction(VT);
} }

7
llvm/lib/Target/PowerPC/PPCInstrVSX.td
View File

@ -3658,6 +3658,13 @@ def : Pat<(f32 (extloadf16 xoaddr:$src)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX xoaddr:$src)), VSSRC))>; (f32 (COPY_TO_REGCLASS (XSCVHPDP (LXSIHZX xoaddr:$src)), VSSRC))>;
def : Pat<(truncstoref16 f32:$src, xoaddr:$dst), def : Pat<(truncstoref16 f32:$src, xoaddr:$dst),
(STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), xoaddr:$dst)>; (STXSIHX (XSCVDPHP (COPY_TO_REGCLASS $src, VSFRC)), xoaddr:$dst)>;
def : Pat<(f64 (f16_to_fp i32:$A)),
(f64 (XSCVHPDP (MTVSRWZ $A)))>;
def : Pat<(f32 (f16_to_fp i32:$A)),
(f32 (COPY_TO_REGCLASS (XSCVHPDP (MTVSRWZ $A)), VSSRC))>;
def : Pat<(i32 (fp_to_f16 f32:$A)),
(i32 (MFVSRWZ (XSCVDPHP (COPY_TO_REGCLASS $A, VSFRC))))>;
def : Pat<(i32 (fp_to_f16 f64:$A)), (i32 (MFVSRWZ (XSCVDPHP $A)))>;
// Vector sign extensions // Vector sign extensions
def : Pat<(f64 (PPCVexts f64:$A, 1)), def : Pat<(f64 (PPCVexts f64:$A, 1)),

1081
llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
View File

File diff suppressed because it is too large Load Diff

88
llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
View File

@ -11,46 +11,34 @@
define void @test_liwzx1(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) { define void @test_liwzx1(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
; P9LE-LABEL: test_liwzx1: ; P9LE-LABEL: test_liwzx1:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: lfiwzx f0, 0, r3 ; P9LE-NEXT: lfs f0, 0(r3)
; P9LE-NEXT: lfiwzx f1, 0, r4 ; P9LE-NEXT: lfs f1, 0(r4)
; P9LE-NEXT: xxswapd vs0, f0 ; P9LE-NEXT: xsaddsp f0, f0, f1
; P9LE-NEXT: xxswapd vs1, f1 ; P9LE-NEXT: stfs f0, 0(r5)
; P9LE-NEXT: xvaddsp vs0, vs0, vs1
; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 2
; P9LE-NEXT: stfiwx f0, 0, r5
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: test_liwzx1: ; P9BE-LABEL: test_liwzx1:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lfiwzx f0, 0, r3 ; P9BE-NEXT: lfs f0, 0(r3)
; P9BE-NEXT: lfiwzx f1, 0, r4 ; P9BE-NEXT: lfs f1, 0(r4)
; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 ; P9BE-NEXT: xsaddsp f0, f0, f1
; P9BE-NEXT: xxsldwi vs1, f1, f1, 1 ; P9BE-NEXT: stfs f0, 0(r5)
; P9BE-NEXT: xvaddsp vs0, vs0, vs1
; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P9BE-NEXT: stfiwx f0, 0, r5
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: test_liwzx1: ; P8LE-LABEL: test_liwzx1:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: lfiwzx f0, 0, r3 ; P8LE-NEXT: lfsx f0, 0, r3
; P8LE-NEXT: lfiwzx f1, 0, r4 ; P8LE-NEXT: lfsx f1, 0, r4
; P8LE-NEXT: xxswapd vs0, f0 ; P8LE-NEXT: xsaddsp f0, f0, f1
; P8LE-NEXT: xxswapd vs1, f1 ; P8LE-NEXT: stfsx f0, 0, r5
; P8LE-NEXT: xvaddsp vs0, vs0, vs1
; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 2
; P8LE-NEXT: stfiwx f0, 0, r5
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: test_liwzx1: ; P8BE-LABEL: test_liwzx1:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: lfiwzx f0, 0, r3 ; P8BE-NEXT: lfsx f0, 0, r3
; P8BE-NEXT: lfiwzx f1, 0, r4 ; P8BE-NEXT: lfsx f1, 0, r4
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 ; P8BE-NEXT: xsaddsp f0, f0, f1
; P8BE-NEXT: xxsldwi vs1, f1, f1, 1 ; P8BE-NEXT: stfsx f0, 0, r5
; P8BE-NEXT: xvaddsp vs0, vs0, vs1
; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P8BE-NEXT: stfiwx f0, 0, r5
; P8BE-NEXT: blr ; P8BE-NEXT: blr
@ -65,50 +53,38 @@ define void @test_liwzx1(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) { define <1 x float>* @test_liwzx2(<1 x float>* %A, <1 x float>* %B, <1 x float>* %C) {
; P9LE-LABEL: test_liwzx2: ; P9LE-LABEL: test_liwzx2:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: lfiwzx f0, 0, r3 ; P9LE-NEXT: lfs f0, 0(r3)
; P9LE-NEXT: lfiwzx f1, 0, r4
; P9LE-NEXT: xxswapd vs0, f0
; P9LE-NEXT: xxswapd vs1, f1
; P9LE-NEXT: xvsubsp vs0, vs0, vs1
; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 2
; P9LE-NEXT: mr r3, r5 ; P9LE-NEXT: mr r3, r5
; P9LE-NEXT: stfiwx f0, 0, r5 ; P9LE-NEXT: lfs f1, 0(r4)
; P9LE-NEXT: xssubsp f0, f0, f1
; P9LE-NEXT: stfs f0, 0(r5)
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: test_liwzx2: ; P9BE-LABEL: test_liwzx2:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lfiwzx f0, 0, r3 ; P9BE-NEXT: lfs f0, 0(r3)
; P9BE-NEXT: lfiwzx f1, 0, r4
; P9BE-NEXT: xxsldwi vs0, f0, f0, 1
; P9BE-NEXT: xxsldwi vs1, f1, f1, 1
; P9BE-NEXT: xvsubsp vs0, vs0, vs1
; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P9BE-NEXT: mr r3, r5 ; P9BE-NEXT: mr r3, r5
; P9BE-NEXT: stfiwx f0, 0, r5 ; P9BE-NEXT: lfs f1, 0(r4)
; P9BE-NEXT: xssubsp f0, f0, f1
; P9BE-NEXT: stfs f0, 0(r5)
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: test_liwzx2: ; P8LE-LABEL: test_liwzx2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: lfiwzx f0, 0, r3 ; P8LE-NEXT: lfsx f0, 0, r3
; P8LE-NEXT: lfiwzx f1, 0, r4 ; P8LE-NEXT: lfsx f1, 0, r4
; P8LE-NEXT: mr r3, r5 ; P8LE-NEXT: mr r3, r5
; P8LE-NEXT: xxswapd vs0, f0 ; P8LE-NEXT: xssubsp f0, f0, f1
; P8LE-NEXT: xxswapd vs1, f1 ; P8LE-NEXT: stfsx f0, 0, r5
; P8LE-NEXT: xvsubsp vs0, vs0, vs1
; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 2
; P8LE-NEXT: stfiwx f0, 0, r5
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: test_liwzx2: ; P8BE-LABEL: test_liwzx2:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: lfiwzx f0, 0, r3 ; P8BE-NEXT: lfsx f0, 0, r3
; P8BE-NEXT: lfiwzx f1, 0, r4 ; P8BE-NEXT: lfsx f1, 0, r4
; P8BE-NEXT: mr r3, r5 ; P8BE-NEXT: mr r3, r5
; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 ; P8BE-NEXT: xssubsp f0, f0, f1
; P8BE-NEXT: xxsldwi vs1, f1, f1, 1 ; P8BE-NEXT: stfsx f0, 0, r5
; P8BE-NEXT: xvsubsp vs0, vs0, vs1
; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 3
; P8BE-NEXT: stfiwx f0, 0, r5
; P8BE-NEXT: blr ; P8BE-NEXT: blr

146
llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
View File

@ -9,9 +9,7 @@ define <1 x float> @constrained_vector_fdiv_v1f32() #0 {
; PC64LE-NEXT: addis 4, 2, .LCPI0_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI0_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI0_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI0_0@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI0_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI0_1@toc@l(4)
; PC64LE-NEXT: xsdivsp 0, 1, 0 ; PC64LE-NEXT: xsdivsp 1, 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fdiv_v1f32: ; PC64LE9-LABEL: constrained_vector_fdiv_v1f32:
@ -20,9 +18,7 @@ define <1 x float> @constrained_vector_fdiv_v1f32() #0 {
; PC64LE9-NEXT: lfs 0, .LCPI0_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI0_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI0_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI0_1@toc@l(3)
; PC64LE9-NEXT: xsdivsp 0, 1, 0 ; PC64LE9-NEXT: xsdivsp 1, 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%div = call <1 x float> @llvm.experimental.constrained.fdiv.v1f32( %div = call <1 x float> @llvm.experimental.constrained.fdiv.v1f32(
@ -232,8 +228,6 @@ define <1 x float> @constrained_vector_frem_v1f32() #0 {
; PC64LE-NEXT: lfs 2, .LCPI5_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI5_1@toc@l(4)
; PC64LE-NEXT: bl fmodf ; PC64LE-NEXT: bl fmodf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -250,8 +244,6 @@ define <1 x float> @constrained_vector_frem_v1f32() #0 {
; PC64LE9-NEXT: lfs 2, .LCPI5_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI5_1@toc@l(3)
; PC64LE9-NEXT: bl fmodf ; PC64LE9-NEXT: bl fmodf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -645,9 +637,7 @@ define <1 x float> @constrained_vector_fmul_v1f32() #0 {
; PC64LE-NEXT: addis 4, 2, .LCPI10_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI10_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI10_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI10_0@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI10_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI10_1@toc@l(4)
; PC64LE-NEXT: xsmulsp 0, 1, 0 ; PC64LE-NEXT: xsmulsp 1, 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fmul_v1f32: ; PC64LE9-LABEL: constrained_vector_fmul_v1f32:
@ -656,9 +646,7 @@ define <1 x float> @constrained_vector_fmul_v1f32() #0 {
; PC64LE9-NEXT: lfs 0, .LCPI10_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI10_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI10_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI10_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI10_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI10_1@toc@l(3)
; PC64LE9-NEXT: xsmulsp 0, 1, 0 ; PC64LE9-NEXT: xsmulsp 1, 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%mul = call <1 x float> @llvm.experimental.constrained.fmul.v1f32( %mul = call <1 x float> @llvm.experimental.constrained.fmul.v1f32(
@ -865,9 +853,7 @@ define <1 x float> @constrained_vector_fadd_v1f32() #0 {
; PC64LE-NEXT: addis 4, 2, .LCPI15_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI15_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI15_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI15_0@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI15_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI15_1@toc@l(4)
; PC64LE-NEXT: xsaddsp 0, 1, 0 ; PC64LE-NEXT: xsaddsp 1, 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fadd_v1f32: ; PC64LE9-LABEL: constrained_vector_fadd_v1f32:
@ -876,9 +862,7 @@ define <1 x float> @constrained_vector_fadd_v1f32() #0 {
; PC64LE9-NEXT: lfs 0, .LCPI15_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI15_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI15_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI15_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI15_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI15_1@toc@l(3)
; PC64LE9-NEXT: xsaddsp 0, 1, 0 ; PC64LE9-NEXT: xsaddsp 1, 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%add = call <1 x float> @llvm.experimental.constrained.fadd.v1f32( %add = call <1 x float> @llvm.experimental.constrained.fadd.v1f32(
@ -1081,9 +1065,7 @@ define <1 x float> @constrained_vector_fsub_v1f32() #0 {
; PC64LE-NEXT: addis 4, 2, .LCPI20_1@toc@ha ; PC64LE-NEXT: addis 4, 2, .LCPI20_1@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI20_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI20_0@toc@l(3)
; PC64LE-NEXT: lfs 1, .LCPI20_1@toc@l(4) ; PC64LE-NEXT: lfs 1, .LCPI20_1@toc@l(4)
; PC64LE-NEXT: xssubsp 0, 1, 0 ; PC64LE-NEXT: xssubsp 1, 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fsub_v1f32: ; PC64LE9-LABEL: constrained_vector_fsub_v1f32:
@ -1092,9 +1074,7 @@ define <1 x float> @constrained_vector_fsub_v1f32() #0 {
; PC64LE9-NEXT: lfs 0, .LCPI20_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI20_0@toc@l(3)
; PC64LE9-NEXT: addis 3, 2, .LCPI20_1@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI20_1@toc@ha
; PC64LE9-NEXT: lfs 1, .LCPI20_1@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI20_1@toc@l(3)
; PC64LE9-NEXT: xssubsp 0, 1, 0 ; PC64LE9-NEXT: xssubsp 1, 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32( %sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
@ -1295,18 +1275,14 @@ define <1 x float> @constrained_vector_sqrt_v1f32() #0 {
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI25_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI25_0@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI25_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI25_0@toc@l(3)
; PC64LE-NEXT: xssqrtsp 0, 0 ; PC64LE-NEXT: xssqrtsp 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sqrt_v1f32: ; PC64LE9-LABEL: constrained_vector_sqrt_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI25_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI25_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI25_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI25_0@toc@l(3)
; PC64LE9-NEXT: xssqrtsp 0, 0 ; PC64LE9-NEXT: xssqrtsp 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sqrt = call <1 x float> @llvm.experimental.constrained.sqrt.v1f32( %sqrt = call <1 x float> @llvm.experimental.constrained.sqrt.v1f32(
@ -1481,8 +1457,6 @@ define <1 x float> @constrained_vector_pow_v1f32() #0 {
; PC64LE-NEXT: lfs 2, .LCPI30_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI30_1@toc@l(4)
; PC64LE-NEXT: bl powf ; PC64LE-NEXT: bl powf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -1499,8 +1473,6 @@ define <1 x float> @constrained_vector_pow_v1f32() #0 {
; PC64LE9-NEXT: lfs 2, .LCPI30_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI30_1@toc@l(3)
; PC64LE9-NEXT: bl powf ; PC64LE9-NEXT: bl powf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -1899,8 +1871,6 @@ define <1 x float> @constrained_vector_powi_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI35_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI35_0@toc@l(3)
; PC64LE-NEXT: bl __powisf2 ; PC64LE-NEXT: bl __powisf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -1916,8 +1886,6 @@ define <1 x float> @constrained_vector_powi_v1f32() #0 {
; PC64LE9-NEXT: li 4, 3 ; PC64LE9-NEXT: li 4, 3
; PC64LE9-NEXT: bl __powisf2 ; PC64LE9-NEXT: bl __powisf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -2284,8 +2252,6 @@ define <1 x float> @constrained_vector_sin_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI40_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI40_0@toc@l(3)
; PC64LE-NEXT: bl sinf ; PC64LE-NEXT: bl sinf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -2300,8 +2266,6 @@ define <1 x float> @constrained_vector_sin_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI40_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI40_0@toc@l(3)
; PC64LE9-NEXT: bl sinf ; PC64LE9-NEXT: bl sinf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -2637,8 +2601,6 @@ define <1 x float> @constrained_vector_cos_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI45_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI45_0@toc@l(3)
; PC64LE-NEXT: bl cosf ; PC64LE-NEXT: bl cosf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -2653,8 +2615,6 @@ define <1 x float> @constrained_vector_cos_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI45_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI45_0@toc@l(3)
; PC64LE9-NEXT: bl cosf ; PC64LE9-NEXT: bl cosf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -2990,8 +2950,6 @@ define <1 x float> @constrained_vector_exp_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI50_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI50_0@toc@l(3)
; PC64LE-NEXT: bl expf ; PC64LE-NEXT: bl expf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -3006,8 +2964,6 @@ define <1 x float> @constrained_vector_exp_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI50_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI50_0@toc@l(3)
; PC64LE9-NEXT: bl expf ; PC64LE9-NEXT: bl expf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -3343,8 +3299,6 @@ define <1 x float> @constrained_vector_exp2_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI55_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI55_0@toc@l(3)
; PC64LE-NEXT: bl exp2f ; PC64LE-NEXT: bl exp2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -3359,8 +3313,6 @@ define <1 x float> @constrained_vector_exp2_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI55_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI55_0@toc@l(3)
; PC64LE9-NEXT: bl exp2f ; PC64LE9-NEXT: bl exp2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -3696,8 +3648,6 @@ define <1 x float> @constrained_vector_log_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI60_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI60_0@toc@l(3)
; PC64LE-NEXT: bl logf ; PC64LE-NEXT: bl logf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -3712,8 +3662,6 @@ define <1 x float> @constrained_vector_log_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI60_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI60_0@toc@l(3)
; PC64LE9-NEXT: bl logf ; PC64LE9-NEXT: bl logf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -4049,8 +3997,6 @@ define <1 x float> @constrained_vector_log10_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI65_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI65_0@toc@l(3)
; PC64LE-NEXT: bl log10f ; PC64LE-NEXT: bl log10f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -4065,8 +4011,6 @@ define <1 x float> @constrained_vector_log10_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI65_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI65_0@toc@l(3)
; PC64LE9-NEXT: bl log10f ; PC64LE9-NEXT: bl log10f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -4402,8 +4346,6 @@ define <1 x float> @constrained_vector_log2_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI70_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI70_0@toc@l(3)
; PC64LE-NEXT: bl log2f ; PC64LE-NEXT: bl log2f
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -4418,8 +4360,6 @@ define <1 x float> @constrained_vector_log2_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI70_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI70_0@toc@l(3)
; PC64LE9-NEXT: bl log2f ; PC64LE9-NEXT: bl log2f
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -4750,18 +4690,14 @@ define <1 x float> @constrained_vector_rint_v1f32() #0 {
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI75_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI75_0@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI75_0@toc@l(3) ; PC64LE-NEXT: lfs 0, .LCPI75_0@toc@l(3)
; PC64LE-NEXT: xsrdpic 0, 0 ; PC64LE-NEXT: xsrdpic 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_rint_v1f32: ; PC64LE9-LABEL: constrained_vector_rint_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI75_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI75_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI75_0@toc@l(3) ; PC64LE9-NEXT: lfs 0, .LCPI75_0@toc@l(3)
; PC64LE9-NEXT: xsrdpic 0, 0 ; PC64LE9-NEXT: xsrdpic 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rint = call <1 x float> @llvm.experimental.constrained.rint.v1f32( %rint = call <1 x float> @llvm.experimental.constrained.rint.v1f32(
@ -4934,8 +4870,6 @@ define <1 x float> @constrained_vector_nearbyint_v1f32() #0 {
; PC64LE-NEXT: lfs 1, .LCPI80_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI80_0@toc@l(3)
; PC64LE-NEXT: bl nearbyintf ; PC64LE-NEXT: bl nearbyintf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -4950,8 +4884,6 @@ define <1 x float> @constrained_vector_nearbyint_v1f32() #0 {
; PC64LE9-NEXT: lfs 1, .LCPI80_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI80_0@toc@l(3)
; PC64LE9-NEXT: bl nearbyintf ; PC64LE9-NEXT: bl nearbyintf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -5289,8 +5221,6 @@ define <1 x float> @constrained_vector_maxnum_v1f32() #0 {
; PC64LE-NEXT: lfs 2, .LCPI85_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI85_1@toc@l(4)
; PC64LE-NEXT: bl fmaxf ; PC64LE-NEXT: bl fmaxf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -5307,8 +5237,6 @@ define <1 x float> @constrained_vector_maxnum_v1f32() #0 {
; PC64LE9-NEXT: lfs 2, .LCPI85_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI85_1@toc@l(3)
; PC64LE9-NEXT: bl fmaxf ; PC64LE9-NEXT: bl fmaxf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -5580,8 +5508,6 @@ define <1 x float> @constrained_vector_minnum_v1f32() #0 {
; PC64LE-NEXT: lfs 2, .LCPI90_1@toc@l(4) ; PC64LE-NEXT: lfs 2, .LCPI90_1@toc@l(4)
; PC64LE-NEXT: bl fminf ; PC64LE-NEXT: bl fminf
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: xscvdpspn 0, 1
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: addi 1, 1, 32 ; PC64LE-NEXT: addi 1, 1, 32
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
@ -5598,8 +5524,6 @@ define <1 x float> @constrained_vector_minnum_v1f32() #0 {
; PC64LE9-NEXT: lfs 2, .LCPI90_1@toc@l(3) ; PC64LE9-NEXT: lfs 2, .LCPI90_1@toc@l(3)
; PC64LE9-NEXT: bl fminf ; PC64LE9-NEXT: bl fminf
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: xscvdpspn 0, 1
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: addi 1, 1, 32 ; PC64LE9-NEXT: addi 1, 1, 32
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
@ -5864,18 +5788,14 @@ define <1 x float> @constrained_vector_fptrunc_v1f64() #0 {
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI95_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI95_0@toc@ha
; PC64LE-NEXT: lfd 0, .LCPI95_0@toc@l(3) ; PC64LE-NEXT: lfd 0, .LCPI95_0@toc@l(3)
; PC64LE-NEXT: frsp 0, 0 ; PC64LE-NEXT: frsp 1, 0
; PC64LE-NEXT: xscvdpspn 0, 0
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64: ; PC64LE9-LABEL: constrained_vector_fptrunc_v1f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI95_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI95_0@toc@ha
; PC64LE9-NEXT: lfd 0, .LCPI95_0@toc@l(3) ; PC64LE9-NEXT: lfd 0, .LCPI95_0@toc@l(3)
; PC64LE9-NEXT: frsp 0, 0 ; PC64LE9-NEXT: frsp 1, 0
; PC64LE9-NEXT: xscvdpspn 0, 0
; PC64LE9-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64( %result = call <1 x float> @llvm.experimental.constrained.fptrunc.v1f32.v1f64(
@ -6027,15 +5947,13 @@ define <1 x double> @constrained_vector_fpext_v1f32() #0 {
; PC64LE-LABEL: constrained_vector_fpext_v1f32: ; PC64LE-LABEL: constrained_vector_fpext_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI99_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI99_0@toc@ha
; PC64LE-NEXT: lfs 0, .LCPI99_0@toc@l(3) ; PC64LE-NEXT: lfs 1, .LCPI99_0@toc@l(3)
; PC64LE-NEXT: xxspltd 34, 0, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_fpext_v1f32: ; PC64LE9-LABEL: constrained_vector_fpext_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI99_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI99_0@toc@ha
; PC64LE9-NEXT: lfs 0, .LCPI99_0@toc@l(3) ; PC64LE9-NEXT: lfs 1, .LCPI99_0@toc@l(3)
; PC64LE9-NEXT: xxspltd 34, 0, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32( %result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32(
@ -6137,17 +6055,13 @@ define <1 x float> @constrained_vector_ceil_v1f32() #0 {
; PC64LE-LABEL: constrained_vector_ceil_v1f32: ; PC64LE-LABEL: constrained_vector_ceil_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI103_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI103_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI103_0@toc@l ; PC64LE-NEXT: lfs 1, .LCPI103_0@toc@l(3)
; PC64LE-NEXT: lfiwzx 0, 0, 3
; PC64LE-NEXT: xxswapd 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_ceil_v1f32: ; PC64LE9-LABEL: constrained_vector_ceil_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI103_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI103_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI103_0@toc@l ; PC64LE9-NEXT: lfs 1, .LCPI103_0@toc@l(3)
; PC64LE9-NEXT: lfiwzx 0, 0, 3
; PC64LE9-NEXT: xxswapd 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32( %ceil = call <1 x float> @llvm.experimental.constrained.ceil.v1f32(
@ -6226,17 +6140,13 @@ define <1 x float> @constrained_vector_floor_v1f32() #0 {
; PC64LE-LABEL: constrained_vector_floor_v1f32: ; PC64LE-LABEL: constrained_vector_floor_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI107_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI107_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI107_0@toc@l ; PC64LE-NEXT: lfs 1, .LCPI107_0@toc@l(3)
; PC64LE-NEXT: lfiwzx 0, 0, 3
; PC64LE-NEXT: xxswapd 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_floor_v1f32: ; PC64LE9-LABEL: constrained_vector_floor_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI107_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI107_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI107_0@toc@l ; PC64LE9-NEXT: lfs 1, .LCPI107_0@toc@l(3)
; PC64LE9-NEXT: lfiwzx 0, 0, 3
; PC64LE9-NEXT: xxswapd 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32( %floor = call <1 x float> @llvm.experimental.constrained.floor.v1f32(
@ -6316,17 +6226,13 @@ define <1 x float> @constrained_vector_round_v1f32() #0 {
; PC64LE-LABEL: constrained_vector_round_v1f32: ; PC64LE-LABEL: constrained_vector_round_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI111_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI111_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI111_0@toc@l ; PC64LE-NEXT: lfs 1, .LCPI111_0@toc@l(3)
; PC64LE-NEXT: lfiwzx 0, 0, 3
; PC64LE-NEXT: xxswapd 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_round_v1f32: ; PC64LE9-LABEL: constrained_vector_round_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI111_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI111_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI111_0@toc@l ; PC64LE9-NEXT: lfs 1, .LCPI111_0@toc@l(3)
; PC64LE9-NEXT: lfiwzx 0, 0, 3
; PC64LE9-NEXT: xxswapd 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%round = call <1 x float> @llvm.experimental.constrained.round.v1f32( %round = call <1 x float> @llvm.experimental.constrained.round.v1f32(
@ -6408,17 +6314,13 @@ define <1 x float> @constrained_vector_trunc_v1f32() #0 {
; PC64LE-LABEL: constrained_vector_trunc_v1f32: ; PC64LE-LABEL: constrained_vector_trunc_v1f32:
; PC64LE: # %bb.0: # %entry ; PC64LE: # %bb.0: # %entry
; PC64LE-NEXT: addis 3, 2, .LCPI115_0@toc@ha ; PC64LE-NEXT: addis 3, 2, .LCPI115_0@toc@ha
; PC64LE-NEXT: addi 3, 3, .LCPI115_0@toc@l ; PC64LE-NEXT: lfs 1, .LCPI115_0@toc@l(3)
; PC64LE-NEXT: lfiwzx 0, 0, 3
; PC64LE-NEXT: xxswapd 34, 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_trunc_v1f32: ; PC64LE9-LABEL: constrained_vector_trunc_v1f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: addis 3, 2, .LCPI115_0@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI115_0@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI115_0@toc@l ; PC64LE9-NEXT: lfs 1, .LCPI115_0@toc@l(3)
; PC64LE9-NEXT: lfiwzx 0, 0, 3
; PC64LE9-NEXT: xxswapd 34, 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32( %trunc = call <1 x float> @llvm.experimental.constrained.trunc.v1f32(