forked from OSchip/llvm-project
[PowerPC] Generate VSX version of splat word
This patch corresponds to review: http://reviews.llvm.org/D18592 It allows the PPC back end to generate the xxspltw instruction where we previously only emitted vspltw. llvm-svn: 268516
This commit is contained in:
Nemanja Ivanovic
parent
38bd217d0c
commit
1a2b2f03e7
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@ -1014,6 +1014,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
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case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
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case PPCISD::VPERM: return "PPCISD::VPERM";
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case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
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case PPCISD::CMPB: return "PPCISD::CMPB";
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case PPCISD::Hi: return "PPCISD::Hi";
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case PPCISD::Lo: return "PPCISD::Lo";
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@ -7419,6 +7420,16 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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EVT VT = Op.getValueType();
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bool isLittleEndian = Subtarget.isLittleEndian();
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if (Subtarget.hasVSX()) {
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if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) {
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int SplatIdx = PPC::getVSPLTImmediate(SVOp, 4, DAG);
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SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
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SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv,
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DAG.getConstant(SplatIdx, dl, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Splat);
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}
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}
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if (Subtarget.hasQPX()) {
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if (VT.getVectorNumElements() != 4)
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return SDValue();
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@ -61,6 +61,10 @@ namespace llvm {
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///
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VPERM,
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/// XXSPLT - The PPC VSX splat instructions
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///
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XXSPLT,
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/// The CMPB instruction (takes two operands of i32 or i64).
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CMPB,
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@ -31,6 +31,10 @@ def SDT_PPCvperm : SDTypeProfile<1, 3, [
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SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
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]>;
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def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>,
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SDTCisVec<1>, SDTCisInt<2>
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]>;
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def SDT_PPCvcmp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
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]>;
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@ -141,6 +145,7 @@ def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>;
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def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>;
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def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
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def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>;
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def PPCqvfperm : SDNode<"PPCISD::QVFPERM", SDT_PPCqvfperm, []>;
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def PPCqvgpci : SDNode<"PPCISD::QVGPCI", SDT_PPCqvgpci, []>;
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@ -775,7 +775,9 @@ let Uses = [RM] in {
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"xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, []>;
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def XXSPLTW : XX2Form_2<60, 164,
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(outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
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"xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>;
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"xxspltw $XT, $XB, $UIM", IIC_VecPerm,
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[(set v4i32:$XT,
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(PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>;
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} // hasSideEffects
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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@ -407,9 +407,9 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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case PPC::VSPLTB:
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case PPC::VSPLTH:
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case PPC::VSPLTW:
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case PPC::XXSPLTW:
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// Splats are lane-sensitive, but we can use special handling
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// to adjust the source lane for the splat. This is not yet
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// implemented. When it is, we need to uncomment the following:
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// to adjust the source lane for the splat.
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SwapVector[VecIdx].IsSwappable = 1;
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SwapVector[VecIdx].SpecialHandling = SHValues::SH_SPLAT;
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break;
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@ -515,7 +515,6 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
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// permute control vectors (for shift values 1, 2, 3). However,
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// VPERM has a more restrictive register class.
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case PPC::XXSLDWI:
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case PPC::XXSPLTW:
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break;
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}
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}
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@ -806,12 +805,21 @@ void PPCVSXSwapRemoval::handleSpecialSwappables(int EntryIdx) {
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llvm_unreachable("Unexpected splat opcode");
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case PPC::VSPLTB: NElts = 16; break;
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case PPC::VSPLTH: NElts = 8; break;
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case PPC::VSPLTW: NElts = 4; break;
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case PPC::VSPLTW:
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case PPC::XXSPLTW: NElts = 4; break;
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}
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unsigned EltNo = MI->getOperand(1).getImm();
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unsigned EltNo;
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if (MI->getOpcode() == PPC::XXSPLTW)
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EltNo = MI->getOperand(2).getImm();
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else
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EltNo = MI->getOperand(1).getImm();
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EltNo = (EltNo + NElts / 2) % NElts;
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MI->getOperand(1).setImm(EltNo);
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if (MI->getOpcode() == PPC::XXSPLTW)
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MI->getOperand(2).setImm(EltNo);
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else
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MI->getOperand(1).setImm(EltNo);
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DEBUG(dbgs() << " Into: ");
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DEBUG(MI->dump());
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@ -9,7 +9,7 @@ define <4 x float> @bar(float* %p, float* %q) {
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%6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
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ret <4 x float> %6
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; CHECK: vspltw
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; CHECK: xxspltw
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; CHECK: vmrghw
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; CHECK: vsldoi
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}
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@ -87,5 +87,5 @@ entry:
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; CHECK-LABEL: @ifoo
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; CHECK: lxvd2x
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; CHECK: vspltw {{[0-9]+}}, {{[0-9]+}}, 0
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; CHECK: xxspltw {{[0-9]+}}, {{[0-9]+}}, 0
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; CHECK: stxvd2x
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@ -0,0 +1,147 @@
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; RUN: llc -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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define <4 x float> @test0f(<4 x float> %a) {
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entry:
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%0 = bitcast <4 x float> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = bitcast <16 x i8> %1 to <4 x float>
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ret <4 x float> %2
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; CHECK-LABEL: test0f
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; CHECK xxspltw: 34, 34, 3
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; CHECK-BE-LABEL: test0f
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; CHECK-BE: xxspltw 34, 34, 0
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}
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define <4 x float> @test1f(<4 x float> %a) {
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entry:
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%0 = bitcast <4 x float> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
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%2 = bitcast <16 x i8> %1 to <4 x float>
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ret <4 x float> %2
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; CHECK-LABEL: test1f
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; CHECK xxspltw: 34, 34, 2
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; CHECK-BE-LABEL: test1f
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; CHECK-BE: xxspltw 34, 34, 1
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}
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define <4 x float> @test2f(<4 x float> %a) {
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entry:
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%0 = bitcast <4 x float> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
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%2 = bitcast <16 x i8> %1 to <4 x float>
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ret <4 x float> %2
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; CHECK-LABEL: test2f
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; CHECK xxspltw: 34, 34, 1
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; CHECK-LABEL: test2f
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; CHECK-BE: xxspltw 34, 34, 2
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}
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define <4 x float> @test3f(<4 x float> %a) {
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entry:
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%0 = bitcast <4 x float> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
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%2 = bitcast <16 x i8> %1 to <4 x float>
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ret <4 x float> %2
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; CHECK-LABEL: test3f
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; CHECK xxspltw: 34, 34, 0
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; CHECK-BE-LABEL: test3f
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; CHECK-BE: xxspltw 34, 34, 3
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}
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define <4 x i32> @test0si(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test0si
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; CHECK xxspltw: 34, 34, 3
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; CHECK-BE-LABEL: test0si
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; CHECK-BE: xxspltw 34, 34, 0
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}
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define <4 x i32> @test1si(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test1si
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; CHECK xxspltw: 34, 34, 2
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; CHECK-BE-LABEL: test1si
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; CHECK-BE: xxspltw 34, 34, 1
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}
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define <4 x i32> @test2si(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test2si
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; CHECK xxspltw: 34, 34, 1
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; CHECK-BE-LABEL: test2si
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; CHECK-BE: xxspltw 34, 34, 2
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}
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define <4 x i32> @test3si(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test3si
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; CHECK xxspltw: 34, 34, 0
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; CHECK-BE-LABEL: test3si
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; CHECK-BE: xxspltw 34, 34, 3
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}
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define <4 x i32> @test0ui(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test0ui
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; CHECK xxspltw: 34, 34, 3
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; CHECK-BE-LABEL: test0ui
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; CHECK-BE: xxspltw 34, 34, 0
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}
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define <4 x i32> @test1ui(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test1ui
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; CHECK xxspltw: 34, 34, 2
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; CHECK-BE-LABEL: test1ui
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; CHECK-BE: xxspltw 34, 34, 1
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}
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define <4 x i32> @test2ui(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test2ui
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; CHECK xxspltw: 34, 34, 1
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; CHECK-BE-LABEL: test2ui
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; CHECK-BE: xxspltw 34, 34, 2
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}
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define <4 x i32> @test3ui(<4 x i32> %a) {
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entry:
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%0 = bitcast <4 x i32> %a to <16 x i8>
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
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%2 = bitcast <16 x i8> %1 to <4 x i32>
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ret <4 x i32> %2
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; CHECK-LABEL: test3ui
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; CHECK xxspltw: 34, 34, 0
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; CHECK-BE-LABEL: test3ui
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; CHECK-BE: xxspltw 34, 34, 3
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}
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