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[RegisterClassInfo] Invalidate cached information if ignoreCSRForAllocationOrder changes 

Even if CSR list is same between functions, we could have had a different
allocation order if ignoreCSRForAllocationOrder is evaluated differently.
Hence invalidate cached register class information if
ignoreCSRForAllocationOrder changes.

Patch by Srividya Karumuri <srividya_karumuri@apple.com>

Differential Revision: https://reviews.llvm.org/D126565
This commit is contained in:
Quentin Colombet 2022-06-01 17:14:03 -07:00
parent 2108f7a243
commit 1a155ee7de
2 changed files with 20 additions and 2 deletions
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4
llvm/include/llvm/CodeGen/RegisterClassInfo.h
View File

@ -60,6 +60,10 @@ class RegisterClassInfo {
// Map register alias to the callee saved Register.
SmallVector<MCPhysReg, 4> CalleeSavedAliases;
// Indicate if a specified callee saved register be in the allocation order
// exactly as written in the tablegen descriptions or listed later.
BitVector IgnoreCSRForAllocOrder;
// Reserved registers in the current MF.
BitVector Reserved;

18
llvm/lib/CodeGen/RegisterClassInfo.cpp
View File

@ -43,9 +43,11 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
bool Update = false;
MF = &mf;
auto &STI = MF->getSubtarget();
// Allocate new array the first time we see a new target.
if (MF->getSubtarget().getRegisterInfo() != TRI) {
TRI = MF->getSubtarget().getRegisterInfo();
if (STI.getRegisterInfo() != TRI) {
TRI = STI.getRegisterInfo();
RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
Update = true;
}
@ -67,6 +69,18 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
}
CalleeSavedRegs = CSR;
// Even if CSR list is same, we could have had a different allocation order
// if ignoreCSRForAllocationOrder is evaluated differently.
BitVector CSRHintsForAllocOrder(TRI->getNumRegs());
for (const MCPhysReg *I = CSR; *I; ++I)
for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI);
if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() ||
IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
Update = true;
IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
}
RegCosts = TRI->getRegisterCosts(*MF);
// Different reserved registers?