forked from OSchip/llvm-project
Revert "[AArch64][GlobalISel] Make G_USUBO legal and select it."
This reverts commit 3dedad475d.
Broke UBSan on Android:
http://lab.llvm.org:8011/#/builders/77/builds/3082
More details at: https://reviews.llvm.org/D95032
This commit is contained in:
Mitch Phillips
parent
e3a7532cc9
commit
19ec559c66
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@ -2745,8 +2745,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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}
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}
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case TargetOpcode::G_SADDO:
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case TargetOpcode::G_SADDO:
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case TargetOpcode::G_UADDO:
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case TargetOpcode::G_UADDO:
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case TargetOpcode::G_SSUBO:
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case TargetOpcode::G_SSUBO: {
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case TargetOpcode::G_USUBO: {
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// Emit the operation and get the correct condition code.
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// Emit the operation and get the correct condition code.
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MachineIRBuilder MIRBuilder(I);
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MachineIRBuilder MIRBuilder(I);
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auto OpAndCC = emitOverflowOp(Opcode, I.getOperand(0).getReg(),
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auto OpAndCC = emitOverflowOp(Opcode, I.getOperand(0).getReg(),
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@ -4377,8 +4376,6 @@ AArch64InstructionSelector::emitOverflowOp(unsigned Opcode, Register Dst,
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return std::make_pair(emitADDS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
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return std::make_pair(emitADDS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
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case TargetOpcode::G_SSUBO:
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case TargetOpcode::G_SSUBO:
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return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::VS);
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return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::VS);
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case TargetOpcode::G_USUBO:
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return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
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}
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}
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}
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}
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@ -165,8 +165,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
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getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
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getActionDefinitionsBuilder(
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getActionDefinitionsBuilder({G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO})
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{G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
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.legalFor({{s32, s1}, {s64, s1}})
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.legalFor({{s32, s1}, {s64, s1}})
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.minScalar(0, s32);
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.minScalar(0, s32);
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@ -73,44 +73,6 @@ body: |
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%5:_(s64) = G_ANYEXT %4(s8)
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%5:_(s64) = G_ANYEXT %4(s8)
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$x0 = COPY %5(s64)
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$x0 = COPY %5(s64)
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...
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---
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name: test_scalar_uaddo_32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_uaddo_32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[COPY]], [[COPY1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDO1]](s1)
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; CHECK: $w0 = COPY [[UADDO]](s32)
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; CHECK: $w1 = COPY [[ANYEXT]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32), %3:_(s1) = G_UADDO %0, %1
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%4:_(s32) = G_ANYEXT %3
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$w0 = COPY %2(s32)
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$w1 = COPY %4(s32)
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...
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---
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name: test_scalar_saddo_32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_saddo_32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[SADDO:%[0-9]+]]:_(s32), [[SADDO1:%[0-9]+]]:_(s1) = G_SADDO [[COPY]], [[COPY1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDO1]](s1)
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; CHECK: $w0 = COPY [[SADDO]](s32)
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; CHECK: $w1 = COPY [[ANYEXT]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32), %3:_(s1) = G_SADDO %0, %1
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%4:_(s32) = G_ANYEXT %3
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$w0 = COPY %2(s32)
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$w1 = COPY %4(s32)
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...
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...
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---
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---
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name: test_vector_add
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name: test_vector_add
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@ -1,59 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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---
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---
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name: test_scalar_sub_big
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_sub_big
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY2]]
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; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY3]], [[USUBO1]]
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; CHECK: $x0 = COPY [[USUBO]](s64)
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; CHECK: $x1 = COPY [[USUBE]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = COPY $x2
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%3:_(s64) = COPY $x3
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%4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
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%5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)
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%6:_(s128) = G_SUB %4, %5
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%7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6(s128)
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$x0 = COPY %7(s64)
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$x1 = COPY %8(s64)
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...
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---
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name: test_scalar_sub_big_nonpow2
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_sub_big_nonpow2
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
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; CHECK: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[COPY1]], [[COPY2]], [[USUBO1]]
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; CHECK: [[USUBE2:%[0-9]+]]:_(s64), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[COPY2]], [[COPY3]], [[USUBE1]]
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; CHECK: $x0 = COPY [[USUBO]](s64)
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; CHECK: $x1 = COPY [[USUBE]](s64)
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; CHECK: $x2 = COPY [[USUBE2]](s64)
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%0:_(s64) = COPY $x0
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%1:_(s64) = COPY $x1
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%2:_(s64) = COPY $x2
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%3:_(s64) = COPY $x3
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%4:_(s192) = G_MERGE_VALUES %0(s64), %1(s64), %2(s64)
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%5:_(s192) = G_MERGE_VALUES %1(s64), %2(s64), %3(s64)
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%6:_(s192) = G_SUB %4, %5
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%7:_(s64), %8:_(s64), %9:_(s64) = G_UNMERGE_VALUES %6(s192)
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$x0 = COPY %7(s64)
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$x1 = COPY %8(s64)
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$x2 = COPY %9(s64)
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...
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---
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name: test_scalar_sub_small
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name: test_scalar_sub_small
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body: |
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body: |
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bb.0.entry:
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bb.0.entry:
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@ -74,41 +21,3 @@ body: |
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$x0 = COPY %5(s64)
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$x0 = COPY %5(s64)
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...
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...
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---
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name: test_scalar_usubo_32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_usubo_32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[COPY]], [[COPY1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBO1]](s1)
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; CHECK: $w0 = COPY [[USUBO]](s32)
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; CHECK: $w1 = COPY [[ANYEXT]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32), %3:_(s1) = G_USUBO %0, %1
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%4:_(s32) = G_ANYEXT %3
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$w0 = COPY %2(s32)
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$w1 = COPY %4(s32)
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...
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---
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name: test_scalar_ssubo_32
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_scalar_ssubo_32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; CHECK: [[SSUBO:%[0-9]+]]:_(s32), [[SSUBO1:%[0-9]+]]:_(s1) = G_SSUBO [[COPY]], [[COPY1]]
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBO1]](s1)
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; CHECK: $w0 = COPY [[SSUBO]](s32)
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; CHECK: $w1 = COPY [[ANYEXT]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32), %3:_(s1) = G_SSUBO %0, %1
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%4:_(s32) = G_ANYEXT %3
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$w0 = COPY %2(s32)
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$w1 = COPY %4(s32)
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...
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@ -300,9 +300,8 @@
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_USUBO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: G_USUBO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
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# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
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# DEBUG-NEXT: G_USUBE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: G_USUBE (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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# DEBUG-NEXT: .. the first uncovered type index: 2, OK
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@ -1,166 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-uknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
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...
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---
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name: saddo_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: saddo_s32
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
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; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
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; CHECK: $w0 = COPY [[UBFMWri1]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%3:gpr(s32), %4:gpr(s1) = G_SADDO %0, %1
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%5:gpr(s8) = G_ZEXT %4(s1)
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%6:gpr(s32) = G_ZEXT %5(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: saddo_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: saddo_s64
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
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; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
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; CHECK: $w0 = COPY [[UBFMWri1]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = COPY $x1
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%3:gpr(s64), %4:gpr(s1) = G_SADDO %0, %1
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%5:gpr(s8) = G_ZEXT %4(s1)
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%6:gpr(s32) = G_ZEXT %5(s8)
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$w0 = COPY %6(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: saddo_s32_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; Check that we get ADDSWri when we can fold in a constant.
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;
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; CHECK-LABEL: name: saddo_s32_imm
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %copy:gpr32sp = COPY $w0
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; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
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|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy:gpr(s32) = COPY $w0
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 16
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy, %constant
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: saddo_s32_shifted
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get ADDSWrs when we can fold in a shift.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: saddo_s32_shifted
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy1:gpr32 = COPY $w0
|
|
||||||
; CHECK: %copy2:gpr32 = COPY $w1
|
|
||||||
; CHECK: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy1:gpr(s32) = COPY $w0
|
|
||||||
%copy2:gpr(s32) = COPY $w1
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 16
|
|
||||||
%shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy1, %shift
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: saddo_s32_neg_imm
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get SUBSWri when we can fold in a negative constant.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: saddo_s32_neg_imm
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy:gpr32sp = COPY $w0
|
|
||||||
; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy:gpr(s32) = COPY $w0
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 -16
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_SADDO %copy, %constant
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: saddo_arith_extended
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $x0
|
|
||||||
; Check that we get ADDSXrx.
|
|
||||||
; CHECK-LABEL: name: saddo_arith_extended
|
|
||||||
; CHECK: liveins: $w0, $x0
|
|
||||||
; CHECK: %reg0:gpr64sp = COPY $x0
|
|
||||||
; CHECK: %reg1:gpr32 = COPY $w0
|
|
||||||
; CHECK: %add:gpr64 = ADDSXrx %reg0, %reg1, 18, implicit-def $nzcv
|
|
||||||
; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $x0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $x0
|
|
||||||
%reg0:gpr(s64) = COPY $x0
|
|
||||||
%reg1:gpr(s32) = COPY $w0
|
|
||||||
%ext:gpr(s64) = G_ZEXT %reg1(s32)
|
|
||||||
%cst:gpr(s64) = G_CONSTANT i64 2
|
|
||||||
%shift:gpr(s64) = G_SHL %ext, %cst(s64)
|
|
||||||
%add:gpr(s64), %flags:gpr(s1) = G_SADDO %reg0, %shift
|
|
||||||
$x0 = COPY %add(s64)
|
|
||||||
RET_ReallyLR implicit $x0
|
|
||||||
|
|
@ -1,166 +0,0 @@
|
||||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
||||||
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-uknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: ssubo_s32
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
|
|
||||||
; CHECK-LABEL: name: ssubo_s32
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
||||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
||||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
|
||||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
|
|
||||||
; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
|
|
||||||
; CHECK: $w0 = COPY [[UBFMWri1]]
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%0:gpr(s32) = COPY $w0
|
|
||||||
%1:gpr(s32) = COPY $w1
|
|
||||||
%3:gpr(s32), %4:gpr(s1) = G_SSUBO %0, %1
|
|
||||||
%5:gpr(s8) = G_ZEXT %4(s1)
|
|
||||||
%6:gpr(s32) = G_ZEXT %5(s8)
|
|
||||||
$w0 = COPY %6(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: ssubo_s64
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $x0, $x1, $x2
|
|
||||||
|
|
||||||
; CHECK-LABEL: name: ssubo_s64
|
|
||||||
; CHECK: liveins: $x0, $x1, $x2
|
|
||||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
||||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
|
||||||
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
|
||||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
|
|
||||||
; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
|
|
||||||
; CHECK: $w0 = COPY [[UBFMWri1]]
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%0:gpr(s64) = COPY $x0
|
|
||||||
%1:gpr(s64) = COPY $x1
|
|
||||||
%3:gpr(s64), %4:gpr(s1) = G_SSUBO %0, %1
|
|
||||||
%5:gpr(s8) = G_ZEXT %4(s1)
|
|
||||||
%6:gpr(s32) = G_ZEXT %5(s8)
|
|
||||||
$w0 = COPY %6(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: ssubo_s32_imm
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get ADDSWri when we can fold in a constant.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: ssubo_s32_imm
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy:gpr32sp = COPY $w0
|
|
||||||
; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy:gpr(s32) = COPY $w0
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 16
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: ssubo_s32_shifted
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get ADDSWrs when we can fold in a shift.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: ssubo_s32_shifted
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy1:gpr32 = COPY $w0
|
|
||||||
; CHECK: %copy2:gpr32 = COPY $w1
|
|
||||||
; CHECK: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy1:gpr(s32) = COPY $w0
|
|
||||||
%copy2:gpr(s32) = COPY $w1
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 16
|
|
||||||
%shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy1, %shift
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: ssubo_s32_neg_imm
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get SUBSWri when we can fold in a negative constant.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: ssubo_s32_neg_imm
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy:gpr32sp = COPY $w0
|
|
||||||
; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy:gpr(s32) = COPY $w0
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 -16
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: ssubo_arith_extended
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $x0
|
|
||||||
; Check that we get ADDSXrx.
|
|
||||||
; CHECK-LABEL: name: ssubo_arith_extended
|
|
||||||
; CHECK: liveins: $w0, $x0
|
|
||||||
; CHECK: %reg0:gpr64sp = COPY $x0
|
|
||||||
; CHECK: %reg1:gpr32 = COPY $w0
|
|
||||||
; CHECK: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
|
|
||||||
; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
|
|
||||||
; CHECK: $x0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $x0
|
|
||||||
%reg0:gpr(s64) = COPY $x0
|
|
||||||
%reg1:gpr(s32) = COPY $w0
|
|
||||||
%ext:gpr(s64) = G_ZEXT %reg1(s32)
|
|
||||||
%cst:gpr(s64) = G_CONSTANT i64 2
|
|
||||||
%shift:gpr(s64) = G_SHL %ext, %cst(s64)
|
|
||||||
%add:gpr(s64), %flags:gpr(s1) = G_SSUBO %reg0, %shift
|
|
||||||
$x0 = COPY %add(s64)
|
|
||||||
RET_ReallyLR implicit $x0
|
|
||||||
|
|
@ -1,166 +0,0 @@
|
||||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
||||||
# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-uknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: usubo_s32
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
|
|
||||||
; CHECK-LABEL: name: usubo_s32
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
|
|
||||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
|
|
||||||
; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
|
||||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
|
|
||||||
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
|
|
||||||
; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
|
|
||||||
; CHECK: $w0 = COPY [[UBFMWri1]]
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%0:gpr(s32) = COPY $w0
|
|
||||||
%1:gpr(s32) = COPY $w1
|
|
||||||
%3:gpr(s32), %4:gpr(s1) = G_USUBO %0, %1
|
|
||||||
%5:gpr(s8) = G_ZEXT %4(s1)
|
|
||||||
%6:gpr(s32) = G_ZEXT %5(s8)
|
|
||||||
$w0 = COPY %6(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: usubo_s64
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $x0, $x1, $x2
|
|
||||||
|
|
||||||
; CHECK-LABEL: name: usubo_s64
|
|
||||||
; CHECK: liveins: $x0, $x1, $x2
|
|
||||||
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
|
|
||||||
; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
|
|
||||||
; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
|
|
||||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
|
|
||||||
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
|
|
||||||
; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
|
|
||||||
; CHECK: $w0 = COPY [[UBFMWri1]]
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%0:gpr(s64) = COPY $x0
|
|
||||||
%1:gpr(s64) = COPY $x1
|
|
||||||
%3:gpr(s64), %4:gpr(s1) = G_USUBO %0, %1
|
|
||||||
%5:gpr(s8) = G_ZEXT %4(s1)
|
|
||||||
%6:gpr(s32) = G_ZEXT %5(s8)
|
|
||||||
$w0 = COPY %6(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: usubo_s32_imm
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get ADDSWri when we can fold in a constant.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: usubo_s32_imm
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy:gpr32sp = COPY $w0
|
|
||||||
; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy:gpr(s32) = COPY $w0
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 16
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: usubo_s32_shifted
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get ADDSWrs when we can fold in a shift.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: usubo_s32_shifted
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy1:gpr32 = COPY $w0
|
|
||||||
; CHECK: %copy2:gpr32 = COPY $w1
|
|
||||||
; CHECK: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy1:gpr(s32) = COPY $w0
|
|
||||||
%copy2:gpr(s32) = COPY $w1
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 16
|
|
||||||
%shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy1, %shift
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: usubo_s32_neg_imm
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $w1, $x2
|
|
||||||
; Check that we get SUBSWri when we can fold in a negative constant.
|
|
||||||
;
|
|
||||||
; CHECK-LABEL: name: usubo_s32_neg_imm
|
|
||||||
; CHECK: liveins: $w0, $w1, $x2
|
|
||||||
; CHECK: %copy:gpr32sp = COPY $w0
|
|
||||||
; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
|
|
||||||
; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
|
|
||||||
; CHECK: $w0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $w0
|
|
||||||
%copy:gpr(s32) = COPY $w0
|
|
||||||
%constant:gpr(s32) = G_CONSTANT i32 -16
|
|
||||||
%add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
|
|
||||||
$w0 = COPY %add(s32)
|
|
||||||
RET_ReallyLR implicit $w0
|
|
||||||
|
|
||||||
...
|
|
||||||
---
|
|
||||||
name: usubo_arith_extended
|
|
||||||
alignment: 4
|
|
||||||
legalized: true
|
|
||||||
regBankSelected: true
|
|
||||||
tracksRegLiveness: true
|
|
||||||
body: |
|
|
||||||
bb.1.entry:
|
|
||||||
liveins: $w0, $x0
|
|
||||||
; Check that we get ADDSXrx.
|
|
||||||
; CHECK-LABEL: name: usubo_arith_extended
|
|
||||||
; CHECK: liveins: $w0, $x0
|
|
||||||
; CHECK: %reg0:gpr64sp = COPY $x0
|
|
||||||
; CHECK: %reg1:gpr32 = COPY $w0
|
|
||||||
; CHECK: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
|
|
||||||
; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
|
|
||||||
; CHECK: $x0 = COPY %add
|
|
||||||
; CHECK: RET_ReallyLR implicit $x0
|
|
||||||
%reg0:gpr(s64) = COPY $x0
|
|
||||||
%reg1:gpr(s32) = COPY $w0
|
|
||||||
%ext:gpr(s64) = G_ZEXT %reg1(s32)
|
|
||||||
%cst:gpr(s64) = G_CONSTANT i64 2
|
|
||||||
%shift:gpr(s64) = G_SHL %ext, %cst(s64)
|
|
||||||
%add:gpr(s64), %flags:gpr(s1) = G_USUBO %reg0, %shift
|
|
||||||
$x0 = COPY %add(s64)
|
|
||||||
RET_ReallyLR implicit $x0
|
|
||||||
Loading…
Reference in New Issue