forked from OSchip/llvm-project
Revert two bad commits.
Summary: I forgot to squash git commits before doing an svn dcommit of D12219. Reverting, and re-submitting. Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D12298 llvm-svn: 245886
This commit is contained in:
parent
5cd113df01
commit
19c2e6634d
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@ -44,16 +44,3 @@ void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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printInstruction(MI, OS);
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printInstruction(MI, OS);
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printAnnotation(OS, Annot);
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printAnnotation(OS, Annot);
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}
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}
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void WebAssemblyInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg())
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O << getRegisterName(Op.getReg());
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else if (Op.isImm())
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O << '#' << Op.getImm();
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else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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Op.getExpr()->print(O, &MAI);
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}
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}
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@ -32,9 +32,6 @@ public:
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void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
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void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
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const MCSubtargetInfo &STI) override;
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const MCSubtargetInfo &STI) override;
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// Used by tblegen code.
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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// Autogenerated by tblgen.
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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void printInstruction(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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static const char *getRegisterName(unsigned RegNo);
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@ -85,7 +85,6 @@ static SmallString<32> Name(const WebAssemblyInstrInfo *TII,
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}
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}
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void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
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SmallString<128> Str;
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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raw_svector_ostream OS(Str);
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@ -1,19 +0,0 @@
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//- WebAssemblyISD.def - WebAssembly ISD ---------------------------*- C++ -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file describes the various WebAssembly ISD node types.
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///
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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HANDLE_NODETYPE(CALL)
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HANDLE_NODETYPE(RETURN)
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HANDLE_NODETYPE(ARGUMENT)
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@ -19,7 +19,6 @@
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#include "WebAssemblyTargetMachine.h"
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#include "WebAssemblyTargetMachine.h"
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#include "WebAssemblyTargetObjectFile.h"
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#include "WebAssemblyTargetObjectFile.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/DiagnosticInfo.h"
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@ -165,13 +164,9 @@ MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
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const char *
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const char *
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WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
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WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
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switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
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case WebAssemblyISD::FIRST_NUMBER:
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case WebAssemblyISD::FIRST_NUMBER: break;
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break;
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case WebAssemblyISD::RETURN: return "WebAssemblyISD::RETURN";
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#define HANDLE_NODETYPE(NODE) \
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case WebAssemblyISD::ARGUMENT: return "WebAssemblyISD::ARGUMENT";
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case WebAssemblyISD::NODE: \
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return "WebAssemblyISD::" #NODE;
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#include "WebAssemblyISD.def"
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#undef HANDLE_NODETYPE
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}
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}
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return nullptr;
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return nullptr;
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}
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}
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@ -190,6 +185,7 @@ static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
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DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
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DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
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}
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}
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<<<<<<< HEAD
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SDValue
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SDValue
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WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
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WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SmallVectorImpl<SDValue> &InVals) const {
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@ -209,6 +205,7 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
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SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
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SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
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SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
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Type *retTy = CLI.RetTy;
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bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
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bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
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if (IsStructRet)
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if (IsStructRet)
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fail(DL, DAG, "WebAssembly doesn't support struct return yet");
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fail(DL, DAG, "WebAssembly doesn't support struct return yet");
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@ -216,6 +213,7 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
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fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
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fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
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SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
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SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
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ArgListTy &Args = CLI.getArgs();
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bool IsVarArg = CLI.IsVarArg;
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bool IsVarArg = CLI.IsVarArg;
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if (IsVarArg)
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if (IsVarArg)
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fail(DL, DAG, "WebAssembly doesn't support varargs yet");
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fail(DL, DAG, "WebAssembly doesn't support varargs yet");
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@ -225,33 +223,33 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
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unsigned NumBytes = CCInfo.getNextStackOffset();
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unsigned NumBytes = CCInfo.getNextStackOffset();
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auto PtrVT = getPointerTy(MF.getDataLayout());
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auto PtrVT = getPointerTy(MF.getDataLayout());
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auto Zero = DAG.getConstant(0, DL, PtrVT, true);
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auto Zero = DAG.getConstant(0, CLI.DL, PtrVT, true);
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auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
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auto NB = DAG.getConstant(NumBytes, CLI.DL, PtrVT, true);
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Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
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Chain = DAG.getCALLSEQ_START(Chain, NB, CLI.DL);
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SmallVector<SDValue, 16> Ops;
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SmallVector<SDValue, 16> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.push_back(CLI.Callee);
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Ops.append(OutVals.begin(), OutVals.end());
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Ops.append(CLI.OutVals.begin(), CLI.OutVals.end());
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SmallVector<EVT, 8> Tys;
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SmallVector<EVT, 8> Tys;
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for (const auto &In : Ins)
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for (const auto &In : CLI.Ins)
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Tys.push_back(In.VT);
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Tys.push_back(In.VT);
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Tys.push_back(MVT::Other);
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Tys.push_back(MVT::Other);
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SDVTList TyList = DAG.getVTList(Tys);
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SDVTList TyList = CLI.DAG.getVTList(Tys);
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SDValue Res = DAG.getNode(WebAssemblyISD::CALL, DL, TyList, Ops);
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SDValue Res = CLI.DAG.getNode(WebAssemblyISD::CALL, CLI.DL, TyList, Ops);
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if (!Ins.empty()) {
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InVals.push_back(Res);
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InVals.push_back(Res);
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Chain = Res.getValue(1);
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Chain = Res.getValue(1);
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}
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// FIXME: handle CLI.RetSExt and CLI.RetZExt?
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// FIXME: handle CLI.RetSExt and CLI.RetZExt?
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Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
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Chain = CLI.DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), CLI.DL);
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return Chain;
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return Chain;
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}
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}
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=======
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>>>>>>> parent of 03685a9... call
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bool WebAssemblyTargetLowering::CanLowerReturn(
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bool WebAssemblyTargetLowering::CanLowerReturn(
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CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
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CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
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const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
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@ -24,9 +24,9 @@ namespace WebAssemblyISD {
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enum NodeType : unsigned {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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#define HANDLE_NODETYPE(NODE) NODE,
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RETURN,
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#include "WebAssemblyISD.def"
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ARGUMENT,
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#undef HANDLE_NODETYPE
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// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
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// add memory opcodes starting at ISD::FIRST_TARGET_MEMORY_OPCODE here...
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};
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};
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@ -52,9 +52,6 @@ private:
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const char *getTargetNodeName(unsigned Opcode) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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@ -12,29 +12,6 @@
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///
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// The call sequence start/end LLVM-isms isn't useful to WebAssembly since it's
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// a virtual ISA.
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// FIXME make noop?
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//def : Pat<(WebAssemblycallseq_start timm), (i32 (IMPLICIT_DEF))>;
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//def : Pat<(WebAssemblycallseq_end timm, timm), (i32 (IMPLICIT_DEF))>;
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def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
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def SDT_WebAssemblyCallSeqEnd :
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SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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def WebAssemblycallseq_start :
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SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def WebAssemblycallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def : Pseudo<(outs), (ins i64imm:$amt),
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[(WebAssemblycallseq_start timm:$amt)],
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"#ADJCALLSTACKDOWN $amt">;
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def : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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[(WebAssemblycallseq_end timm:$amt1, timm:$amt2)],
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"#ADJCALLSTACKUP $amt1 $amt2">;
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/*
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/*
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* TODO(jfb): Add the following.
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* TODO(jfb): Add the following.
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*
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*
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@ -12,7 +12,7 @@
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///
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// WebAssembly Instruction Format.
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// WebAssembly Instruction Format
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class WebAssemblyInst<string cstr> : Instruction {
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class WebAssemblyInst<string cstr> : Instruction {
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field bits<0> Inst; // Instruction encoding.
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field bits<0> Inst; // Instruction encoding.
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let Namespace = "WebAssembly";
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let Namespace = "WebAssembly";
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let Constraints = cstr;
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let Constraints = cstr;
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}
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}
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// Normal instructions.
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// Normal instructions
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class I<dag oops, dag iops, list<dag> pattern, string cstr = "">
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class I<dag oops, dag iops, list<dag> pattern, string cstr = "">
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: WebAssemblyInst<cstr> {
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: WebAssemblyInst<cstr> {
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dag OutOperandList = oops;
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dag OutOperandList = oops;
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@ -28,14 +28,6 @@ class I<dag oops, dag iops, list<dag> pattern, string cstr = "">
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let Pattern = pattern;
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let Pattern = pattern;
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}
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}
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// Pseudo instructions.
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class Pseudo<dag oops, dag iops, list<dag> pattern, string asmstr,
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string cstr = "">
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: I<oops, iops, pattern, cstr> {
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let isPseudo = 1;
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let AsmString = asmstr;
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}
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// Unary and binary instructions, for the local types that WebAssembly supports.
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// Unary and binary instructions, for the local types that WebAssembly supports.
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multiclass UnaryInt<SDNode node> {
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multiclass UnaryInt<SDNode node> {
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def _I32 : I<(outs Int32:$dst), (ins Int32:$src),
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def _I32 : I<(outs Int32:$dst), (ins Int32:$src),
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@ -5,14 +5,13 @@
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target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
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target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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target triple = "wasm32-unknown-unknown"
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declare void @void_nullary()
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declare void @nullary()
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declare void @int32_nullary()
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; CHECK-LABEL: call_void_nullary:
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; CHECK-LABEL: call_nullary:
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; CHECK-NEXT: (call @foo)
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; CHECK-NEXT: (call @foo)
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; CHECK-NEXT: (return)
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; CHECK-NEXT: (return)
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define void @call_void_nullary() {
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define void @call_nullary() {
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call void @void_nullary()
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call void @nullary()
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ret void
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ret void
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}
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}
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